JP2005129656A - Surface-mounting electronic circuit unit - Google Patents

Surface-mounting electronic circuit unit Download PDF

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JP2005129656A
JP2005129656A JP2003362241A JP2003362241A JP2005129656A JP 2005129656 A JP2005129656 A JP 2005129656A JP 2003362241 A JP2003362241 A JP 2003362241A JP 2003362241 A JP2003362241 A JP 2003362241A JP 2005129656 A JP2005129656 A JP 2005129656A
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solder
circuit board
circuit unit
electronic circuit
penetrating
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Kazumasa Koga
一正 古賀
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a surface-mounting electronic circuit unit which does not include a fault by soldering at the time of surface mounting and ensures higher surface mounting process. <P>SOLUTION: The surface-mounting electronic circuit unit shields with an insulating film 8 between the immediately adjacent solder 7 and land 3 because the insulating film 8 is provided over the lower surface of the solder 7 and the lower surface 1b of the circuit board 1 located near the lower surface of the solder 7. Accordingly, when the circuit board 1 is surface-mounted to a mother board, the solder 7 and the land 3 does not become conductive with the solder 7 at the time of surface mounting, and a fault of solder 7 can be eliminated at the time of surface mounting, resulting in reliable soldering process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は電圧制御発振器等に使用して好適な面実装型電子回路ユニットに関する。   The present invention relates to a surface mount electronic circuit unit suitable for use in a voltage controlled oscillator or the like.

従来の面実装型電子回路ユニットの図面を説明すると、図10は従来の面実装型電子回路ユニットの斜視図、図11は従来の面実装型電子回路ユニットの下面図、図12は従来の面実装型電子回路ユニットの要部断面図である。   FIG. 10 is a perspective view of a conventional surface-mount electronic circuit unit, FIG. 11 is a bottom view of the conventional surface-mount electronic circuit unit, and FIG. 12 is a conventional surface. It is principal part sectional drawing of a mounting type electronic circuit unit.

次に、従来の面実装型電子回路ユニットの構成を図10〜図12に基づいて説明すると、回路基板51の上面51aには、配線パターン52が形成されると共に、回路基板51の下面51bには、複数個のランド部53が設けられている。   Next, the configuration of a conventional surface mount electronic circuit unit will be described with reference to FIGS. 10 to 12. A wiring pattern 52 is formed on the upper surface 51 a of the circuit board 51 and the lower surface 51 b of the circuit board 51. A plurality of land portions 53 are provided.

また、回路基板51の端面51cには、上下方向に貫通する切り欠き部51dが設けられると共に、この切り欠き部51dの壁面には、導電体54が設けられており、そして、配線パターン52上には、種々の電子部品55が搭載されて、所望の電気回路が形成されている。   Further, the end surface 51c of the circuit board 51 is provided with a notch portion 51d penetrating in the vertical direction, and a conductor 54 is provided on the wall surface of the notch portion 51d. A variety of electronic components 55 are mounted to form a desired electric circuit.

金属製の箱形のカバー56は、電子部品55を覆うように配置され、その取付脚56aが切り欠き部51d内に挿入された状態で、導電体54に半田57付けされて、従来の面実装型電子回路ユニットが構成されている。(例えば、特許文献1参照)   The metal box-shaped cover 56 is disposed so as to cover the electronic component 55, and with the mounting leg 56a inserted into the cutout portion 51d, the metal box-shaped cover 56 is soldered 57 to the conductor 54, and the conventional surface. A mounting electronic circuit unit is configured. (For example, see Patent Document 1)

このような構成を有する従来の面実装型電子回路ユニットは、図11,図12に示すように、取付脚56aを取り付けるための半田57,及び導電体54の下端は、回路基板51の下面51bから露出している。   As shown in FIGS. 11 and 12, the conventional surface-mount type electronic circuit unit having such a configuration includes a solder 57 for mounting the mounting leg 56a and a lower end of the conductor 54 on the lower surface 51b of the circuit board 51. Is exposed from.

そして、この半田57,及び導電体54は、下面51bに設けられた信号用(ホット側)のランド部53間に配置されているが、回路基板51が小型化されるに従って、両者が近接した状態となる。   The solder 57 and the conductor 54 are disposed between the signal (hot-side) land portions 53 provided on the lower surface 51b. However, as the circuit board 51 is miniaturized, both of them approach each other. It becomes a state.

従って、従来の面実装型電子回路ユニットの回路基板51が電子機器(図示せず)のマザー基板(図示せず)上に載置され、ランド部53がマザー基板上の導電パターン(図示せず)に半田付けされて面実装された際、この半田付によって、近接状態にある半田57,及び導電体54とランド部53が導通されると言う事態を招く。   Therefore, the circuit board 51 of the conventional surface mount electronic circuit unit is placed on a mother board (not shown) of an electronic device (not shown), and the land portion 53 is a conductive pattern (not shown) on the mother board. ), The solder 57 and the conductor 54 and the land portion 53 are brought into conduction with each other due to the soldering.

特開2001−284756号公報JP 2001-284756 A

従来の面実装型電子回路ユニットは、取付脚56aを取り付けるための半田57,及び導電体54の下端が回路基板51の下面51bから露出しているため、回路基板51が小型化されるに従って、半田57,及び導電体54とランド部53間が近接した状態となり、従って、回路基板51がマザー基板に面実装された際、近接状態にある半田57,及び導電体54とランド部53が面実装時の半田によって導通する事態を生じるという問題がある。   In the conventional surface mount type electronic circuit unit, the lower end of the solder 57 for attaching the mounting leg 56a and the conductor 54 is exposed from the lower surface 51b of the circuit board 51. Therefore, as the circuit board 51 is downsized, Therefore, when the circuit board 51 is surface-mounted on the mother board, the solder 57, the conductor 54, and the land part 53 are in a state of being close to each other. There is a problem in that a situation where electrical connection is caused by solder during mounting occurs.

そこで、本発明は面実装時の半田付による不良が無く、面実装の信頼性の高い面実装型電子回路ユニットを提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a surface mounting type electronic circuit unit that is free from defects caused by soldering during surface mounting and has high surface mounting reliability.

上記課題を解決するための第1の解決手段として、上面に設けられた配線パターン、及び下面に設けられたランド部を有する回路基板と、前記配線パターン上に搭載された電子部品と、上下方向に貫通して前記回路基板に設けられた貫通部と、この貫通部の壁面に設けられた導電体と、前記電子部品を覆った状態で、前記回路基板に取り付けられた箱形のカバーとを備え、前記カバーに設けられた取付脚は、前記貫通部内に位置した状態で、前記導電体に半田付けされて取り付けられると共に、絶縁膜が前記半田の下面、及び前記半田の下面の近傍に位置する前記回路基板の下面に跨って設けられた構成とした。   As a first means for solving the above problems, a circuit pattern having a wiring pattern provided on the upper surface and a land portion provided on the lower surface, an electronic component mounted on the wiring pattern, and a vertical direction A penetrating portion provided on the circuit board, a conductor provided on a wall surface of the penetrating portion, and a box-shaped cover attached to the circuit board in a state of covering the electronic component. The mounting legs provided on the cover are soldered and attached to the conductor in a state of being located in the through portion, and an insulating film is positioned on the lower surface of the solder and in the vicinity of the lower surface of the solder. It was set as the structure provided ranging over the lower surface of the said circuit board.

また、第2の解決手段として、前記絶縁膜が半田レジスト膜で形成された構成とした。
また、第3の解決手段として、前記貫通部は、前記回路基板の端面の位置に設けられた上下方向に貫通する切り欠き部、又は/及び前記回路基板の前記端面から外れた位置に設けられた上下方向に貫通する貫通孔で形成された構成とした。
As a second solution, the insulating film is formed of a solder resist film.
Further, as a third solution, the penetrating portion is provided in a vertically extending notch portion provided at a position of the end surface of the circuit board or / and a position away from the end surface of the circuit board. It was set as the structure formed with the through-hole penetrated in the up-down direction.

本発明の面実装型電子回路ユニットは、上面に設けられた配線パターン、及び下面に設けられたランド部を有する回路基板と、配線パターン上に搭載された電子部品と、上下方向に貫通して回路基板に設けられた貫通部と、この貫通部の壁面に設けられた導電体と、電子部品を覆った状態で、回路基板に取り付けられた箱形のカバーとを備え、カバーに設けられた取付脚は、貫通部内に位置した状態で、導電体に半田付けされて取り付けられると共に、絶縁膜が半田の下面、及び半田の下面の近傍に位置する回路基板の下面に跨って設けられた構成とした。
このように、絶縁膜が半田の下面、及び半田の下面の近傍に位置する回路基板の下面に跨って設けられると、近接状態にある半田とランド部間が絶縁膜によって遮断され、従って、回路基板がマザー基板に面実装された際、半田とランド部間は、面実装時の半田によって導通することが無く、面実装時の半田付不良を無くすることが出来て、確実な半田付ができると共に、面実装の信頼性の高い面実装型電子回路ユニットを提供することができる。
The surface mount electronic circuit unit of the present invention includes a circuit board having a wiring pattern provided on the upper surface and a land portion provided on the lower surface, an electronic component mounted on the wiring pattern, and vertically penetrating. A through-hole provided in the circuit board, a conductor provided on the wall surface of the through-hole, and a box-shaped cover attached to the circuit board in a state of covering the electronic component are provided in the cover. The mounting legs are soldered and attached to the conductor in a state where they are located in the through portion, and the insulating film is provided across the lower surface of the solder and the lower surface of the circuit board located near the lower surface of the solder. It was.
Thus, when the insulating film is provided across the lower surface of the solder and the lower surface of the circuit board located in the vicinity of the lower surface of the solder, the insulating film is blocked between the solder and the land portion in the close state. When the board is surface-mounted on the mother board, there is no conduction between the solder and the land due to the solder at the time of surface mounting, and soldering defects at the time of surface mounting can be eliminated. In addition, it is possible to provide a surface mount electronic circuit unit with high surface mount reliability.

また、絶縁膜が半田レジスト膜で形成されたため、その構成が簡単で、安価なものが得られる。   Further, since the insulating film is formed of a solder resist film, the structure is simple and an inexpensive one can be obtained.

また、貫通部は、回路基板の端面の位置に設けられた上下方向に貫通する切り欠き部、又は/及び回路基板の端面から外れた位置に設けられた上下方向に貫通する貫通孔で形成されたため、その構成が簡単であると共に、大版基板の状態で、絶縁膜の形成が可能となって、生産性の良好なものが得られる。   Further, the through portion is formed by a notch portion penetrating in the vertical direction provided at the position of the end face of the circuit board or / and a through hole penetrating in the vertical direction provided at a position away from the end face of the circuit board. Therefore, the structure is simple, and an insulating film can be formed in the state of a large plate substrate, and a product with good productivity can be obtained.

本発明の面実装型電子回路ユニットの図面を説明すると、図1は本発明の面実装型電子回路ユニットの第1実施例に係る平面図、図2は本発明の面実装型電子回路ユニットの第1実施例に係る下面図、図3は本発明の面実装型電子回路ユニットの第1実施例に係る要部断面図である。   FIG. 1 is a plan view of a surface mount electronic circuit unit according to a first embodiment of the present invention. FIG. 2 is a plan view of the surface mount electronic circuit unit according to the present invention. FIG. 3 is a bottom view according to the first embodiment, and FIG. 3 is a cross-sectional view of an essential part according to the first embodiment of the surface mount electronic circuit unit of the present invention.

また、図4は本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第1工程を示す平面図、図5は本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第2工程を示す平面図、図6は本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第2工程を示す下面図である。   4 is a plan view showing a first step for explaining the manufacturing method according to the first embodiment of the surface mount electronic circuit unit of the present invention, and FIG. 5 is a surface mount electronic circuit unit of the present invention. FIG. 6 is a plan view showing a second step for explaining the manufacturing method according to the first embodiment of the present invention, and FIG. 6 shows the manufacturing method according to the first embodiment of the surface mount electronic circuit unit of the present invention. It is a bottom view which shows the 2nd process for this.

また、図7は本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第3工程を示す下面図、図8は本発明の面実装型電子回路ユニットの第2実施例に係る下面図、図9は本発明の面実装型電子回路ユニットの第2実施例に係る要部断面図である。   7 is a bottom view showing a third step for explaining the manufacturing method according to the first embodiment of the surface mount electronic circuit unit of the present invention, and FIG. 8 is a surface mount electronic circuit unit of the present invention. FIG. 9 is a cross-sectional view of a main part according to a second embodiment of the surface mount electronic circuit unit of the present invention.

次に、本発明の面実装型電子回路ユニットの構成を図1〜図3に基づいて説明すると、絶縁樹脂や低温焼成セラミック等からなる回路基板1は、1枚、或いは複数枚が積層されて形成され、上面1aと下面1b、及び外周部に位置する端面1cと、端面1cの位置に設けられ、上下方向に貫通する切り欠き部からなる貫通部1dとを有する。   Next, the configuration of the surface mount electronic circuit unit according to the present invention will be described with reference to FIGS. 1 to 3. One or more circuit boards 1 made of insulating resin, low-temperature fired ceramic, or the like are laminated. An upper surface 1a, a lower surface 1b, and an end surface 1c positioned on the outer peripheral portion, and a through portion 1d that is provided at a position of the end surface 1c and includes a notch that penetrates in the vertical direction.

この回路基板1の上面1aには、配線パターン2が形成され、また、回路基板1の下面1bには、信号用(ホット側)の複数個のランド部3が設けられると共に、貫通部1dの壁面には、導電体4が設けられ、そして、配線パターン2上には、種々の電子部品5が搭載されて、所望の電気回路が形成されている。   A wiring pattern 2 is formed on the upper surface 1a of the circuit board 1, and a plurality of land portions 3 for signals (hot side) are provided on the lower surface 1b of the circuit board 1, and a through-hole 1d is formed. A conductor 4 is provided on the wall surface, and various electronic components 5 are mounted on the wiring pattern 2 to form a desired electric circuit.

金属製の箱形のカバー6は、箱形の覆い部6aと、この覆い部6aから下方に延びる取付脚6bを有し、このカバー6は、覆い部6aで電子部品5を覆い、取付脚6bが貫通部1d内に挿入された状態で、導電体4に半田7付けされている。   The metal box-shaped cover 6 includes a box-shaped cover portion 6a and a mounting leg 6b extending downward from the cover portion 6a. The cover 6 covers the electronic component 5 with the cover portion 6a, and the mounting leg. Solder 7 is attached to the conductor 4 in a state where 6b is inserted into the through portion 1d.

絶縁膜8は、半田レジスト膜等の絶縁材で形成され、半田7の下面と、この半田7の下面の近傍に位置する回路基板1の下面1bに跨って設けられて、半田7の下面が絶縁膜8によって覆われた状態となっており、この絶縁膜8によって、互いに近接した状態にある半田7とランド部3との間が遮断された状態となっている。   The insulating film 8 is formed of an insulating material such as a solder resist film, and is provided across the lower surface of the solder 7 and the lower surface 1 b of the circuit board 1 located in the vicinity of the lower surface of the solder 7. The insulating film 8 is in a state of being covered, and the insulating film 8 blocks the solder 7 and the land portion 3 that are in close proximity to each other.

この第1実施例(特に図3参照)で示すように、導電体4の下端が回路基板1の下面1bに露出している場合は、この導電体4の下端が絶縁膜8によって覆われていること勿論であるが、導電体4の下端が貫通部1dの壁面の途中となったものが存在し、この場合、半田7が下面1b側に流れ落ちた状態となり、この半田7の下面が絶縁膜8によって覆われた状態となる。   As shown in the first embodiment (particularly, see FIG. 3), when the lower end of the conductor 4 is exposed on the lower surface 1b of the circuit board 1, the lower end of the conductor 4 is covered with the insulating film 8. Of course, there is a conductor 4 whose lower end is in the middle of the wall surface of the penetrating portion 1d. In this case, the solder 7 flows down to the lower surface 1b, and the lower surface of the solder 7 is insulated. The film is covered with the film 8.

また、回路基板1の下面1bには、ランド部3を露出した状態で半田レジスト膜(図示せず)が設けられ、この状態で、取付脚6bと導電体4の半田7付けを行い、しかる後、絶縁膜8を形成したり、或いは、取付脚6bと導電体4の半田7付けを行った後、ランド部3を除く下面1bの全体に半田レジスト膜を形成して、絶縁膜8を同時に形成するようにしても良い。   In addition, a solder resist film (not shown) is provided on the lower surface 1b of the circuit board 1 with the land portions 3 exposed, and in this state, the mounting legs 6b and the conductors 4 are soldered 7. Thereafter, the insulating film 8 is formed, or the mounting legs 6b and the conductor 4 are soldered 7, and then a solder resist film is formed on the entire lower surface 1b except for the land portion 3, and the insulating film 8 is formed. You may make it form simultaneously.

このような構成によって本発明の面実装型電子回路ユニットが形成され、本発明の面実装型電子回路ユニットは、ここでは図示しないが、回路基板1が電子機器(図示せず)のマザー基板(図示せず)上に載置され、ランド部3がマザー基板に設けられた導電パターン(図示せず)に半田付けされて、面実装されるようになっている。   With this configuration, the surface mount electronic circuit unit of the present invention is formed. The surface mount electronic circuit unit of the present invention is not shown here, but the circuit board 1 is a mother board (not shown) of an electronic device (not shown). The land portion 3 is soldered to a conductive pattern (not shown) provided on the mother board and surface-mounted.

そして、回路基板1は、小型化されればされる程、半田7と信号用(ホット側)のランド部3間が接近した状態となるが、半田7の下面が絶縁膜8で覆われているため、回路基板1がマザー基板に面実装された際、半田7とランド部3間は、面実装時の半田によって導通することが無く、面実装時の半田付不良を無くすることが出来て、確実な半田付ができると共に、面実装の信頼性の高いものが得られる。   As the circuit board 1 is further reduced in size, the solder 7 and the signal (hot side) land 3 are closer to each other, but the lower surface of the solder 7 is covered with the insulating film 8. Therefore, when the circuit board 1 is surface-mounted on the mother board, the solder 7 and the land portion 3 are not electrically connected by the solder at the time of surface mounting, and the soldering failure at the time of surface mounting can be eliminated. As a result, reliable soldering and high surface mounting reliability can be obtained.

次に、本発明の面実装型電子回路ユニットの第1実施例の製造方法を図4〜図7に基づいて説明すると、先ず、図4に示す第1工程では、複数個の回路基板1が結合された大版基板11を用意する。   Next, the manufacturing method of the first embodiment of the surface mount electronic circuit unit according to the present invention will be described with reference to FIGS. 4 to 7. First, in the first step shown in FIG. A large plate substrate 11 is prepared.

そして、この大版基板11の各回路基板(二点鎖線で囲まれた部分)1に対応した箇所には、ここでは図示しないが、配線パターン2と、ランド部3が設けられると共に、隣り合う回路基板1間には、切り欠き部からなる貫通部1dとなる貫通孔12が設けられ、この貫通孔12の壁面には、導電体4が形成された状態となっている。   And although not shown here, the wiring pattern 2 and the land part 3 are provided in the location corresponding to each circuit board (part surrounded by a two-dot chain line) 1 of the large-size substrate 11 and adjacent to each other. Between the circuit boards 1, a through hole 12 serving as a through portion 1 d made of a notch is provided, and a conductor 4 is formed on the wall surface of the through hole 12.

次に、図5,図6に示す第2工程では、回路基板1上と貫通孔12内にクリーム半田が塗布され、先ず、クリーム半田上に電子部品5を載置した後、電子部品5をカバー6の覆い部6aにより覆った状態で、取付脚6bを貫通孔12内に挿入し、しかる後、リフロー炉内に搬送し、クリーム半田を溶かすと、配線パターン2への電子部品5の半田付が行われると共に、導電体4への取付脚6bの半田7付が行われる。   Next, in the second step shown in FIGS. 5 and 6, cream solder is applied on the circuit board 1 and in the through holes 12. First, the electronic component 5 is placed on the cream solder, and then the electronic component 5 is mounted. When the mounting leg 6b is inserted into the through-hole 12 while being covered with the cover 6a of the cover 6, and then transported into the reflow furnace to melt the cream solder, the solder of the electronic component 5 to the wiring pattern 2 is soldered. At the same time, the attachment leg 6b to the conductor 4 is soldered.

なお、この電子部品5の半田付と、カバー6の半田7付は、別々の工程によって行っても良い。   Note that the soldering of the electronic component 5 and the soldering 7 of the cover 6 may be performed by separate processes.

次に、図7に示す第3工程では、絶縁膜8が貫通孔12の下面に位置する半田7の下面と、この半田7の下面の近傍に位置する回路基板1の下面1bに跨って設けられて、絶縁膜8によって半田7の下面を覆う。   Next, in the third step shown in FIG. 7, the insulating film 8 is provided across the lower surface of the solder 7 located on the lower surface of the through hole 12 and the lower surface 1 b of the circuit board 1 located in the vicinity of the lower surface of the solder 7. Then, the lower surface of the solder 7 is covered with the insulating film 8.

なお、この絶縁膜8の形成は、上述したように、予め、回路基板1の下面1bに半田レジスト膜(図示せず)が設けられ、この状態で、取付脚6bと導電体4の半田7付けを行った後、絶縁膜8を形成したり、或いは、取付脚6bと導電体4の半田7付けを行った後、ランド部3を除く下面1bの全体に半田レジスト膜を形成して、絶縁膜8を同時に形成するようにしても良い。   As described above, the insulating film 8 is formed in advance by providing a solder resist film (not shown) on the lower surface 1b of the circuit board 1, and in this state, the solder 7 of the mounting leg 6b and the conductor 4 is formed. After the attachment, the insulating film 8 is formed, or after the mounting legs 6b and the conductor 4 are soldered 7, a solder resist film is formed on the entire lower surface 1b except for the land portion 3, The insulating film 8 may be formed at the same time.

そして、最後の工程において、二点差線で示す位置で切断すると、図1〜図3に示すような個々の面実装型電子回路ユニットが形成されると共に、貫通孔12の位置で切断されることによって、回路基板1には切り欠き部からなる貫通部1dが形成されるようになっている。   And in the last process, when it cut | disconnects in the position shown with a dashed-two dotted line, while being formed in each surface mount type electronic circuit unit as shown in FIGS. 1-3, it cut | disconnects in the position of the through-hole 12. FIG. Thus, the circuit board 1 is formed with a through-hole 1d made of a notch.

また、図8,図9は本発明の面実装型電子回路ユニットの第2実施例を示し、この第2実施例は、貫通部1dが回路基板1の端面1cから外れた位置に設けられた上下方向に貫通する貫通孔で形成され、貫通部1dである貫通孔内に挿入された取付脚6bが導電体4に半田7付けされると共に、絶縁膜8が貫通部1d内の半田7の下面と、この半田7の下面の近傍に位置する回路基板1の下面1bに跨って設けられている。   8 and 9 show a second embodiment of the surface mount electronic circuit unit according to the present invention. In the second embodiment, the penetrating portion 1d is provided at a position away from the end face 1c of the circuit board 1. FIG. A mounting leg 6b formed by a through hole penetrating in the vertical direction and inserted into the through hole as the through portion 1d is soldered to the conductor 4, and an insulating film 8 is formed on the solder 7 in the through portion 1d. It is provided across the lower surface and the lower surface 1 b of the circuit board 1 located in the vicinity of the lower surface of the solder 7.

なお、その他の構成は、前記第1実施例と同様であるので、同一部品に同一番号を付し、ここではその説明を省略する。   Since other configurations are the same as those in the first embodiment, the same parts are denoted by the same reference numerals, and the description thereof is omitted here.

本発明の面実装型電子回路ユニットの第1実施例に係る平面図。The top view which concerns on 1st Example of the surface mount-type electronic circuit unit of this invention. 本発明の面実装型電子回路ユニットの第1実施例に係る下面図。1 is a bottom view according to a first embodiment of a surface mount electronic circuit unit of the present invention. FIG. 本発明の面実装型電子回路ユニットの第1実施例に係る要部断面図。The principal part sectional view concerning the 1st example of the surface mounting type electronic circuit unit of the present invention. 本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第1工程を示す平面図。The top view which concerns on 1st Example of the surface mounted electronic circuit unit of this invention, and shows the 1st process for demonstrating the manufacturing method. 本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第2工程を示す平面図。The top view which concerns on 1st Example of the surface mount-type electronic circuit unit of this invention, and shows the 2nd process for demonstrating the manufacturing method. 本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第2工程を示す下面図。The bottom view which shows the 2nd process for demonstrating the manufacturing method concerning the 1st Example of the surface mount-type electronic circuit unit of this invention. 本発明の面実装型電子回路ユニットの第1実施例に係り、その製造方法を説明するための第3工程を示す下面図。The bottom view which concerns on 1st Example of the surface mount-type electronic circuit unit of this invention, and shows the 3rd process for demonstrating the manufacturing method. 本発明の面実装型電子回路ユニットの第2実施例に係る下面図。The bottom view which concerns on 2nd Example of the surface mount-type electronic circuit unit of this invention. 本発明の面実装型電子回路ユニットの第2実施例に係る要部断面図。Sectional drawing of the principal part which concerns on 2nd Example of the surface mount-type electronic circuit unit of this invention. 従来の面実装型電子回路ユニットの斜視図。The perspective view of the conventional surface mount-type electronic circuit unit. 従来の面実装型電子回路ユニットの下面図。The bottom view of the conventional surface mount-type electronic circuit unit. 従来の面実装型電子回路ユニットの要部断面図。Sectional drawing of the principal part of the conventional surface mount-type electronic circuit unit.

符号の説明Explanation of symbols

1:回路基板
1a:上面
1b:下面
1c:端面
1d:貫通部
2:配線パターン
3:ランド部
4:導電体
5:電子部品
6:カバー
6a:覆い部
6b:取付脚
7:半田
8:絶縁膜
11:大版基板
12:貫通孔
DESCRIPTION OF SYMBOLS 1: Circuit board 1a: Upper surface 1b: Lower surface 1c: End surface 1d: Through part 2: Wiring pattern 3: Land part 4: Conductor 5: Electronic component 6: Cover 6a: Cover part 6b: Mounting leg 7: Solder 8: Insulation Film 11: Large plate substrate 12: Through hole

Claims (3)

上面に設けられた配線パターン、及び下面に設けられたランド部を有する回路基板と、前記配線パターン上に搭載された電子部品と、上下方向に貫通して前記回路基板に設けられた貫通部と、この貫通部の壁面に設けられた導電体と、前記電子部品を覆った状態で、前記回路基板に取り付けられた箱形のカバーとを備え、前記カバーに設けられた取付脚は、前記貫通部内に位置した状態で、前記導電体に半田付けされて取り付けられると共に、絶縁膜が前記半田の下面、及び前記半田の下面の近傍に位置する前記回路基板の下面に跨って設けられたことを特徴とする面実装型電子回路ユニット。 A circuit board having a wiring pattern provided on the upper surface and a land portion provided on the lower surface; an electronic component mounted on the wiring pattern; and a through part provided in the circuit board penetrating in the vertical direction; The conductor provided on the wall surface of the penetrating portion and the box-shaped cover attached to the circuit board in a state of covering the electronic component, and the mounting leg provided on the cover includes the penetrating In the state where it is located in the part, it is attached by soldering to the conductor, and the insulating film is provided across the lower surface of the solder and the lower surface of the circuit board located in the vicinity of the lower surface of the solder. A featured surface mount electronic circuit unit. 前記絶縁膜が半田レジスト膜で形成されたことを特徴とする請求項1記載の面実装型電子回路ユニット。 2. The surface mount electronic circuit unit according to claim 1, wherein the insulating film is formed of a solder resist film. 前記貫通部は、前記回路基板の端面の位置に設けられた上下方向に貫通する切り欠き部、又は/及び前記回路基板の前記端面から外れた位置に設けられた上下方向に貫通する貫通孔で形成されたことを特徴とする請求項1、又は2記載の面実装型電子回路ユニット。
The penetrating part is a notch part penetrating in the vertical direction provided at the position of the end face of the circuit board, and / or a through hole penetrating in the vertical direction provided at a position away from the end face of the circuit board. 3. The surface mount electronic circuit unit according to claim 1, wherein the surface mount electronic circuit unit is formed.
JP2003362241A 2003-10-22 2003-10-22 Surface-mounting electronic circuit unit Withdrawn JP2005129656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003362241A JP2005129656A (en) 2003-10-22 2003-10-22 Surface-mounting electronic circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003362241A JP2005129656A (en) 2003-10-22 2003-10-22 Surface-mounting electronic circuit unit

Publications (1)

Publication Number Publication Date
JP2005129656A true JP2005129656A (en) 2005-05-19

Family

ID=34641956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003362241A Withdrawn JP2005129656A (en) 2003-10-22 2003-10-22 Surface-mounting electronic circuit unit

Country Status (1)

Country Link
JP (1) JP2005129656A (en)

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