JP2005123661A - Analog/digital mixedly mounted semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog/digital mixedly mounted semiconductor device capable of suppressing a circuit current at the time of stopping a clock to low. <P>SOLUTION: The device is provided with an analog circuit 2, a digital circuit 1, a clock stop detecting circuit 14 and a control signal selecting circuit 15. The digital circuit 1 operates in accordance with a clock CK, and outputs an analog circuit control signal S1 for controlling the operation of the analog circuit 2. The circuit 14 detects the stoppage of the clock CK and outputs an analog circuit control signal S2 for stopping the analog circuit 2. Using the signals S1, S2, the circuit 15 selects the signal S1 and provides the selected signal to the analog circuit 2 as an analog circuit control signal S3 when the signal S2 is not ouputted, and preferentially selects the signal S2 and provides the selected signal to the analog circuit 2 as an analog circuit control signal S3 when the signal S2 is outputted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an analog / digital mixed semiconductor device having a clock stop detection function in which an analog circuit and a digital circuit are mixedly mounted. In particular, the present invention relates to an analog / digital mixed semiconductor device intended to reduce power consumption when a clock is stopped.

  FIG. 5 shows a configuration of the prior art of a mixed analog / digital semiconductor device.

  In this analog / digital mixed semiconductor device, the digital circuit 1 operates in accordance with the clock CK. The operation of the analog circuit 2 is controlled by an analog circuit control signal S1 generated by the digital circuit 1. That is, the analog circuit 2 can be put into an operation state or a stop state by the analog circuit control signal S1.

  When the analog circuit 2 is powered on, for example, an H level analog circuit control signal S1 indicating power on is transmitted from the digital circuit 1 to the analog circuit 2. As a result, the analog circuit 2 enters an operating state.

  Further, when the analog circuit 2 is powered off, the digital circuit 1 transmits an analog circuit control signal S1 having an L level, for example, indicating the power off to the analog circuit 2. As a result, the analog circuit is stopped.

  FIG. 6 shows one specific example of the configuration of the analog circuit 2 in FIG. The analog circuit 2 includes, for example, a bias current source 5 with a switch using a current mirror circuit with a switch and analog circuits 3 and 4.

The bias current source 5 includes an input side transistor 6 and output side transistors 9 and 10 that constitute a current mirror, switch transistors 7 and 8 that control the operation of the current mirror, a constant current source 11 that supplies a current I ₁ , and an inverter 12. , 13. The analog circuits 3 and 4 are supplied with mirror currents I ₂ and I ₃ with an arbitrary configuration.

In the analog circuit 2, when the analog circuit control signal S1 is in a power-on state (high level), the switch transistor 7 is turned on and the switch transistor 8 is turned off. As a result, the current mirror circuit operates, and the mirror currents I ₂ and I ₃ of the current I ₁ are supplied to the analog circuits 3 and 4, respectively.

When the analog circuit control signal S1 is in the power-off state (low level), the switch transistor 7 is turned off and the switch transistor 8 is turned on, whereby the mirror currents I ₂ and I to the analog circuits 3 and 4 are turned on. The supply of ₃ stops.

  FIG. 7 shows another specific example of the analog circuit 2 in FIG. The analog circuit 2 includes a switched capacitor circuit 21 as shown in FIG. 7A and a control circuit 22 as shown in FIG. 7B that controls the switched capacitor circuit 21.

  The switched capacitor circuit 21 includes an operational amplifier OP1, capacitors C1 and C2, and switches SW1 to SW8. The switched capacitor circuit 21 operates to move the charge accumulated in the capacitor C1 between the terminal of the input signal Ain and the terminal of the reference voltage Vref to the capacitor C2 by switching each switch SW1 to SW8 on and off. I do.

  The control circuit 22 includes a control clock generator 23 that controls the switched capacitor and a logic determination circuit 24 that determines the logic when the clock is stopped.

  The control clock generator 23 receives the clock CK and generates switched capacitor clocks φ1 ′ and φ2 ′ for turning on and off the switches SW1 to SW8. The control clock generator 23 is a switched capacitor clock so that the switches SW1, SW3, SW6, SW8 and the switches SW2, SW4, SW5, SW7 are alternately turned on with a predetermined dead time. φ1 ′ and φ2 ′ are generated.

  Logic decision circuit 24 receives switched capacitor clocks φ1 ′ and φ2 ′ and analog circuit control signal S1 as input and generates switched capacitor clocks φ1 and φ2. The logic determination circuit 24 outputs the switched capacitor clocks φ1 ′ and φ2 ′ as the switched capacitor clocks φ1 and φ2 as they are when the analog circuit 2 is powered on based on the analog circuit control signal S1. When power 2 is off, the switched capacitor clocks φ1 and φ2 have a function of fixing all the switches SW1 to SW8 to be off regardless of the state of the switched capacitor clocks φ1 ′ and φ2 ′.

  That is, when the analog circuit 2 is powered off by the analog circuit control signal S1, the control circuit 22 uses which of the switches SW1 and SW2 provided in series between the terminal of the input signal Ain and the terminal of the reference voltage Vref. Further, the states of the switches SW1 to SW8 are fixed by the logic determination circuit 24 so that the switched capacitor circuit 21 does not stop in the ON state.

When the clock CK is stopped, the state of the switches SW1 to SW8 is fixed to the above state by stopping the clock CK after the analog circuit 2 is powered off.
Japanese Patent Application No. 05-276048

  In the conventional analog / digital mixed semiconductor device, when the clock CK to the digital circuit 1 suddenly stops, the digital circuit 1 stops, and the logical value of the internal logic circuit of the digital circuit 1 is the logical value immediately before the stop of the clock CK. Fixed. Therefore, the output analog circuit control signal S1 is held in the state immediately before the stop of the clock CK. Therefore, when the state of the analog circuit 2 when the clock CK is stopped is the power-on state, there is a problem that the analog circuit 2 remains in the power-on state and the circuit current continues to flow.

For example, in the case of the circuit shown in FIG. 6, when the analog circuit control signal S1 is at a high level when the clock CK is stopped, the switch transistor 7 is turned on and the switch transistor 8 is kept off. Currents I ₂ and I ₃ are continuously supplied.

  Further, as shown in FIG. 7, when the analog circuit 2 includes a switched capacitor circuit, another problem occurs. If the clock CK stops while the analog circuit 2 is in the power-on state, there is a possibility that both the switches SW1 and SW2 are on. In that case, the terminal of the input signal Ain and the terminal of the reference voltage Vref are short-circuited, and a great amount of circuit current flows. Further, in this circuit, not only the power supply short circuit as described above occurs, but also a short circuit between an external input and the ground of the semiconductor integrated circuit may occur, for example.

  SUMMARY OF THE INVENTION The present invention solves the above-described problem, and an analog / digital mixed semiconductor device comprising a digital circuit that operates according to a clock and an analog circuit that can be stopped by an analog circuit control signal generated by the digital circuit. An object of the present invention is to provide an analog / digital mixed semiconductor device capable of keeping a circuit current low when a clock is stopped.

  In order to solve the above problems, an analog / digital mixed semiconductor device of the present invention includes an analog circuit, a digital circuit, a clock stop detection circuit, and a control signal selection circuit.

  The digital circuit operates according to the clock and outputs a first analog circuit control signal for controlling the operation of the analog circuit.

  The clock stop detection circuit detects a clock stop and outputs a second analog circuit control signal for stopping the operation of the analog circuit.

  The control signal selection circuit inputs the first analog circuit control signal and the second analog circuit control signal, and selects the first analog circuit control signal when the second analog circuit control signal is not output. The third analog circuit control signal is given to the analog circuit, and when the second analog circuit control signal is output, the second analog circuit control signal is preferentially selected and the analog circuit is used as the third analog circuit control signal. To give.

  According to this configuration, when the clock stops, the clock stop detection circuit detects it and outputs the second analog circuit control signal. The control signal selection circuit preferentially selects the second analog circuit control signal and supplies it to the analog circuit as a third analog circuit control signal. Therefore, the analog circuit is forcibly stopped when the clock suddenly stops and the first analog circuit control signal output from the digital circuit cannot be controlled normally due to the influence of the clock stop. Can be stopped.

  As the analog circuit, for example, one having a control means for supplying or blocking a bias current or a bias voltage according to a third analog circuit control signal is used. Alternatively, a circuit that includes a switched capacitor circuit and a logic determination circuit that fixes the switch elements constituting the switched capacitor circuit in a specific state in accordance with the third analog circuit control signal is used.

  According to the present invention, when the clock stop detection circuit detects the clock stop and outputs the second analog circuit control signal, the control signal selection circuit gives priority to the second analog circuit control signal. The signal is selected and supplied to the analog circuit as a third analog circuit control signal. Therefore, the analog circuit is forcibly stopped when the clock suddenly stops and the first analog circuit control signal output from the digital circuit cannot be controlled normally due to the influence of the clock stop. Can be stopped. As a result, it is possible to provide an analog / digital mixed semiconductor device in which the circuit current when the clock is stopped is kept low.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of an analog / digital mixed semiconductor device having a clock stop detection function according to an embodiment of the present invention.

  As shown in FIG. 1, the analog / digital mixed semiconductor device includes an analog circuit 2, a digital circuit 1, a clock stop detection circuit 14, and a control signal selection circuit 15.

  The digital circuit 1 operates in accordance with the clock CK and outputs a first analog circuit control signal S1 for controlling the operation of the analog circuit 2.

  The clock stop detection circuit 14 outputs a second analog circuit control signal S2 that detects the stop of the clock CK and stops the operation of the analog circuit 2.

  The control signal selection circuit 15 receives the first analog circuit control signal S1 and the second analog circuit control signal S2, and outputs the first analog circuit when the second analog circuit control signal S2 is not output. The control signal S1 is selected and supplied to the analog circuit 2 as the third analog circuit control signal S3. When the second analog circuit control signal S2 is output, the second analog circuit control signal S2 is preferentially selected and 3 is supplied to the analog circuit 2 as the analog circuit control signal S3.

  With this configuration, when the clock stop detection circuit 14 detects that the clock CK has been stopped and outputs the second analog circuit control signal S2, the control signal selection circuit 15 causes the second analog circuit to The control signal S2 is preferentially selected and supplied to the analog circuit 2 as the third analog circuit control signal S3. Therefore, when the clock CK suddenly stops and the first analog circuit control signal S1 output from the digital circuit 1 is affected by the stop of the clock CK, the analog circuit 2 cannot be normally controlled. The analog circuit 2 can be forcibly stopped. As a result, an analog / digital mixed semiconductor device in which the circuit current when the clock CK is stopped can be kept low can be provided.

FIG. 2 shows a circuit example of the clock stop detection circuit 14, and FIG. 3 shows a time chart of input / output signals of each part of the clock stop detection circuit 14 of FIG. As shown in FIG. 2, the clock stop detection circuit 14 includes a frequency divider 31 that divides the clock CK by 2, an integrator 32 that integrates the output of the frequency divider 31, and an output level of the integrator 32. The level judgment unit 33 is configured to judge by two threshold values V _THH and V _THL .

The frequency divider 31 is composed of, for example, a D flip-flop 31a. Further, the integrator 32 includes, for example, a resistor 32a and a capacitor 32b. The level determination unit 33 includes, for example, an H level comparator 33a, an L level comparator 33b, and a NAND circuit 33c. In the H level comparator 32a, a threshold value V _THH is set to, for example, 2/3 from the bottom between the low level potential and the high level potential of the output of the integrator 32. In the L level comparator 32b, the threshold value V _THL is set to, for example, 1/3 from the bottom between the low level potential and the high level potential of the output of the integrator 32.

In the clock stop detection circuit 14, the following operation is performed. A clock CK as shown in FIG. 3A is divided by 2 by the frequency divider 31 to generate a frequency-divided signal as shown in FIG. 3B with a duty ratio of 50%. When this frequency-divided signal is passed through the integrator 32, the frequency-divided signal is integrated to obtain an integrated signal as shown in FIG. When the divided signal is fixed at the low level, the integrated signal is maintained at the low level. When the divided signal is fixed at the high level, the integrated signal is maintained at the high level, and the divided signal is alternately switched between the high level and the low level. When it is repeated at a duty ratio of 50%, the integration signal maintains a potential approximately halfway between the high level and the low level. Further, during the transition period from the clock stop to the clock operation, or the transition period from the clock operation to the clock stop, the level of the integration signal gradually changes so as to cross the threshold values V _THH and V _THL .

  Then, the integrated signal of the integrator 32 is passed through the level determination unit 33 to discriminate the level of the integrated signal.

When the clock CK is continuously input (during clock operation), the level of the integration signal is within the range of the clock detection level A, that is, within the range of the threshold value V _{THL and} less than the threshold value V _THH. The existing state is maintained, and the analog circuit control signal S2 (clock stop detection signal) becomes high level as shown in FIG.

On the other hand, when the clock CK is stopped, the level of the frequency- _divided signal moves outside the range of the clock detection level A, that is, below the threshold V _THL or above the threshold V _THH , and the analog circuit control signal S2 (clock The stop detection signal) is at a low level. That is, a state where the clock stop detection signal is at a low level is a state where a clock stop is detected, and a low level clock stop detection signal is an active state as the second analog circuit control signal S2.

  FIG. 4A shows a circuit example of the control signal selection circuit 15. In this example, the control signal selection circuit 15 includes an AND circuit 15a. FIG. 4B shows a truth table of the control signal selection circuit 15.

  In the control signal selection circuit 15, whether to output power on (H level) or power off (L level) to the analog circuit control signal S3 according to the analog circuit control signal S1 and the analog circuit control signal S2. Is determined. When the power is turned on, the analog circuit control signal S1 of the H level is input from the digital circuit 1 as the analog circuit control signal S1, and the analog circuit control signal S1 of the L level is input from the digital circuit 1 when the power is turned off. .

  During clock operation, an H level signal is input from the clock stop detection circuit 14 as the analog circuit control signal S2 (a state in which the second analog circuit control signal S2 is not output). When the clock is stopped, an L level signal is input (a state in which the second analog circuit control signal S2 is output).

  As a result, when the clock CK to the digital circuit 1 suddenly stops, the digital circuit 1 stops, and even if the logic value of the logic circuit is fixed at the logic value immediately before the clock CK stops, the clock stop detection circuit 14 Since the analog circuit control signal S2 is input to the analog circuit control signal selection circuit 15 to output a power-off signal, the analog circuit 2 can be stopped.

  Further, even when a switched capacitor circuit is used, the on / off state of each switch can be appropriately determined. That is, each switch can be fixed in a specific state. As a result, it is possible not only to prevent a power supply short circuit, but also to prevent a short circuit between an external input and the ground of the semiconductor integrated circuit, for example.

  Therefore, even when the clock CK suddenly stops during operation, there is no problem that the current of the analog circuit 2 continues to flow, and the circuit current when the clock CK is stopped can be kept low.

  In the analog / digital mixed semiconductor device according to the present invention, the clock suddenly stops, and the first analog circuit control signal output from the digital circuit can be normally controlled by the influence of the clock stop. Analog / digital mixed semiconductor device in which analog circuit and digital circuit are mixed and has the effect of being able to forcibly stop the analog circuit when it is lost and suppressing the circuit current when the clock is stopped. Useful as such.

It is a block diagram which shows the structure of the analog / digital mixed semiconductor device by embodiment of this invention. It is a circuit diagram which shows the structure of the clock stop detection circuit in embodiment of this invention. 3 is a time chart showing the operation of the clock stop detection circuit of FIG. (A) is a block diagram showing the configuration of the analog circuit control signal selection circuit in the embodiment of the present invention, (b) is a truth table showing the operation of the control signal selection circuit. It is a block diagram which shows the structure of the prior art of an analog / digital mixed semiconductor device. It is a circuit diagram which shows an example of a structure of the analog circuit incorporating a bias current source. It is a circuit diagram which shows an example of a structure of the analog circuit incorporating a switched capacitor circuit, (a) shows a switched capacitor circuit, (b) has shown the control circuit which controls a switched capacitor circuit.

Explanation of symbols

1 Digital circuit 2 Analog circuit 14 Clock stop detection circuit 15 Control signal selection circuit

Claims (3)

An analog circuit;
A digital circuit that operates according to a clock and outputs a first analog circuit control signal for controlling the operation of the analog circuit;
A clock stop detection circuit for detecting a stop of the clock and outputting a second analog circuit control signal for stopping the operation of the analog circuit;
When the first analog circuit control signal and the second analog circuit control signal are input, and the second analog circuit control signal is not output, the first analog circuit control signal is selected. The third analog circuit control signal is given to the analog circuit, and when the second analog circuit control signal is output, the second analog circuit control signal is preferentially selected and the third analog circuit control signal is selected. An analog / digital mixed semiconductor device provided with a control signal selection circuit to be given to the analog circuit.   2. The analog / digital mixed semiconductor device according to claim 1, wherein the analog circuit includes control means for supplying or cutting off a bias current or a bias voltage in accordance with the third analog circuit control signal. 2. The analog circuit includes a switched capacitor circuit and a logic determination circuit that fixes a switch element constituting the switched capacitor circuit in a specific state in accordance with the third analog circuit control signal. The analog / digital mixed semiconductor device described.

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