JP2005123497A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor constituted of an organic material which is excellent in bendability and flexibility. <P>SOLUTION: The field effect transistor 40 has (A); a source/drain region 65 and a channel formation region 64 formed in a semiconductor layer 63, and (B); and a gate electrode 60 opposed to the channel formation region 64 via the gate insulating layer 62. It has an insulating matrix layer 50 constituting the semiconductor layer 63 and the gate insulating layer 62, and a conductive polymeric material is impregnated into the part 51 of the insulating matrix layer constituting the semiconductor layer 63. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof, and more particularly to a so-called organic field effect transistor and a manufacturing method thereof.

  When manufacturing a semiconductor device from a conventional silicon semiconductor substrate or the like, a photolithography technique and various thin film forming techniques are used. However, these production techniques are complicated, require a long time for manufacturing the semiconductor device, and are a great obstacle to reducing the manufacturing cost of the semiconductor device. Further, the conventional semiconductor device is so-called bulk, and it is difficult to apply it to a field where flexibility and flexibility are required. Furthermore, as symbolized by Moore's Law, the limits of speeding up (accumulation) are becoming visible.

  Research and development of an electronic element that replaces a semiconductor device based on such a conventional silicon semiconductor substrate, such as a field effect transistor (FET), using an electroconductive polymer material has been eagerly advanced. In addition, a new field of inexpensive plastic electronics is being developed.

  Such a field effect transistor is disclosed in, for example, “Development of Line Patterning Method and Application to Electronic Devices”, Hidenori Okasaki, Polymer Preprints, Japan, Vol. 51, No. 1 (2002), pp 10-12. Has been. In the field effect transistor disclosed in this document, a poly (3,4-ethylenedioxythiophene) / polystyrenesulfonic acid aqueous solution is coated on an OHP film made of PET on which a toner is transferred and fixed using a laser printer, and then dried. Thereafter, the toner is removed to form source / drain regions and a channel formation region, and then a gate insulating layer made of polyvinylphenol (PVP) resin is formed.

"Development of line patterning method and application to electronic devices", Hidenori Okasaki, Polymer Preprints, Japan, Vol. 51, No. 1 (2002), pp 10-12

  Organic electronics is one of the candidates for post-silicon technology, but in reality, examples of realizing its superiority, that is, cheap and easy manufacturing methods, and flexibility and flexibility of devices Still very few. That is, for example, in the method of manufacturing a field effect transistor disclosed in the above-mentioned document, the gate insulating layer is formed after the source / drain region and the channel forming region are formed. There is a strong demand for a method for manufacturing such a field effect transistor. In order to realize organic electronics, it is extremely important to realize a switchable element (for example, FET) as an element that plays a central role. However, at present, it is difficult to say that the performance is at a practical level.

  Accordingly, an object of the present invention is to provide a simpler and simpler method for manufacturing a field effect transistor composed of an organic material, and excellent flexibility and flexibility obtained by such a manufacturing method. The object is to provide a field effect transistor.

In order to achieve the above object, a field effect transistor according to the first aspect of the present invention provides:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
Comprising one insulating matrix layer constituting a semiconductor layer and a gate insulating layer;
A portion of the insulating matrix layer that constitutes the semiconductor layer is impregnated with a conductive polymer material.

  In the field effect transistor according to the first aspect of the present invention, the insulating matrix layer constituting the gate insulating layer may be impregnated with the insulating polymer material. The field effect transistor having such a configuration is referred to as a field effect transistor according to the first aspect of the present invention for convenience. In the field effect transistor according to aspect 1A of the present invention, a portion of an insulating matrix layer constituting a gate insulating layer impregnated with an insulating polymer material, and a semiconductor layer impregnated with a conductive polymer material There may be a boundary region between the insulating matrix layer that is not impregnated with the insulating polymer material and that is not impregnated with the conductive polymer material. However, the boundary region of such an insulating matrix layer functions as a gate insulating layer.

In order to achieve the above object, a field effect transistor according to the second aspect of the present invention provides:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
Comprising an insulating matrix layer having a two-layer structure constituting a semiconductor layer and a gate insulating layer;
The first layer of the insulating matrix layer constituting the semiconductor layer is impregnated with a conductive polymer material,
A gate insulating layer is constituted by the second layer of the insulating matrix layer.

  In the field effect transistor according to the second aspect of the present invention, the second layer of the insulating matrix layer may be impregnated with an insulating polymer material. For convenience, the field effect transistor having such a configuration is referred to as a field effect transistor according to the second aspect of the present invention. In the field effect transistor according to aspect 2A of the present invention, the first layer of the insulating matrix layer constituting the semiconductor layer impregnated with the conductive polymer material and the insulating polymer material are impregnated. The boundary of the insulating matrix layer not impregnated with the insulating polymer material and not impregnated with the conductive polymer material between the second layer of the insulating matrix layer constituting the gate insulating layer Although a region may exist, the boundary region of such an insulating matrix layer functions as a gate insulating layer. This boundary region may exist in the first layer of the insulating matrix layer, may exist in the second layer of the insulating matrix layer, or may be present in the first layer of the insulating matrix layer. And may be present in the second layer.

In order to achieve the above object, a field effect transistor according to the third aspect of the present invention provides:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
It has a laminated structure of an insulating matrix layer and an insulating polymer material layer,
A gate insulating layer is constituted by the insulating polymer material layer,
The insulating matrix layer constituting the semiconductor layer is impregnated with a conductive polymer material.

  In the field effect transistor according to the third aspect of the present invention, the insulating matrix layer in the vicinity of the interface between the insulating polymer material layer and the insulating matrix layer is a boundary region that is not impregnated with the conductive polymer material. In some cases, the boundary region constituted by such an insulating matrix layer functions as a gate insulating layer.

In order to achieve the above object, a field effect transistor according to the fourth aspect of the present invention provides:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
It has a laminated structure of an insulating matrix layer and an insulating material layer transferred and fixed to one surface of the insulating matrix layer,
The insulating material layer constitutes the gate insulating layer,
The insulating matrix layer constituting the semiconductor layer is impregnated with a conductive polymer material.

  In the field effect transistor according to the fourth aspect of the present invention, the insulating matrix layer in the vicinity of the interface between the insulating material layer and the insulating matrix layer has a boundary region that is not impregnated with the conductive polymer material. In some cases, the boundary region constituted by such an insulating matrix layer functions as a gate insulating layer.

In order to achieve the above object, a method of manufacturing a field effect transistor according to the first aspect of the present invention includes:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
A method of manufacturing a field effect transistor comprising a single insulating matrix layer constituting a semiconductor layer and a gate insulating layer,
The method includes a step of impregnating a portion of the insulating matrix layer that constitutes the semiconductor layer with a conductive polymer material.

In the method of manufacturing the field effect transistor according to the first aspect of the present invention,
(1) A method of forming a gate electrode before impregnating a conductive polymer material into a portion of an insulating matrix layer that constitutes a semiconductor layer. (2) Conductivity in a portion of an insulating matrix layer that constitutes a semiconductor layer. Two methods of forming the gate electrode after impregnating the conductive polymer material are included.

  Furthermore, in the method of manufacturing the field effect transistor according to the first aspect of the present invention, it is desirable to form source / drain electrodes in the source / drain regions. In the case of the above (1), it is preferably performed after impregnating the conductive polymer material in the portion of the insulating matrix layer that constitutes the semiconductor layer, and in the case of the above (2), the insulation that constitutes the semiconductor layer. It is preferable that the conductive matrix layer is impregnated with a conductive polymer material before the gate electrode is formed or after the gate electrode is formed.

  In the method of manufacturing the field effect transistor according to the first aspect of the present invention, the gate insulating layer should be formed after the conductive polymer material is impregnated into the portion of the insulating matrix layer that should form the semiconductor layer. The insulating matrix layer may be impregnated with an insulating polymer material. In addition, the manufacturing method of the field effect transistor of such a structure is called the manufacturing method of the field effect transistor which concerns on 1A aspect of this invention for convenience.

In the method of manufacturing the field effect transistor according to the aspect 1A of the present invention,
(1) A method of forming a gate electrode before impregnating a conductive polymer material into a portion of an insulating matrix layer that constitutes a semiconductor layer. (2) Conductivity in a portion of an insulating matrix layer that constitutes a semiconductor layer. A method of impregnating an insulating polymer material after impregnating the insulating polymer material and then forming a gate electrode, and then impregnating the insulating polymer material into a portion of the insulating matrix layer that is to constitute the gate insulating layer (3) Configuring the gate insulating layer Three methods are included: a method of forming a gate electrode after impregnating a portion of a power insulating matrix layer with an insulating polymer material.

  Furthermore, in the method of manufacturing the field effect transistor according to the first aspect of the present invention, it is desirable to form the source / drain electrodes in the source / drain regions. In the case of (1) and (2) above, it is preferably carried out after impregnating a conductive polymer material into the portion of the insulating matrix layer that constitutes the semiconductor layer. In the case of (3) above, the gate insulating layer It is preferable that the insulating matrix layer portion to be formed is impregnated with an insulating polymer material before the gate electrode is formed or after the gate electrode is formed.

  Alternatively, in the method of manufacturing the field effect transistor according to the first aspect of the present invention, the gate insulating layer is formed before the conductive matrix material is impregnated into the insulating matrix layer portion that should form the semiconductor layer. A structure including a step of impregnating an insulating polymer material into a portion of the insulating matrix layer to be formed can be employed. In addition, the manufacturing method of the field effect transistor of such a structure is called the manufacturing method of the field effect transistor which concerns on the 1B aspect of this invention for convenience.

In the method of manufacturing the field effect transistor according to the aspect 1B of the present invention,
(1) A method of forming a gate electrode before impregnating an insulating polymer material into a portion of an insulating matrix layer that constitutes a gate insulating layer. (2) A portion of an insulating matrix layer that constitutes a gate insulating layer. (4) Method of impregnating a conductive polymer material into a portion of an insulating matrix layer that is to constitute a semiconductor layer. (3) Constructing a semiconductor layer Three methods are included: a method of forming a gate electrode after impregnating a portion of a power insulating matrix layer with a conductive polymer material.

  Furthermore, in the method for manufacturing a field effect transistor according to the first aspect of the present invention, it is desirable to form source / drain electrodes in the source / drain regions. In the case of (1) and (2) above, it is preferably carried out after impregnating the conductive polymer material into the portion of the insulating matrix layer that constitutes the semiconductor layer. This is preferably performed after the conductive matrix material is impregnated into the portion of the insulating matrix layer to be formed and before the gate electrode is formed or after the gate electrode is formed.

  In the method of manufacturing the field effect transistor according to the aspects 1A and 1B of the present invention, the insulating matrix layer portion constituting the gate insulating layer impregnated with the insulating polymer material, and The insulating polymer layer is not impregnated between the portion of the insulating matrix layer constituting the semiconductor layer impregnated with the conductive polymer material, and the conductive polymer material is not impregnated. Although there may be a boundary region of the insulating matrix layer, such a boundary region of the insulating matrix layer functions as a gate insulating layer.

In order to achieve the above object, a method of manufacturing a field effect transistor according to the second aspect of the present invention includes:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
Comprising an insulating matrix layer having a two-layer structure constituting a semiconductor layer and a gate insulating layer;
A method of manufacturing a field effect transistor in which a semiconductor layer is formed by a first layer of an insulating matrix layer and a gate insulating layer is formed by a second layer of the insulating matrix layer,
The method includes a step of laminating a first layer of an insulating matrix layer impregnated with a conductive polymer material and a second layer of the insulating matrix layer.

  In the method for manufacturing the field effect transistor according to the second aspect of the present invention, the second layer of the insulating matrix layer may be impregnated with an insulating polymer material. In addition, the manufacturing method of the field effect transistor of such a structure is called the manufacturing method of the field effect transistor which concerns on the 2A aspect of this invention for convenience.

  In the method for manufacturing a field effect transistor according to the second aspect of the present invention including the second aspect, the first and second layers of the insulating matrix layer are stacked, and then the gate electrode is formed. Although it is desirable to form, a gate electrode may be formed before lamination. Further, it is desirable to form source / drain electrodes in the source / drain regions. However, these source / drain electrodes are formed after the first and second layers of the insulating matrix layer are stacked. However, the source / drain electrodes may be formed before lamination.

  In the method for manufacturing a field effect transistor according to the second aspect of the present invention, the first layer of the insulating matrix layer constituting the semiconductor layer impregnated with the conductive polymer material, and, if necessary, the insulating high Between the second layer of the insulating matrix layer constituting the gate insulating layer impregnated with the molecular material, the insulating polymer material is not impregnated and the conductive polymer material is not impregnated. Although there may be a boundary region of the insulating matrix layer, such a boundary region of the insulating matrix layer functions as a gate insulating layer. This boundary region may exist in the first layer of the insulating matrix layer, may exist in the second layer of the insulating matrix layer, or may be present in the first layer of the insulating matrix layer. And may be present in the second layer.

In order to achieve the above object, a method of manufacturing a field effect transistor according to the third aspect of the present invention includes:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
It has a laminated structure of an insulating matrix layer and an insulating polymer material layer,
A method of manufacturing a field effect transistor in which a gate insulating layer is constituted by an insulating polymer material layer,
The method includes a step of impregnating a conductive polymer material into an insulating matrix layer that constitutes a semiconductor layer.

In the method of manufacturing the field effect transistor according to the third aspect of the present invention,
(1) A method of forming a gate electrode before impregnating a conductive polymer material into an insulating matrix layer to constitute a semiconductor layer (2) A conductive polymer material to an insulating matrix layer to constitute a semiconductor layer Two methods of forming the gate electrode after impregnating with are included.

  Furthermore, in the method for manufacturing a field effect transistor according to the third aspect of the present invention, it is desirable to form source / drain electrodes in the source / drain regions. In the case of (1), it is preferable to carry out after impregnating a conductive polymer material into the insulating matrix layer that constitutes the semiconductor layer, and in the case of (2), the insulating matrix that constitutes the semiconductor layer. This is preferably performed after the layer is impregnated with the conductive polymer material and before the gate electrode is formed or after the gate electrode is formed.

  In the method for manufacturing a field effect transistor according to the third aspect of the present invention, the insulating matrix layer and the insulating polymer are impregnated before impregnating the insulating matrix layer to form the semiconductor layer with the conductive polymer material. It can be set as the structure including the process of laminating | stacking a material layer. In addition, the manufacturing method of the field effect transistor of such a structure is called the manufacturing method of the field effect transistor which concerns on the 3A aspect of this invention for convenience.

In the method of manufacturing the field effect transistor according to the aspect 3A of the present invention,
(1) A method of forming a gate electrode after laminating an insulating matrix layer and an insulating polymer material layer, and then impregnating the insulating matrix layer constituting the semiconductor layer with a conductive polymer material (2 2) A method of forming a gate electrode after impregnating a conductive polymer material into an insulating matrix layer to constitute a semiconductor layer is included.

  Furthermore, in the method for manufacturing a field effect transistor according to the third aspect of the present invention, it is desirable to form source / drain electrodes in the source / drain regions. In the case of (1), it is preferable to carry out after impregnating a conductive polymer material into the insulating matrix layer that constitutes the semiconductor layer, and in the case of (2), the insulating matrix that constitutes the semiconductor layer. This is preferably performed after the layer is impregnated with the conductive polymer material and before the gate electrode is formed or after the gate electrode is formed.

  Alternatively, in the method of manufacturing the field effect transistor according to the third aspect of the present invention, the insulating matrix layer that should constitute the semiconductor layer is impregnated with the conductive polymer material, and then the insulating matrix layer and the insulating matrix layer are insulated. It can be set as the structure including the process of laminating | stacking a polymeric material layer. In addition, the manufacturing method of the field effect transistor of such a structure is called the manufacturing method of the field effect transistor which concerns on the 3B aspect of this invention for convenience.

  In the method for manufacturing a field effect transistor according to the third aspect of the present invention, it is desirable to form the gate electrode after laminating the insulating matrix layer and the insulating polymer material layer. In this case, it is desirable to form source / drain electrodes in the source / drain regions. However, these source / drain electrodes are formed after the insulating matrix layer and the insulating polymer material layer are laminated. Thus, it is preferably performed before the gate electrode is formed or after the gate electrode is formed.

  In the method of manufacturing the field effect transistor according to the third aspect of the present invention including the third A aspect and the third B aspect, the insulating matrix layer in the vicinity of the interface between the insulating polymer material layer and the insulating matrix layer In some cases, there is a boundary region that is not impregnated with the conductive polymer material. The boundary region formed by such an insulating matrix layer functions as a gate insulating layer.

In order to achieve the above object, a method of manufacturing a field effect transistor according to the fourth aspect of the present invention includes:
(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
It has a laminated structure of an insulating matrix layer and an insulating material layer,
A method of manufacturing a field effect transistor in which a gate insulating layer is constituted by an insulating material layer,
The method includes a step of impregnating a conductive polymer material into an insulating matrix layer that constitutes a semiconductor layer after transferring and fixing the insulating material layer on one surface of the insulating matrix layer.

In the method of manufacturing a field effect transistor according to the fourth aspect of the present invention,
(1) A method of forming a gate electrode before impregnating a conductive polymer material into an insulating matrix layer to constitute a semiconductor layer (2) A conductive polymer material to an insulating matrix layer to constitute a semiconductor layer Two methods of forming the gate electrode after impregnating with are included.

  Furthermore, in the method for manufacturing a field effect transistor according to the fourth aspect of the present invention, it is desirable to form source / drain electrodes in the source / drain regions. In the case of the above (1), it is preferably performed after impregnating the conductive polymer material in the portion of the insulating matrix layer that constitutes the semiconductor layer, and in the case of the above (2), the insulation that constitutes the semiconductor layer. This is preferably performed after the conductive matrix layer is impregnated with the conductive polymer material and before the gate electrode is formed or after the gate electrode is formed.

  In the method of manufacturing a field effect transistor according to the fourth aspect of the present invention, the insulating matrix layer in the vicinity of the interface between the insulating material layer and the insulating matrix layer is not impregnated with the conductive polymer material. In some cases, the boundary region constituted by such an insulating matrix layer functions as a gate insulating layer.

  The field effect transistor according to the first aspect of the present invention including the 1A aspect, the field effect transistor according to the third aspect of the present invention, or the present invention including the 1A aspect and the 1B aspect. In the method of manufacturing the field effect transistor according to the third aspect of the present invention, including the method of manufacturing the field effect transistor according to the first aspect of the present invention, the mode of 3A, and the mode of 3B, an insulating matrix is provided. The layer is preferably made of a porous organic insulating material. Alternatively, in these cases, the insulating matrix layer is preferably made of paper, made of cloth including woven fabric and non-woven fabric, or made of wood.

  Further, in the field effect transistor according to the second aspect of the present invention including the second A aspect, or the method of manufacturing the field effect transistor according to the second aspect of the present invention including the second A aspect. The insulating matrix layer having a two-layer structure is preferably made of a porous organic insulating material. Alternatively, in these cases, the insulating matrix layer having a two-layer laminated structure is preferably made of paper, made of cloth including woven fabric and non-woven fabric, or made of wood. The material constituting the first layer of the insulating matrix layer and the material constituting the second layer of the insulating matrix layer may be the same material, or the same or similar materials. Alternatively, different materials may be used. More specifically, the following combinations can be given as a combination of (material constituting the first layer of the insulating matrix layer / material constituting the second layer of the insulating matrix layer).

1st layer 2nd layer Paper Paper Paper Cloth Paper Wood Cloth Cloth Cloth Paper Cloth Wood Wood Wood Wood Paper Paper Wood Cloth

  Furthermore, in the field effect transistor according to the fourth aspect of the present invention or the method of manufacturing the field effect transistor according to the fourth aspect of the present invention, the insulating matrix layer is made of porous organic insulation. Preferably it consists of a material. Alternatively, in these cases, the insulating matrix layer is preferably made of paper.

  Field effect transistor according to the first aspect of the present invention including the first aspect A, field effect transistor according to the second aspect of the present invention including the second A aspect, the third aspect of the present invention, the fourth The field effect transistor according to the embodiment of the present invention, or the manufacturing method of the field effect transistor according to the first embodiment of the present invention including the 1A embodiment and 1B embodiment, and the second embodiment of the present invention including the 2A embodiment A method for manufacturing a field effect transistor according to the second aspect, a method for manufacturing a field effect transistor according to the third aspect of the present invention including the third aspect, the third A aspect, and the third aspect, and the fourth aspect of the present invention. In the method for producing a field effect transistor, the conductive polymer material is preferably poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid (PEDOT / PSS). The structural formula (1) of poly (3,4-ethylenedioxythiophene) and the structural formula (2) of polystyrene sulfonic acid are shown in FIG.

Alternatively, as the conductive polymer material, for example, a heterocyclic conjugated conductive polymer and a heteroatom-containing conjugated conductive polymer exemplified below can be used. In the structural formula, “R” and “R ′” mean an alkyl group (C _n H _{2n + 1} ).

[Heterocyclic conjugated conductive polymer]
Polypyrrole [see structural formula (3) in FIG. 1]
Polyfuran [see structural formula (4) in FIG. 1]
Polythiophene [see structural formula (5) in FIG. 1]
Polyselenophene [see structural formula (6) in FIG. 1]
Polyterlophene [see structural formula (7) in FIG. 1]
Poly (3-alkylthiophene) [see structural formula (8) in FIG. 1]
Poly (3-thiophene-β-ethanesulfonic acid) [see structural formula (9) in FIG. 1]
Poly (N-alkylpyrrole) [see structural formula (10) in FIG. 2]
Poly (3-alkylpyrrole) [see structural formula (11) in FIG. 2]
Poly (3,4-dialkylpyrrole) [see structural formula (12) in FIG. 2]
Poly (2,2′-thienylpyrrole) [see structural formula (13) in FIG. 2]

[Containing heteroatom-containing conductive polymer]
Polyaniline [see structural formula (14) in FIG. 2]
Poly (dibenzothiophene sulfide) [see structural formula (15) in FIG. 2]

  As a method of impregnating a conductive polymer material into a portion of an insulating matrix layer that constitutes a semiconductor layer, a spin coat method, an air doctor coater method, a blade coater method, a rod coater method, a knife coater method, a squeeze coater method, reverse Roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, various printing methods, etc. A method suitable for the above may be selected. Alternatively, by impregnating the conductive polymer material at the time of manufacturing the insulating matrix layer, it is possible to obtain an insulating matrix layer impregnated with the conductive polymer material when the manufacturing of the insulating matrix layer is completed. Further, as a method for impregnating the insulating polymer layer that constitutes the semiconductor layer with the conductive polymer material, a dipping method can be used in addition to the above-described method.

  In addition, as a method of impregnating the insulating polymer layer portion to constitute the gate insulating layer with the insulating polymer material, the spin coat method, the air doctor coater method, the blade coater method, the rod coater method, the knife coater method, the squeeze coater Of the insulating polymer material to be used, such as printing method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar coater method, various printing methods, etc. A method suitable for physical properties and characteristics may be selected. Alternatively, the insulating matrix layer impregnated with the insulating polymer material at the time of completion of the manufacturing of the insulating matrix layer can be obtained by impregnating the insulating polymer material during the manufacturing of the insulating matrix layer. Further, as a method of impregnating the insulating matrix layer that constitutes the gate insulating layer with the insulating polymer material, a dipping method can be used in addition to the above-described method.

  In the field effect transistor according to the second aspect of the present invention including the second A aspect, the insulating matrix layer has a two-layer laminated structure, and the second aspect of the present invention including the second A aspect includes In such a field effect transistor manufacturing method, the first layer of the insulating matrix layer impregnated with the conductive polymer material and the second of the insulating matrix layer impregnated with the insulating polymer material as necessary. Such a two-layer laminated structure can be obtained by bonding two insulating matrix layers using an adhesive, or a laminated structure can be obtained by a thermocompression bonding method. .

In the field effect transistor according to the first aspect of the present invention including the first A aspect, or alternatively, the manufacture of the field effect transistor according to the first aspect of the present invention including the first A aspect and the first B aspect. In the method, the thickness t _SC of the insulating matrix layer constituting the semiconductor layer and the thickness t _GI of the insulating matrix layer constituting the gate insulating layer are characteristics required for the field effect transistor. It may be determined appropriately based on the above.

In the field effect transistor according to the second aspect including the second A aspect and the method of manufacturing the field effect transistor according to the second aspect of the present invention including the second A aspect, the insulating property constituting the semiconductor layer The thickness t ₁ of the first layer of the matrix layer and the thickness t ₂ of the second layer of the insulating matrix layer constituting the gate insulating layer are based on characteristics required for the field effect transistor, etc. What is necessary is just to determine suitably.

In the field effect transistor according to the third aspect, and the method of manufacturing the field effect transistor according to the third aspect including the third and third aspects, the insulating matrix layer and the insulating polymer material layer are provided. As a method of laminating
(1) A method of laminating a film-like insulating polymer material layer on an insulating matrix layer (including wet laminating method, dry laminating method, solventless laminating method, thermal laminating method, etc.)
(2) Method for coating the insulating matrix layer with the solution constituting the insulating polymer material layer (3) Method for coating the insulating matrix layer with the emulsion constituting the insulating polymer material layer (4) High insulation properties A method of extruding and coating the material constituting the molecular material layer on the insulating matrix layer can be mentioned.

In the method of manufacturing the field effect transistor according to the third aspect, and the field effect transistor according to the third aspect including the third and third aspects, the thickness t _INS of the insulating polymer material layer is provided. The thickness t _SC of the insulating matrix layer constituting the semiconductor layer may be determined as appropriate based on characteristics required for the field effect transistor.

  In the field effect transistor according to the fourth aspect of the present invention or the method of manufacturing the field effect transistor according to the fourth aspect of the present invention, more specifically, the insulating material layer is, for example, dry indirect. The toner is composed of toner particles, a binder, a charge control agent and the like used in an electrostatic copying machine. The transfer / fixing of the insulating material layer to one surface of the insulating matrix layer can be performed more specifically using a dry indirect electrostatic copying machine. Here, “transfer” specifically means that an image on a photoreceptor in a dry indirect electrostatic copying machine is transferred onto one surface of an insulating matrix layer, and “fixing” specifically means Specifically, this means that an insulating material layer (for example, made of toner) after transfer is fixed on one surface of the insulating matrix layer.

In the field effect transistor according to the fourth aspect and the method of manufacturing the field effect transistor according to the fourth aspect, the thickness t ′ _INS of the insulating material layer, the thickness of the insulating matrix layer constituting the semiconductor layer The t _SC may be determined as appropriate based on the characteristics required for the field effect transistor.

  As materials constituting the gate electrode and the source / drain electrode, gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), palladium (Pd), nickel (Ni), chromium ( Examples thereof include metals such as Cr) and tungsten (W), various alloys, conductive particles made of these metals, and conductive particles of alloys containing these metals. Furthermore, the various conductive polymers mentioned above can also be mentioned. The gate electrode and the source / drain electrode are formed by physical vapor deposition (PVD method) exemplified by vacuum deposition or sputtering, or conductive paste or a solution of various conductive polymers described above. It can be formed based on the screen printing method used.

  Further, as an insulating polymer material, or as a material constituting the insulating polymer material layer in the field effect transistor and the manufacturing method thereof according to the third aspect of the present invention, a phenolic material such as a novolak resin or a resole resin is used. Resin; Modified phenol resin; Malee resin; Alkyd resin; Amino resin such as urea resin and melamine resin; Vinyl resin such as polyvinylphenol (PVP) resin, polyvinyl acetate resin, polyvinyl butyral resin, polyvinyl chloride resin, polyvinyl alcohol resin An epoxy resin; a polyester resin such as a polyethylene terephthalate (PET) resin and a polybutylene terephthalate (PBT) resin; a polystyrene resin; an acrylic resin; a silicone resin; a urethane resin; a polyamide 6, a polyamide 66, Polyamide resins such as polyamide MXD; polyimide resin; fluorine resin, polyethylene resin, olefin resin such as polypropylene resin, may be mentioned polycarbonate resin.

  Paper includes not only those mainly composed of plant fibers (cellulose fibers) but also those composed mainly of synthetic polymers and those mainly composed of inorganic substances, and are produced by wet papermaking or dry sheet forming methods. The More specifically, various types of dust-free paper (clean paper), thick white paper, tracing paper, Japanese paper, medium-quality paper, high-quality paper, coated paper, art paper, gravure paper, slip paper, vulcanized fiber, parchment (Sulfuric acid paper), synthetic paper, aluminum vapor-deposited paper, glass fiber paper, electrical insulating paper (electrolytic condenser paper, condenser thin paper, insulating thin paper), photographic paper, glassine paper, hatron paper, imitation paper, India paper However, it is not limited to these.

  The fabric may be a woven fabric or a non-woven fabric. Examples of the constituent material of the cloth include natural fibers such as cotton, synthetic fibers such as polyester, nylon, vinylon, and rayon, and inorganic fibers such as glass fibers. More specifically, examples of the cloth include felt, cotton, regenerated cellulose fiber (cupra), acetate, vinylidene, polyvinyl chloride, polyester, acrylic, polyethylene, and polypropylene, but are not limited thereto. It is not a thing.

  As wood, southern wood mainly made from lauan (meranchi, apiton), lindenwood, cedar, cypress, red pine, fir, tsuga, beech, oak, spruce, todomatsu, daffodil larch, Korean pine, red pine, spruce, balsa sheet However, the present invention is not limited to these examples.

  A field effect transistor may be placed on the substrate. Here, the base body can be composed of various films having insulating properties, for example. Further, the field effect transistor may be sealed with resin.

  In a field effect transistor, even if an organic material is used as a material for forming a channel formation region, as long as the gate insulating layer is formed of polyvinylphenol (PVP) resin or the like, and a bulk material such as glass is used for the substrate. There are limits to the reduction in manufacturing costs of field effect transistors and the flexibility and flexibility of field effect transistors. In the present invention, the semiconductor layer is composed of an insulating matrix layer impregnated with a conductive polymer material, and the gate insulating layer is an insulating matrix layer or an insulating polymer layer laminated on the insulating matrix layer. The layered structure of the semiconductor layer and the gate insulating layer is much simpler and simpler than the conventional technology. It is possible to form the desired shape and to obtain desired flexibility and flexibility.

  That is, in the present invention, the laminated structure of the semiconductor layer and the gate insulating layer constituting the FET can be formed more simply and simply than the conventional technique, and the insulating matrix layer Since the inherent flexibility and softness of the FET is maintained, the desired flexibility and softness can be obtained as a whole FET. Therefore, the superiority of organic electronics over silicon electronics can be realized. In addition, by using a flexible and flexible FET, it is possible to manufacture a sensing element that can be in close contact with a non-planar surface such as a living body or a TFT array as a controller for a flexible display. Note that PEDOT / PSS has high conductivity to the extent that it is used as an organic wiring material. On the contrary, it has been considered that PEDOT / PSS is not suitable as a material for forming a channel formation region of an FET. However, a composite material obtained by impregnating PEDOT / PSS into an insulating matrix layer such as paper, cloth, or wood exhibits semiconducting properties, and an FET whose IV curve is modulated by the voltage applied to the gate electrode. It has been found to show characteristics.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Using an insulating matrix layer shown in Table 1 below, as a conductive polymer material, a poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] aqueous solution (manufactured by Nagase ChemteX Corporation): A field-effect transistor (hereinafter abbreviated as FET) was prototyped using Denatron.

  In trial manufacture of FET, the PEDOT / PSS aqueous solution was apply | coated and infiltrated to the single side | surface of the insulating matrix layer using the commercially available brush, and it was then allowed to air dry. A schematic partial cross-sectional view of the sample 10 thus obtained is shown in FIG. The sample 10 made of the insulating matrix layer 11 has a portion 12 impregnated with the conductive polymer material and a portion 13 not impregnated with the conductive polymer material in the thickness direction. It was. The portion 12 impregnated with the conductive polymer material is not patterned at all.

  Then, as shown in the schematic partial cross-sectional view of FIG. 3B, the sample 10 is placed on the sample table 20 of a parameter analyzer manufactured by Hewlett-Packard Co., and a vacuum suction device is used. The sample 10 was brought into close contact with the sample stage 20. The portion 13 not impregnated with the conductive polymer material is in contact with the sample table 20.

  Next, two needle-shaped manual probers 21 (made of tungsten) provided in the parameter analyzer were brought into contact with the portion 12 of the sample 10 impregnated with the conductive polymer material (in FIG. 3C). (See schematic partial cross-sectional view). This state can be regarded as an FET having the sample stage 20 as a gate electrode and two needle-shaped manual probers 21 as source / drain electrodes. The interval between the two needle-shaped manual probers 21 was set to 1 mm to 2 mm.

While maintaining the state shown in FIG. 3 (C), while applying a voltage V _G which corresponds to the gate voltage to the sample stage 20, by applying a voltage V _SD between the two needle-like manual prober 21 The current I _SD flowing between the two needle-shaped manual probers 21 was measured. The insulating matrix layer 11 was composed of tracing paper, clean paper, felt, cotton, balsa sheet, and non-wood pulp. When the voltage V _G (corresponding to the gate voltage) is changed from 40 volts to −40 volts in increments of 5 volts, the current flowing between the two needle-shaped manual probers 21 (between the source region and the drain region) the flow corresponds to the current) I _SD is greatly modulated. Since V _G channel is closed in the case of negative, these samples can be considered to indicate an N-type behavior.

  In Example 1, the portion 12 impregnated with the conductive polymer material was not patterned at all. On the other hand, in Example 2, the portion impregnated with the conductive polymer material was in a patterned state.

  Specifically, in Example 2, plain paper copy paper of Fuji Xerox Office Supply Co., Ltd. is used, and a pattern 30 as shown in the schematic plan view of FIG. Printed on plain paper copy paper (corresponding to the insulating matrix layer 11). A gap 31 between the pattern 30 and the pattern 30 was set as an interval corresponding to 3 points. Then, the PEDOT / PSS aqueous solution was applied and penetrated from one side of the plain paper copy paper with a commercial brush only on one side, and then naturally dried. FIG. 4B shows a schematic partial cross-sectional view along the arrow BB in FIG.

  As shown in FIG. 4B, in the gap 31 portion of the insulating matrix layer 11 made of plain paper copy paper, a portion 12 impregnated with a conductive polymer material in the thickness direction. And a portion 13 that is not impregnated with the conductive polymer material. The portion 14 of the insulating matrix layer 11 covered with the pattern 30 is not impregnated with the conductive polymer material.

Based on the obtained sample thus, in the same manner as in Example 1, the portion 12 where the conductive polymer material of the gap 31 is impregnated against the two needle-like manual prober 21, applying a voltage V _G However, the voltage V _SD is applied between the two needle-shaped manual probers 21 (see the schematic plan view of FIG. 4C), and between the two needle-shaped manual probers 21. The current I _SD flowing through was measured. When the voltage V _G (corresponding to the gate voltage) is changed from 40 volts to −40 volts in increments of 5 volts, the current flowing between the two needle-shaped manual probers 21 (between the source region and the drain region) the flow corresponds to the current) I _SD is greatly modulated. Since V _G channel is closed in the case of negative, these samples can be considered to indicate an N-type behavior.

  Example 3 relates to the FET according to the first aspect of the present invention and the method for manufacturing the FET according to the first aspect of the present invention.

  As shown in the schematic partial cross-sectional view of FIG. 5A, the FET 40 in Example 3 includes a source / drain region 65 and a channel formation region 64 formed in the semiconductor layer 63, and a gate insulating layer 62. A gate electrode 60 is provided so as to face the channel formation region 64 via the. The insulating matrix layer 50 constituting the semiconductor layer 63 and the gate insulating layer 62 is provided, and the insulating matrix layer portion 51 constituting the semiconductor layer 63 is impregnated with a conductive polymer material. The insulating matrix layer 50 is made of a porous organic insulating material, or is made of paper, cloth, or wood. The conductive polymer material is made of PEDOT / PSS. The insulating matrix layer portion 52 constituting the gate insulating layer 62 is not impregnated with a conductive polymer material.

  Such an FET 40 can be manufactured by the following method. That is, for example, the insulating matrix layer 50 is prepared, and the PEDOT / PSS aqueous solution is impregnated from one surface (first surface) of the insulating matrix layer 50 and dried. As a result, the conductive polymer material can be impregnated in the portion 51 of the insulating matrix layer constituting the semiconductor layer 63. Thereafter, a source (drain) electrode 61 is formed on one surface (first surface) of the insulating matrix layer 50 by printing a gold (Au) paste by screen printing, and the other side of the insulating matrix layer 50 is formed. The gate electrode 60 is formed by printing a gold (Au) paste on the surface (second surface) by a screen printing method. Note that the procedure for forming the source / drain electrode 61 and the gate electrode 60 may be reversed. Further, before impregnating the PEDOT / PSS aqueous solution from one surface (first surface) of the insulating matrix layer 50, the gate electrode 60 is formed in advance on the other surface (21st surface) of the insulating matrix layer 50. It may be left.

  Alternatively, the insulating matrix layer portion 52 constituting the gate insulating layer 62 may be impregnated with an insulating polymer material. In such an FET 40, the insulating matrix layer portion 51 that constitutes the semiconductor layer 63 is impregnated with a conductive polymer material, and then the insulating matrix layer portion 52 that constitutes the gate insulating layer 62 is insulated. It can be obtained by impregnating a polymer material. In this case, (1) the gate electrode 60 may be formed before the conductive polymer material is impregnated in the portion 51 of the insulating matrix layer to form the semiconductor layer 63, or (2) the semiconductor layer. After impregnating the conductive matrix material into the insulating matrix layer portion 51 to constitute 63, the gate electrode 60 is formed, and then the insulating matrix layer portion 52 to constitute the gate insulating layer 62 is insulated. Alternatively, the gate electrode 60 may be formed after impregnating the insulating polymer layer portion 52 of the insulating matrix layer which should constitute the gate insulating layer 62 with the insulating polymer material. May be.

  Furthermore, in these cases, it is desirable to form the source / drain electrodes 61 in the source / drain regions 65. However, the formation of these source / drain electrodes 61 is performed in the semiconductor layer in the cases (1) and (2) above. This may be performed after impregnating the conductive matrix material into the insulating matrix layer portion 51 that constitutes 63, and in the case of (3) above, the insulating matrix layer portion 52 that constitutes the gate insulating layer 62. May be performed after impregnating with an insulating polymer material before forming the gate electrode 60 or after forming the gate electrode 60.

  Alternatively, a portion 51 of the insulating matrix layer 50 to form the semiconductor layer 63 after impregnating the insulating matrix layer portion 52 to form the gate insulating layer 62 with the insulating polymer material made of the above-described material. Can be obtained by impregnating with a conductive polymer material. In this case, (1) the gate electrode 60 may be formed before impregnating the insulating matrix layer portion 52 to form the gate insulating layer 62 with the insulating polymer material, or (2) the gate. After impregnating the insulating polymer layer portion 52 to form the insulating layer 62 with the insulating polymer material, the gate electrode 60 is formed, and then the insulating matrix layer portion 51 to form the semiconductor layer 63 is formed. The conductive polymer material may be impregnated, or (3) the gate electrode 60 is formed after the conductive polymer material is impregnated in the insulating matrix layer portion 51 to constitute the semiconductor layer 63. May be.

  Furthermore, in these cases, the source / drain electrodes 61 are formed in the source / drain regions 65. The formation of these source / drain electrodes 61 constitutes the semiconductor layer 63 in the cases (1) and (2) above. This may be performed after impregnating the portion 51 of the insulating matrix layer to be impregnated with the conductive polymer material. In the case of the above (3), the portion 51 of the insulating matrix layer that should constitute the semiconductor layer 63 is electrically conductive. This may be performed after the molecular material is impregnated and before the gate electrode 60 is formed or after the gate electrode 60 is formed.

  Example 4 relates to the FET according to the second aspect of the present invention and the method for manufacturing the FET according to the second aspect of the present invention.

  As shown in the schematic partial cross-sectional view of FIG. 5B, the FET 40 </ b> A according to the fourth embodiment includes a source / drain region 65 and a channel formation region 64 formed in the semiconductor layer 63, and a gate insulating layer 62. A gate electrode 60 is provided so as to face the channel formation region 64 via the. An insulating matrix layer 70 having a two-layer structure constituting the semiconductor layer 63 and the gate insulating layer 62 is provided, and the first layer 71 of the insulating matrix layer 70 constituting the semiconductor layer 63 is provided with a conductive polymer. The gate insulating layer 62 is constituted by the second layer 72 of the insulating matrix layer 70 impregnated with the material. The insulating matrix layer 70 having a two-layer structure is made of a porous organic insulating material, or is made of paper, cloth, or wood. The conductive polymer material is made of PEDOT / PSS. The second layer 72 of the insulating matrix layer 70 is impregnated with an insulating polymer material. In some cases, the second layer 72 of the insulating matrix layer 70 may not be impregnated with the insulating polymer material.

  Such an FET 40A can be manufactured by the following method. That is, for example, the second layer 72 of the insulating matrix layer 70 is prepared, and a solution in which the insulating polymer material is dissolved is applied from the other surface (second surface) of the second layer 72 of the insulating matrix layer 70. Impregnate and dry. Meanwhile, a first layer 71 of an insulating matrix layer 70 having an adhesive layer formed on one surface (first surface) is prepared, and an aqueous PEDOT / PSS solution is applied to the first layer 71 of the insulating matrix layer 70. Impregnation from the other surface (second surface) and drying. Next, one surface (first surface) of the first layer 71 of the insulating matrix layer 70 and the other surface (second surface) of the second layer 72 of the insulating matrix layer 70 are bonded together. Thus, the first layer 71 of the insulating matrix layer 70 impregnated with the conductive polymer material and the second layer 72 of the insulating matrix layer 70 impregnated with the insulating polymer material are laminated. Can do. Thereafter, a source / drain electrode 61 is formed on the other surface (second surface) of the first layer 71 of the insulating matrix layer 70 by printing a gold (Au) paste by a screen printing method. The gate electrode 60 is formed on one surface (first surface) of the second layer 72 of the conductive matrix layer 70 by printing a gold (Au) paste by a screen printing method. Note that the procedure for forming the source / drain electrode 61 and the gate electrode 60 may be reversed. In addition, before the first layer 71 of the insulating matrix layer 70 and the second layer 72 of the insulating matrix layer 70 are stacked, one surface of the second layer 72 of the insulating matrix layer 70 (first surface) The gate electrode 60 may be formed on the surface. Further, before the first layer 71 of the insulating matrix layer 70 and the second layer 72 of the insulating matrix layer 70 are stacked, the other surface (first surface) of the first layer 71 of the insulating matrix layer 70 (the first layer 71). The source / drain electrode 61 may be formed on the second surface.

  Example 5 relates to the FET according to the third aspect of the present invention and the method for manufacturing the FET according to the third aspect of the present invention.

  As shown in the schematic partial cross-sectional view of FIG. 6A, the FET 40B in Example 5 includes a source / drain region 65 and a channel forming region 64 formed in the semiconductor layer 63, and a gate insulating layer 62. A gate electrode 60 is provided so as to face the channel formation region 64 via the. The insulating matrix layer 80 and the insulating polymer material layer 82 have a laminated structure, the insulating polymer material layer 82 includes the gate insulating layer 62, and the insulating matrix layer 80 constituting the semiconductor layer 63 is formed on the insulating matrix layer 80. Is impregnated with a conductive polymer material. The insulating matrix layer 80 is made of a porous organic insulating material, or is made of paper, cloth, or wood. The conductive polymer material is made of PEDOT / PSS.

  Such an FET 40B can be manufactured by the following method. That is, a laminated structure of the insulating matrix layer 80 and the insulating polymer material layer 82 is prepared, and an aqueous PEDOT / PSS solution is impregnated from the surface of the insulating matrix layer 80 and dried. Thereafter, a gate electrode 60 made of, for example, gold (Au) is formed on the laminated structure of the insulating matrix layer 80 and the insulating polymer material layer 82, and further, the insulating matrix impregnated with PEDOT / PSS. A source / drain electrode 61 is formed on the layer 80 by printing a gold (Au) paste by a screen printing method. Note that the procedure for forming the source / drain electrode 61 and the gate electrode 60 may be reversed. Alternatively, the gate electrode 60 may be formed before the conductive matrix material is impregnated into the insulating matrix layer 80 that constitutes the semiconductor layer 63.

  Alternatively, the insulating matrix layer 80 and the insulating polymer material layer 82 may be laminated before the insulating matrix layer 80 is impregnated with the conductive polymer material. In this case, (1) after the insulating matrix layer 80 and the insulating polymer material layer 82 are laminated, the gate electrode 60 is formed, and then the conductive material is electrically connected to the insulating matrix layer 80 to form the semiconductor layer 63. Alternatively, the gate electrode 60 may be formed after impregnating the conductive polymer material, or (2) impregnating the insulating matrix layer 80 that constitutes the semiconductor layer 63 with the conductive polymer material. Good. Further, in the case of (1) above, the source / drain electrode 61 may be formed after impregnating the insulating matrix layer 80 that constitutes the semiconductor layer 63 with a conductive polymer material. ), After the conductive polymer material is impregnated into the insulating matrix layer 80 that constitutes the semiconductor layer 63 and before the gate electrode 60 is formed or after the gate electrode 60 is formed. Good.

  Alternatively, the insulating matrix layer 80 and the insulating polymer material layer 82 may be laminated after impregnating the insulating matrix layer 80 with a conductive polymer material. In this case, the source / drain electrode 61 is formed after the insulating matrix layer 80 and the insulating polymer material layer 82 are stacked and before the gate electrode 60 is formed or the gate electrode 60 is formed. What is necessary is just to carry out after forming.

  Example 6 relates to the FET according to the fourth aspect of the present invention and the method for manufacturing the FET according to the fourth aspect of the present invention.

  As shown in the schematic partial cross-sectional view of FIG. 6B, the FET 40 </ b> C in Example 6 includes a source / drain region 65 and a channel formation region 64 formed in the semiconductor layer 63, and a gate insulating layer 62. A gate electrode 60 is provided so as to face the channel formation region 64 via the. The insulating matrix layer 90 and the insulating material layer 92 transferred and fixed on one surface of the insulating matrix layer 90 are provided, and the insulating material layer 92 constitutes the gate insulating layer 62. The semiconductor layer An insulating matrix layer 90 constituting 63 is impregnated with a conductive polymer material. The insulating matrix layer 90 is made of a porous organic insulating material, or is made of paper, cloth, or wood. The conductive polymer material is made of PEDOT / PSS. Furthermore, the insulating material layer 92 is made of toner composed of toner particles, a binder, a charge control agent, and the like, which are used in, for example, a dry indirect electrostatic copying machine.

  Such an FET 40C can be manufactured by the following method. That is, by using a dry indirect electrostatic copying machine, the insulating material layer 92 is transferred and fixed on one surface of the insulating matrix layer 90 made of, for example, plain paper copy paper. The pattern of the insulating material layer 92 may be matched with the pattern of the gate insulating layer 62, for example, but is not limited to such a pattern. Thereafter, the insulating matrix layer 90 that constitutes the semiconductor layer 63 is impregnated with a conductive polymer material and dried. Next, a gate electrode 60 made of, for example, gold (Au) is formed on the laminated structure of the insulating matrix layer 90 and the insulating material layer 92, and further, the insulating matrix layer 90 impregnated with PEDOT / PSS is formed. On the top, the source / drain electrode 61 is formed by printing a gold (Au) paste by a screen printing method. Note that the gate electrode 60 may be formed before impregnating the insulating matrix layer 90 to form the semiconductor layer 63 with the conductive polymer material.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these. The structure and manufacturing method of the FET are examples, and can be changed as appropriate. In the FET described in the embodiment, the surface on which the gate electrode is formed is different from the surface on which the source / drain electrode is formed. However, these electrodes may be formed on the same surface. . For example, as shown in a schematic partial cross-sectional view in FIG. 7, in Example 5, a structure in which an insulating polymer material layer 82 </ b> A is formed on the surface of the insulating matrix layer 80 may be adopted. it can.

FIG. 1 illustrates a structural formula of a conductive polymer material suitable for use in the present invention. FIG. 2 illustrates a structural formula of a conductive polymer material suitable for use in the present invention. FIG. 3A is a schematic partial cross-sectional view of the sample obtained in Example 1, and FIG. 3B schematically shows a state where the sample is placed on the sample stage. FIG. 3C is a partial cross-sectional view schematically showing a state in which the characteristics of the sample are measured. 4A is a schematic diagram of the sample obtained in Example 2, and FIG. 4B is an arrow B in FIG. 4A of the sample obtained in Example 2. FIG. 4C is a schematic partial cross-sectional view along -B, and FIG. 4C is a diagram schematically showing a state in which the characteristics of the sample are measured. 5A and 5B are schematic partial cross-sectional views of the field effect transistors of Example 3 and Example 4. FIG. 6A and 6B are schematic partial cross-sectional views of the field effect transistors of Example 5 and Example 6. FIG. FIG. 7 is a schematic partial cross-sectional view of a modified example of the field effect transistor according to the fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Sample, 11 ... Insulating matrix layer, 12 ... Part impregnated with conductive polymer material of insulating matrix layer, 13, 14 ... High conductivity of insulating matrix layer Part not impregnated with molecular material, 20 ... Sample stand, 21 ... Manual prober, 30 ... Pattern, 31 ... Gap between patterns, 40, 40A, 40B, 40C ..Field effect type transistors (FET), 50, 70, 80, 90... Insulating matrix layer, 51... Insulating matrix layer constituting semiconductor layer, 52. Part of insulating matrix layer, 60 ... gate electrode, 61 ... source / drain electrode, 62 ... gate insulating layer, 63 ... semiconductor layer, 64 ... channel formation region, 65 ...・Source / drain region, 71 ... first layer of insulating matrix layer, 72 ... second layer of insulating matrix layer, 82, 82A ... insulating polymer material layer, 92 ...・ Insulating material layer

Claims (43)

(A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
Comprising one insulating matrix layer constituting a semiconductor layer and a gate insulating layer;
A field effect transistor, wherein a portion of an insulating matrix layer constituting a semiconductor layer is impregnated with a conductive polymer material. 2. The field effect transistor according to claim 1, wherein the insulating matrix layer constituting the gate insulating layer is impregnated with an insulating polymer material. 3. The field effect transistor according to claim 1, wherein the insulating matrix layer is made of paper. 3. The field effect transistor according to claim 1, wherein the insulating matrix layer is made of a cloth. 3. The field effect transistor according to claim 1, wherein the insulating matrix layer is made of wood. 3. The field effect transistor according to claim 1, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid. (A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
Comprising an insulating matrix layer having a two-layer structure constituting a semiconductor layer and a gate insulating layer;
The first layer of the insulating matrix layer constituting the semiconductor layer is impregnated with a conductive polymer material,
A field effect transistor, wherein a gate insulating layer is constituted by the second layer of the insulating matrix layer. 8. The field effect transistor according to claim 7, wherein the second layer of the insulating matrix layer is impregnated with an insulating polymer material. 9. The field effect transistor according to claim 7, wherein the insulating matrix layer having a two-layer structure is made of paper. 9. The field effect transistor according to claim 7, wherein the insulating matrix layer having a two-layer structure is made of cloth. 9. The field effect transistor according to claim 7, wherein the insulating matrix layer having a two-layer structure is made of wood. 9. The field effect transistor according to claim 7, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid. (A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
It has a laminated structure of an insulating matrix layer and an insulating polymer material layer,
A gate insulating layer is constituted by the insulating polymer material layer,
A field effect transistor, wherein an insulating matrix layer constituting a semiconductor layer is impregnated with a conductive polymer material. 14. The field effect transistor according to claim 13, wherein the insulating matrix layer is made of paper. 14. The field effect transistor according to claim 13, wherein the insulating matrix layer is made of cloth. 14. The field effect transistor according to claim 13, wherein the insulating matrix layer is made of wood. 14. The field effect transistor according to claim 13, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid. (A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
A field effect transistor comprising:
It has a laminated structure of an insulating matrix layer and an insulating material layer transferred and fixed to one surface of the insulating matrix layer,
The insulating material layer constitutes the gate insulating layer,
A field effect transistor, wherein an insulating matrix layer constituting a semiconductor layer is impregnated with a conductive polymer material. 19. The field effect transistor according to claim 18, wherein the insulating matrix layer is made of paper. The field effect transistor according to claim 18, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid. (A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
A method of manufacturing a field effect transistor comprising a single insulating matrix layer constituting a semiconductor layer and a gate insulating layer,
A method of manufacturing a field effect transistor, comprising a step of impregnating a portion of an insulating matrix layer that constitutes a semiconductor layer with a conductive polymer material. A step of impregnating a portion of the insulating matrix layer that should constitute the semiconductor layer with the conductive polymer material and then impregnating the portion of the insulating matrix layer that should constitute the gate insulating layer with the insulating polymer material. The method of manufacturing a field effect transistor according to claim 21. A step of impregnating an insulating polymer material into a portion of the insulating matrix layer to constitute the gate insulating layer before impregnating the portion of the insulating matrix layer to constitute the semiconductor layer with the conductive polymer material. The method of manufacturing a field effect transistor according to claim 21. The method for manufacturing a field effect transistor according to any one of claims 21 to 23, wherein the insulating matrix layer is made of paper. The method for manufacturing a field effect transistor according to any one of claims 21 to 23, wherein the insulating matrix layer is made of cloth. The method for manufacturing a field effect transistor according to any one of claims 21 to 23, wherein the insulating matrix layer is made of wood. 24. The manufacturing of a field effect transistor according to claim 21, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid. Method. (A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
Comprising an insulating matrix layer having a two-layer structure constituting a semiconductor layer and a gate insulating layer;
A method of manufacturing a field effect transistor in which a semiconductor layer is formed by a first layer of an insulating matrix layer and a gate insulating layer is formed by a second layer of the insulating matrix layer,
A method for manufacturing a field-effect transistor, comprising a step of laminating a first layer of an insulating matrix layer impregnated with a conductive polymer material and a second layer of the insulating matrix layer. 29. The method of manufacturing a field effect transistor according to claim 28, wherein the second layer of the insulating matrix layer is impregnated with an insulating polymer material. 30. The method of manufacturing a field effect transistor according to claim 28 or 29, wherein the insulating matrix layer having a two-layer structure is made of paper. 30. The method of manufacturing a field effect transistor according to claim 28, wherein the insulating matrix layer having a two-layer structure is made of cloth. 30. The method of manufacturing a field effect transistor according to claim 28, wherein the insulating matrix layer having a two-layer structure is made of wood. 30. The method of manufacturing a field effect transistor according to claim 28, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid. (A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
It has a laminated structure of an insulating matrix layer and an insulating polymer material layer,
A method of manufacturing a field effect transistor in which a gate insulating layer is constituted by an insulating polymer material layer,
A method for manufacturing a field effect transistor, comprising a step of impregnating a conductive polymer material into an insulating matrix layer to constitute a semiconductor layer. 35. The method according to claim 34, further comprising a step of laminating the insulating matrix layer and the insulating polymer material layer before impregnating the insulating matrix layer to constitute the semiconductor layer with the conductive polymer material. A method of manufacturing a field effect transistor. 35. The method according to claim 34, further comprising a step of laminating the insulating matrix layer and the insulating polymer material layer after impregnating the insulating matrix layer to constitute the semiconductor layer with the conductive polymer material. A method of manufacturing a field effect transistor. 37. The method of manufacturing a field effect transistor according to any one of claims 34 to 36, wherein the insulating matrix layer is made of paper. 37. The method of manufacturing a field effect transistor according to claim 34, wherein the insulating matrix layer is made of a cloth. 37. The method of manufacturing a field effect transistor according to claim 34, wherein the insulating matrix layer is made of wood. 37. The manufacture of a field effect transistor according to claim 34, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid. Method. (A) a source / drain region and a channel formation region formed in the semiconductor layer, and
(B) a gate electrode provided to face the channel formation region with the gate insulating layer interposed therebetween,
Have
It has a laminated structure of an insulating matrix layer and an insulating material layer,
A method of manufacturing a field effect transistor in which a gate insulating layer is constituted by an insulating material layer,
A field effect transistor comprising a step of impregnating a conductive polymer material into an insulating matrix layer to constitute a semiconductor layer after transferring and fixing an insulating material layer on one surface of the insulating matrix layer Manufacturing method. 42. The method of manufacturing a field effect transistor according to claim 41, wherein the insulating matrix layer is made of paper. The method for manufacturing a field effect transistor according to claim 41, wherein the conductive polymer material is poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid.

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