JP2005121718A - Plasma display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a driver of a PDP apparatus which uses a plasma display panel with a large driving capacity, using an existent driving IC. <P>SOLUTION: The plasma display apparatus is equipped with a plurality of electrodes A and Y and a plurality of drive circuits 11 and 12 for driving the plurality of electrodes, and the drive circuits 11 and 12 include at least one drive IC 21, having a plurality of outputs for independently outputting a plurality of driving signals and drive one electrode in combination with the plurality of driving signals outputted from the driving IC. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device such as a personal computer and a workstation, a flat-screen television, and a plasma display device (PDP device) used for displaying advertisements and information.

  In the AC type color PDP device, a two-electrode type, a three-electrode type, an address / display in which a period for defining a display cell (address period) and a display period (sustain period) for discharging for display lighting are sequentially shifted. There are various methods such as non-separation method and address / display separation method. Most systems of PDP devices have at least a configuration in which a plurality of electrodes provided in parallel with each other intersect, and each electrode needs to be driven independently. The present invention can be applied to any type of PDP apparatus as long as it is configured to independently drive a plurality of electrodes, but here it has been put into practical use and is most widely used. A three-electrode type address / display separation type PDP apparatus will be described as an example. However, the present invention is not limited to this.

  FIG. 1 is a diagram showing a basic configuration of a three-electrode type address / display separation type PDP apparatus. First (X) electrodes and second (Y) electrodes are alternately provided in parallel on a first substrate constituting the plasma display panel 10 and covered with a dielectric layer. A third (address) electrode extending in a direction perpendicular to the X and Y electrodes is provided on a second substrate facing the first substrate, and the electrode surface is covered with a dielectric layer. On the second substrate, a stripe-shaped partition wall extending in parallel with the address electrode between the address electrodes, or a two-dimensional lattice-shaped partition wall disposed between the address electrodes and between the set of the X and Y electrodes is further provided. After the phosphor layer is formed in the barrier rib, the first and second substrates are bonded to each other at a predetermined interval. A discharge space is formed between the first and second substrates, and a discharge gas mixed with neon, xenon, or the like is enclosed. A display cell is formed at the intersection of the pair of adjacent X and Y electrodes and the address electrode. In a PDP apparatus of a normal system other than the ALIS system, which will be described later, a display cell is formed between the same set of X electrodes and Y electrodes, and between the other adjacent X electrodes and Y electrodes. A display cell is not formed.

  As shown in FIG. 1, in addition to the plasma display panel 10, the PDP device supplies an address driver 11 for driving an address electrode, a Y scan driver 12 for driving a Y electrode, and a Y sustain signal to the Y scan driver 12. A Y sustain circuit 13, an X sustain circuit 14 that is driven to supply an X sustain signal to the X electrode, and a control circuit 15 that controls each part. As shown, the X sustain circuit 14 has only one output and drives the commonly connected X electrodes. On the other hand, the Y scan driver 12 drives the Y electrodes independently, and the address driver 11 drives the address electrodes independently.

  FIG. 2 is a diagram illustrating a driving waveform of the PDP apparatus of FIG. The basic drive sequence of the address / display separation type PDP device includes a reset period for making all display cells uniform, an address period for selecting display cells to be lit, and a sustain period for causing the selected display cells to emit light. Have. In the PDP device, only lighting / non-lighting of each display cell can be selected, and the intensity of light emission cannot be controlled. Therefore, one display frame is composed of a plurality of subframes having the basic drive sequence as shown in FIG. 2, and lighting / non-lighting of each display cell is selected in each subframe. Display. In order to perform gradation display efficiently, the luminance ratio of each sub-frame, that is, the number of sustain pulses applied in the sustain period of each sub-frame, for example, is set to be different such as 1: 2: 4: 8. .

  As shown in FIG. 2, in the reset period, the voltage Va is applied to all address electrodes, Vw is applied to the common X electrode, and 0 V is applied to all Y electrodes. As a result, a discharge occurs between the X electrode, the address electrode, and the Y electrode of all the display cells, and all the display cells become uniform. In the next address period, the voltage Vx is applied to the common X electrode, and -Vy1 is applied to all the Y electrodes, -Vy scan pulses are sequentially applied to the Y electrodes, and synchronized with the application of the scan pulses. An address pulse of voltage Va is applied to the address electrode of the display cell that is lit. An address discharge is generated between the Y electrode to which the scan pulse is applied and the address electrode to which the address pulse is applied, and wall charges are accumulated on the surface of the dielectric layer on the electrode of the display cell to be lit. By applying the address pulse while sequentially applying the scan pulse to all the Y electrodes, the display cells that are lit on the entire surface are selected. In the sustain period, a sustain pulse of the voltage Vs is alternately applied to the Y electrode and the X electrode while the voltage Va is applied to the address electrode. In the display cell in which wall charges are formed in the address period, the voltage due to the wall charges is superimposed on the voltage Vs of the sustain pulse and exceeds the discharge start voltage, so sustain discharge occurs. However, no wall charge is formed in the address period. In the display cell, since there is no voltage due to wall charges, only the sustain pulse voltage Vs does not exceed the discharge start voltage and no sustain discharge occurs. In a display cell in which a sustain discharge has occurred, wall charges having a reverse polarity are formed by the sustain discharge, so that a sustain discharge is generated when a sustain pulse is next applied to the X electrode. Thereafter, when the sustain pulse is repeatedly applied, the sustain discharge is repeated in the selected display cell.

  The configuration and driving waveforms of the PDP apparatus described in FIGS. 1 and 2 are examples, and various other configurations and driving methods have been proposed. Here, further detailed description is omitted, but the present invention is applicable to any PDP device.

  FIG. 3 is a diagram illustrating a configuration example of each drive circuit of the PDP device described with reference to FIGS. 1 and 2. The address driver 11 has a driver circuit 16 composed of two transistors AT1 and AT2 connected in series between the power supply of the voltage Va and the GND power supply for the number of address electrodes. A connection node between the transistors AT1 and AT2 is connected to each address electrode. When the transistor AT1 is turned on, the voltage Va is applied to the address electrode, and when the transistor AT2 is turned on, 0 V is applied to the address electrode.

  The Y scan driver 12 includes two transistors ST1 and ST2 connected in series between the power supply of the voltage −Vy1 and the power supply of the voltage −Vy, and two connected to the connection node of the two transistors ST1 and ST2. The driver circuits 17 composed of the diodes D1 and D2 are provided for the number of Y electrodes. The diode D1 is connected to the GND power supply via the transistor of the Y sustain circuit 13, and the diode D2 is connected to the power supply of the voltage Vs via the transistor of the Y sustain circuit 13. During the address period, when applying a scan pulse in a state where both transistors of the Y sustain circuit 13 are turned off, the transistor ST1 is turned on and the voltage −Vy1 is output, ST2 is turned off and ST2 is turned on simultaneously. Turn on. In the sustain period, ST1 and ST2 are turned off, and the two transistors of the Y sustain circuit 13 are alternately turned on and off. Thereby, Vs and GND are alternately applied from the Y sustain circuit 13 via the diodes D1 and D2.

  The X sustain circuit 14 has four transistors that operate as switches connected to the voltages Vw, Vx, Vs, and 0 V (GND), and applies a voltage corresponding to the X electrode by turning each transistor on. it can.

  Since the sustain discharge (sustain discharge) is performed between the X electrode and the Y electrode, the X electrode and the Y electrode are called sustain electrodes. The Y electrode is called a scan electrode because a scan pulse is applied. Here, the Y electrode is called a scan electrode, and the X electrode is called a sustain electrode.

  As described above, the Y scan driver 12 has a driver circuit 17 composed of two transistors ST1 and ST2 and two diodes D1 and D2 as many as the number of scan (Y) electrodes. Scan pulses are output sequentially. Therefore, the Y scan driver 12 further includes a shift register, and a signal indicating the output position of the scan pulse is sequentially shifted by the shift register, and the output of the shift register is input to the plurality of scan driver circuits 17. The address driver 11 has as many address circuits as driver circuits 16 each composed of transistors AT1 and AT2, and outputs an address pulse from each driver circuit 16. Therefore, the address driver 11 further includes a shift register, and the address data is sequentially shifted by the shift register, and when the shift for the length of the address data is completed, the output of the shift register is input to the plurality of driver circuits 16. Yes.

  As described above, a driver that outputs a plurality of drive signals independently generally requires a shift register for setting data to be output. Therefore, the Y scan driver 12 and the address driver 11 are used by using a shift IC, a latch circuit that latches the output of the shift register, and a driver IC that integrates a plurality of driver circuits that output drive signals according to the output of the latch circuit. Is generally realized. The driver IC used for the address driver 11 does not need to be provided with a diode, but the driver IC used for the Y scan driver 12 is provided with a diode.

  The number of driver circuits provided in the drive IC is 16 or 64. Currently, drive ICs having 64 driver circuits are widely used, and 64-bit shift registers and latches are correspondingly used. A circuit is provided. For example, if the plasma display panel shown in FIG. 1 has a 1024 × 768 display cell configuration, the scan driver 12 includes 12 64-bit drive ICs, which are cascade-connected. The address driver 11 is composed of 16 64-bit driving ICs, each bit of 16-bit display data is supplied to each IC, and the 16 64-bit driving ICs are operated in parallel.

JP-A-9-160525

  It is desirable for the drive IC to have specifications such as drive capability and the number of bits set according to the PDP device that is the product. However, if the number of manufactured drive ICs of that specification is sufficiently large due to the number of manufactured PDP devices. Since it takes a long time to commercialize a new drive IC and the problem of high cost, if a dedicated IC is designed and commercialized after determining the specifications of the PDP device, the shipment of the PDP device will be delayed, There is a problem of missing opportunities. Therefore, the driver of the PDP device may be realized by using an off-the-shelf drive IC that has already been commercialized.

  In recent years, the size of plasma display panels has been increased, and not only the number of electrodes has increased, but also the drive capacity and discharge current of each electrode have increased, and a drive IC having a high drive capacity has become necessary. ing. In particular, the ALIS PDP apparatus described in Patent Document 1 can realize a panel with the same number of display lines as that of a normal type with half the number of scanning electrodes and the number of sustain electrodes. However, since the drive capacity and discharge current of the scan electrode may increase to about twice that of the normal type, a drive IC having a significantly high drive capability is required.

  In other words, there is a problem that the performance of a PDP device using the drive IC is limited due to the limitation of the drive capability of the drive IC.

  In particular, in the case of a driving IC used in a PDP device, not only the driving capability of individual driver circuits but also heat generation due to the operation of the driver circuits is a big problem. For example, in the case of the Y scan driver 12, the portion constituted by the transistors ST1 and ST2 of each drive circuit is turned on only once during the address period. Therefore, if the drive capacity of the scan electrode increases, the heat generation of the drive circuit increases accordingly, but the influence of the heat generation is not so great. On the other hand, the portion constituted by the diodes D1 and D2 repeats the on / off operation in all the drive circuits 17 during the sustain period. Therefore, even if the on-resistance is smaller than that of the transistor, the heat generated in the entire IC. Becomes very large. In order to suppress heat generation, it is necessary to limit the number of sustain pulses in one frame, and there is a problem that the display luminance of the PDP device cannot be increased.

  In the case of the address driver 11, there is a possibility that all the driver circuits 16 in each drive IC repeat the on / off operation, and when the drive capacity and discharge current of the address electrode increase, the heat generation of the address driver increases accordingly. There is a problem.

  An object of the present invention is to realize a PDP device using a plasma display panel having a large electrode drive capacity by using an off-the-shelf drive IC.

  In order to achieve the above object, a plasma display device (PDP device) of the present invention is characterized in that a plurality of drive signals output from a drive IC are combined to drive one electrode.

  That is, the PDP device of the present invention is a plasma display device including a plurality of electrodes and a drive circuit that drives the plurality of electrodes, and the drive circuit can output a plurality of drive signals independently. And at least one driving IC having the output of the driving IC, and driving one electrode by combining a plurality of the driving signals of the driving IC.

  According to the present invention, since one electrode is driven by combining a plurality (n) of drive signals of the drive IC, the drive capability of one drive signal is a fraction (1 / n) of the plurality. Well, heat generation in the drive IC is similarly reduced.

  The electrode driven in this configuration is a scan electrode or an address electrode.

  When combining a plurality of drive signals, the drive signals to be combined may be a combination of drive signals output from the same drive IC or a combination of drive signals output from different drive ICs.

  When the drive signals output from the same drive IC are combined, it is necessary to control the two drive signals to be the same. On the other hand, when the drive signals output from different drive ICs are combined, the same control as in the past is performed, and the corresponding output terminals of the drive ICs are simply connected.

  However, when the drive signals output from different drive ICs are combined, there may be a slight difference in the rise and fall timing between the drive signals between the ICs due to manufacturing errors. There is a possibility that both the transistor that operates as the switch of the transistor and the transistor that operates as the switch on the low voltage side of the other IC are simultaneously turned on and a through current flows. Therefore, it is desirable to accurately adjust the operation timing of the driver circuit of each IC. When the drive signals output from the same drive IC are combined, there is almost no difference in timing within the same IC, and therefore the possibility of such a problem occurring is low.

  In general, a driving IC includes a shift register that sequentially shifts input data according to a clock, a latch circuit that latches and outputs an output of the shift register according to a latch signal, and a driving signal corresponding to each output of the latch circuit. In the case of using such a drive IC for a scan driver that combines drive signals output from the same drive IC, only clocks corresponding to the number (n) of drive signals to be combined are provided. One input data is continuously input, and a latch signal is generated for every clock (n) of the number of drive signals to be combined. Further, when such a driving IC is used for an address driver that combines driving signals output from the same driving IC, the same input data is continuously input by the number of clocks corresponding to the number of driving signals to be combined, A latch signal is generated when all the input data is available at the output of the shift register.

  The ALIS system PDP device described in Patent Document 1 is effective when the present invention is applied because the drive capacity of the scan electrodes is larger than that of a normal type PDP device having the same size.

  Not used for driving IC output due to the number of electrodes, the number of output terminal groups connecting electrodes and drivers, the number of electrodes per bundle of output terminal groups, the number of outputs of the driving IC, the ALIS method or the normal method, etc. There may be a case where an output is generated, that is, a remainder is generated in the output of the driving IC. In particular, when one electrode is driven by combining a plurality of drive signals as in the present invention, the remainder is likely to occur. In that case, if the remainder is distributed so that the number of unused drive signals of each of the plurality of drive ICs is substantially equal without concentrating the remainder on one or two drive ICs, heat is generated in each drive IC. Can be reduced.

  According to the present invention, a driver can be configured using an off-the-shelf drive IC even when the drive capacity and discharge current of the electrodes of the plasma display panel are large. As a result, the cost of the driver can be reduced, and the time to commercialization can be shortened.

  FIG. 4 is a diagram showing the configuration of the plasma display device (PDP device) of the first embodiment of the present invention. The first embodiment is an example in which the present invention is applied to an ALIS PDP apparatus described in Patent Document 1. Since details of the ALIS PDP apparatus are described in Patent Document 1, detailed description is omitted here, and only the points directly related to the present invention will be described briefly.

  In the ALIS plasma display panel 10, scan (Y) electrodes and sustain (X) electrodes are alternately arranged at equal intervals, and display lines are formed between the sustain electrodes adjacent to both sides of each scan electrode. The number of sustain electrodes is one more than the number N of scan electrodes. The ALIS system plasma display panel 10 of the first embodiment has 384 scanning electrodes, 385 sustain electrodes, and 1024 address electrodes, and 768 display lines are formed to provide 1024 × 768. A display cell is formed.

  In FIG. 4, odd-numbered display lines are formed between the sustain electrodes adjacent to the upper side of each scan electrode, and even-numbered display lines are formed between the sustain electrodes adjacent to the lower side of each scan electrode. The One frame includes an odd field and an even field, and an odd display line is displayed in the odd field, and an interlaced display is performed in which the even display line is displayed in the even field. Therefore, in the address period and the sustain period of the odd field, a voltage to be discharged is applied between each scan electrode that forms the odd display line and the sustain electrode on the upper side, and each scan that forms the even display line. A voltage for discharging is not applied between the electrode and the sustain electrode below the electrode. Similarly, in the address period and the sustain period of the even field, a discharge voltage is applied between each scan electrode forming the even-numbered display line and the sustain electrode below it to form the odd-numbered display line. A voltage to be discharged is not applied between each scan electrode and the sustain electrode above it.

  In order to enable such voltage application, odd-numbered sustain (X) electrodes are commonly connected to the odd-numbered X sustain circuit 14O, and even-numbered sustain (X) electrodes are commonly connected to the even-numbered X sustain circuit 14E. A voltage can be applied independently to the odd-numbered and even-numbered sustain electrodes. Further, the odd-numbered scan (Y) electrodes are respectively connected to the odd-numbered Y scan driver 120, and the even-numbered scan (Y) electrodes are respectively connected to the even-numbered Y scan driver 12E. The odd Y scan driver 12O and the even Y scan driver 12E are supplied with sustain pulses from the odd Y sustain circuit 13O and the even Y sustain circuit 13E.

  FIG. 5 is a diagram illustrating a driving waveform of one subframe in an odd field in the PDP apparatus according to the first embodiment.

  As shown in FIG. 5, in the reset period, voltage Va is applied to all address electrodes, Vw is applied to odd-numbered and even-numbered sustain (X) electrodes, and 0 V is applied to all scan (Y) electrodes. To do. As a result, a discharge is generated between the sustain electrodes, the address electrodes, and all the scan electrodes of all the display cells, and all the display cells become uniform. The next address period is composed of a first half for selecting lighted cells in odd-numbered display lines among odd-numbered display lines and a second half for selecting lighted cells in even-numbered display lines among odd-numbered display lines. The In the first half, the voltage Vx is applied to the odd-numbered sustain electrodes, 0 V is applied to the even-numbered sustain electrodes and the scan electrodes, and −Vy1 is applied to the odd-numbered scan electrodes. A scan pulse of −Vy is sequentially applied, and an address pulse of voltage Va is applied to the address electrode of the display cell that is turned on in synchronization with the application of the scan pulse. An address discharge is generated between the odd-numbered scan electrode to which the scan pulse is applied and the address electrode to which the address pulse is applied, and in the vicinity of the odd-numbered sustain electrode and the odd-numbered scan electrode to which the voltage Vx is applied. Wall charges are formed. In this manner, the lighted cells in the odd display lines among the odd display lines are selected.

  In the second half, voltage Vx is applied to even-numbered sustain electrodes, 0V is applied to odd-numbered sustain electrodes and scan electrodes, and −Vy1 is applied to even-numbered scan electrodes, and even-numbered scan electrodes are applied to even-numbered scan electrodes. A scan pulse of −Vy is sequentially applied, and an address pulse of voltage Va is applied to the address electrode of the display cell that is turned on in synchronization with the application of the scan pulse. An address discharge is generated between the even-numbered scan electrode to which the scan pulse is applied and the address electrode to which the address pulse is applied, and in the vicinity of the even-numbered sustain electrode and the odd-numbered scan electrode to which the voltage Vx is applied. Wall charges are formed. In this way, the lighted cells in the even display lines among the odd display lines are selected.

  In the sustain period, in a state where the voltage Va is applied to the address electrodes, a sustain pulse having the same phase is applied to the odd-numbered scan electrodes and the even-numbered sustain electrodes, and a sustain pulse having a phase opposite to that is applied to the even-numbered scan electrodes. Applied to odd-numbered sustain electrodes. Accordingly, the sustain voltage Vs is alternately applied between the odd-numbered sustain electrodes and the scan electrodes and between the even-numbered sustain electrodes and the scan electrodes, and the display selected in the first half and the second half of the address period. Sustain discharge occurs in the cell and lights up.

  In the even field, the even-numbered display lines are displayed by switching the voltage waveform applied to the odd-numbered sustain electrodes and the voltage waveform applied to the even-numbered sustain electrodes.

  The above configuration is the same as that of the conventional ALIS PDP apparatus described in Patent Document 1, and further description thereof is omitted. There are various modifications to the ALIS method, and the present invention is also applicable to these modifications.

  In the PDP device of the first embodiment, the configuration of the address driver 11, the odd Y scan driver 120, and the even Y scan driver 12E is different from the conventional one. Hereinafter, the configuration of these portions in the first embodiment will be described.

  FIG. 6 is a diagram showing a configuration of the drive IC 21 used to configure the odd-numbered Y scan driver 120 and the even-numbered Y scan driver 12E. Here, it is assumed that a 64-bit driving IC is used. As illustrated, the driving IC 21 includes a 64-bit shift register 22 that sequentially shifts the input data Din according to the clock CLK, and a 64-bit latch 23 that latches the output of the 64-bit shift register 22 according to the latch enable signal LE. , 64 output drivers 24-1 to 24-64 that output drive signals in response to 64 outputs of the 64-bit latch 23, and outputs and power supplies of 64 output drivers 24-1 to 24-64. Diodes D1-1 to D1-64 and D2-1 to D2-64 connected between terminals VH and VL are provided. The 64 output drivers 24-1 to 24-64 select and output each of the 64 outputs of the 64-bit latch 23 according to the output control signal OC, or the output is high impedance (Hi-Z). It becomes a state. Specifically, when used as a Y scan driver, the outputs of the output drivers 24-1 to 24-64 become Hi-Z during the sustain period, and the output drivers 24-1 to 24-64 to 64 during the address period. An output corresponding to each of the 64 outputs of the bit latch 23 is performed.

  In the sustain period, the GND and the sustain voltage Vs are alternately supplied to the power supply terminals VH1 to VH64 and VL1 to VL64, and the sustain pulse is applied to the scan electrodes through the diodes D1-1 to D1-64 and D2-1 to D2-64. Is applied. As a result, the diodes D1-1 to D1-64 and D2-1 to D2-64 generate heat. The amount of generated heat is related to the drive capacity and discharge current of the scan electrode. If it is large, there is a problem that the amount of heat generation increases accordingly. It is necessary to consider the heat radiation of the IC as a whole, and the problem is heat generation in the entire driving IC 21.

  FIG. 7 is a diagram showing the scan (Y) electrode and the IC output wiring in the first embodiment. As described above, the drive capacity of the scan electrode of the ALIS system plasma display panel (PDP) is large, and the drive IC 21 may have insufficient drive capability to drive one scan electrode with one output of the drive IC 21.

  In order to solve such a problem, in the first embodiment, two adjacent outputs of one drive IC 21 are connected to drive one scan electrode. If necessary, it is also possible to connect one or more outputs and drive one scanning electrode. Accordingly, here, 32 scan electrodes are driven by one 64-bit drive IC 21. As described above, since there are 384 scanning electrodes, 12 driving ICs 21 are used. Further, since it is an ALIS PDP device, it is necessary to drive odd-numbered scan electrodes and even-numbered scan electrodes independently, and odd-numbered scans that drive odd-numbered scan (Y) electrodes as shown in FIG. The driver 120 is divided into an even scan driver 12E that drives even scan (Y) electrodes. Therefore, the odd-numbered scan driver 120 and the even-numbered scan driver 12E are each composed of six drive ICs 21. Furthermore, the scan driver and the scan electrode of the PDP 10 are connected by thermocompression bonding using an anisotropic conductive film. From the viewpoint of the thermocompression bonding equipment conditions and connection performance, 384 wires are aggregated into two blocks and two bundles of output are made. Connect as a terminal group.

  As shown in FIG. 7, 192 first (192) scan (Y) electrodes are connected to the first scan driver circuit via the output terminal group C1, and 192nd to 384th 192 scans ( Y) The electrode is connected to the second scan driver circuit via the output terminal group C2. The first scan driver circuit has six drive ICs 21-O1 to 21-O3 and 21-E1 to 21-E3. The output of the first odd-number drive IC 21-1 is obtained by combining two adjacent outputs. The first even-numbered driving IC 21-E1 is connected to the odd-numbered electrodes Y1, Y3,... The 64th scan (Y) electrode from the 64th to the 64th scan (Y) electrodes are connected to the even-numbered electrodes Y2, Y4,..., Y64, and similarly, the second odd-numbered drive IC 21-2 and the third odd-numbered drive IC 21O3 are 65. Are connected to odd-numbered electrodes Y65, Y67,..., Y191 of the 128th to 192th scanning (Y) electrodes, and the second even-numbered driving IC 21-E2 and the third even-numbered driving IC 21-E3 are from the 65th. 192 1st 8 scanning (Y) even-numbered electrodes among the electrodes Y66, Y68, ..., connected to Y192.

  Further, the second scan driver circuit has six drive ICs 21-O4 to 21-O6 and 21-E4 to 21-E6. The fourth odd drive IC 21-O4 to the sixth odd drive IC 21-O6 are The adjacent outputs are connected to the odd-numbered electrodes Y193, Y195,..., Y383 of the 193rd to 384th 192 scan (Y) electrodes, and the fourth even-number drive IC 21-E4 to the sixth even-number drive. The IC 21 -E 6 connects the adjacent outputs to the even-numbered electrodes Y 194, Y 196,..., Y 384 of the 193 th to 384 th 192 scan (Y) electrodes.

  Further, as shown in FIG. 7, the carry output C of the first odd drive IC 21-O1 is connected to the input data Din of the second odd drive IC 21-O2, and the carry output C of the second odd drive IC 21-O2 is third. The carry output C of the preceding stage of the odd-numbered driving IC is inputted to the input data Din of the next odd-numbered stage so that the input data Din of the odd-numbered driving IC 21-O3 is connected. Similarly, the carry output C of the previous stage of the even-numbered driving IC is input to the input data Din of the next stage of the even-numbered driving IC.

  FIG. 8 is a diagram illustrating details of the connection state of the output unit of the drive IC. As shown in the figure, after connecting the outputs of the drivers 24-2n-1 and 24-2n of the driving IC, connecting to the nth scan (Y) electrode Yn, and connecting the outputs of 2n + 1 and 2n + 2, Connected to the (n + 1) th scanning (Y) electrode Yn + 1.

  FIG. 9 is a diagram showing a drive waveform of the drive IC 21 in the first embodiment. In the first embodiment, the adjacent outputs of the driving IC are combined to drive one scanning (Y) electrode, so that the two adjacent outputs of the driving IC are the same, and the position must be shifted by two outputs in order. is there. Therefore, the cycle of the clock CLK supplied to the driving IC is set to half the time obtained by dividing the address period by 384, that is, the cycle of the clock in the case of the conventional ALIS method. Then, after inputting the clear CLR to set all the values held in the shift register 22 to 0 (“L”), the input data Din is set to 1 (“H”) for 2 clocks CLK. The register 22 sequentially shifts the state where the outputs of two successive stages are 1. Therefore, the latch signal LE is generated every two clocks when the output which is 1 of the shift register 22 moves to the even stage. Thus, the latch circuit 23 outputs a state in which the adjacent odd-numbered and even-numbered outputs are 1 and the other outputs are 0, and shifts the position where the output is 1 for each latch signal LE by 2 outputs. In this way, a drive signal is obtained from the drive IC 21 where the adjacent odd-numbered and even-numbered outputs are 1 and the other outputs are 0, shifting by 2 outputs.

  In the first embodiment, not only the Y scan driver but also the address driver 11 drives one address electrode with two adjacent outputs. FIG. 10 is a diagram showing the configuration of the address driver 11 of the first embodiment. The address driver 11 is also composed of a driving IC, and here, it is assumed that a 64-bit driving IC is used. The drive IC of the address driver 11 has a configuration similar to that of the scan driver, and includes a 64-bit shift register 32, a 64-bit latch 33, and 64 output drivers 34-1 to 34-64. Diodes D1 and D2 are not provided.

  As described above, there are 1024 address electrodes, and each driver IC drives 32 address electrodes. Therefore, the address driver 11 includes 32 driver ICs 31-1 to 31-32. In the address driver 11, since it is necessary to prepare data for one display line during one scan pulse cycle, 32 bits of display data are supplied to 32 drive ICs 31-1 to 31-32, respectively. The drive ICs 31-1 to 31-32 are operated in parallel.

  FIG. 11 is a diagram showing drive waveforms of the address driver in the first embodiment. The difference from the operation of the conventional address driver is that input data is changed every two clocks CLK1. As a result, when the adjacent two bits are the same data and are shifted to 64 bits, that is, with 32 pieces of input data having 2 bits each, the latch signal LE is input and output. Thereby, one address electrode can be driven by two adjacent outputs.

  In the first embodiment, both the scan driver and the address driver drive one electrode with two outputs of the driving IC. However, considering the driving capability and heat generation of the driving IC, only one output has two outputs. It is also possible to drive one electrode with one and the other with one output to drive one electrode.

  Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is an embodiment in which the present invention is applied to the PDP apparatus having the conventional configuration described with reference to FIGS. The PDP 10 of the second embodiment has 768 scan (Y) electrodes, 768 sustain (X) electrodes, and 1024 address electrodes, and the Y scan driver 12 is configured by the drive IC of FIG. Then. The address driver 11 is the same as that of the conventional example or has the configuration described with reference to FIG.

  FIG. 12 is a diagram for explaining the wiring between the scan (Y) electrode and the output of the driving IC in the second embodiment. In the second embodiment, the outputs of two drive ICs are connected to drive one scan (Y) electrode. Therefore, in order to drive 768 scan (Y) electrodes using a 64-bit drive IC, it is necessary to use 24 drive ICs 21-1 to 21-24. As shown in FIG. 12, the first to 64th outputs of the first and second drive ICs 21-1 and 21-2 are combined and connected to the first to 64th scan (Y) electrodes. Similarly, the first to 64th outputs of the third and fourth drive ICs 21-3 and 21-4 are combined and connected to the 65th to 128th scan (Y) electrodes. And the outputs of the even-numbered drive ICs are sequentially connected to 64 scan (Y) electrodes. More specifically, the mth output of the (N−1) th and Nth (N ≦ 24) drive ICs is connected to the 32 (N−2) + mth scan (Y) electrode.

  Further, in the second embodiment, input data that becomes 1 (“H”) for one clock is input to the Din terminals of the first and second drive ICs 21-1 and 21-2, and the first or second input data is input. The carry C of the drive ICs 21-1, 21-2 is input to the Din terminals of the third and fourth drive ICs 21-3, 21-4, and so on, and the N-1th and Nth (N ≦ 24) The drive IC carry C is input to the Din terminals of the (N + 1) th and (N + 2) th drive ICs.

  In other words, in the second embodiment, 768 scanning electrodes are driven by 12 conventional 64-bit driving ICs, and 12 driving ICs are further provided in parallel to output the corresponding driving ICs. It is a connected configuration. Therefore, the driving waveform of the driving IC is the same as the conventional one.

  In the arrangement of the driving ICs in the second embodiment shown in FIG. 12, since all the driving ICs are provided on the same surface of the substrate, the wiring length is different, and the rise between the driving signals of the two driving Cs that connect the outputs. In addition, there is a possibility of causing a fall of the falling edge. When such a shift occurs, the switching transistor on the high potential side of one drive IC and the switching transistor on the low potential side of the other drive IC are simultaneously turned on, and a through current flows for a short time. there is a possibility.

  In order to make such a shift as small as possible, for example, as shown in FIG. 13, it is possible to provide two drive ICs for connecting outputs on the front surface and the back surface of the substrate 40. In this case, odd-numbered drive ICs 21-O (O is an odd number from 1 to 23) are provided on the surface of the substrate, and even-numbered drive ICs 21-E (E is an even number from 2 to 24) are provided on the back surface of the substrate. When a through hole (through hole) is provided in the substrate 40 and a corresponding output is connected, the wiring length from each IC can be made substantially the same, so that the above-described deviation can be reduced. In this case, it is necessary to make the outputs of the odd-numbered and even-numbered drive ICs symmetric.

  In the first and second embodiments, all the outputs of all the drive ICs are used. However, depending on factors such as the number of electrodes for each output terminal group, the number of outputs of the drive IC, the number of outputs to be connected, etc. Output may occur. For example, as in the first embodiment, in the ALIS method, the number of scanning (Y) electrodes is 384, and 192 are connected by two bundles of output terminal groups. When connecting outputs of different driving ICs, 64 odd-numbered scan (Y) electrodes are driven by two odd-numbered electrode drive ICs, and 64 even-numbered scans (two even-numbered electrode drive ICs ( Y) The electrode is driven, and the minimum unit of driving is 128 scanning (Y) electrodes. Therefore, when 192 scan electrodes are connected to a bundle of output terminal groups, 192 scan electrodes are driven using twice this minimum unit, that is, a total of 8 drive ICs. 128 drive IC outputs are not used.

  In this case, the first to 128th scan electrodes are driven by the first two odd-numbered electrode drive ICs and the two even-numbered electrode drive ICs, and the remaining 64 scans from the 129th to the 192nd. It can be considered that the electrodes are driven by two odd-numbered electrode driving ICs and two even-numbered electrode driving ICs in the latter half. The same applies to the portion connected to another bundle of output terminals. In this case, the 33rd to 64th outputs among the outputs of the latter two odd-numbered electrode drive ICs and the two even-numbered electrode drive ICs are not used. As the control sequence, if the first half address operation and the second half address operation described with reference to FIG. 5 are performed, a counter for counting clocks is provided, and the latter two odd electrode drive ICs or two even electrode drive ICs are provided. When the output up to the 32nd is completed, that is, when 96 clocks are counted, control is performed so as to start the operation of the drive IC that drives the scan electrodes connected to another bundle of output terminals.

  However, in this configuration, the four drive ICs that drive the 128th scan electrode from the first to the 128th generate a large amount of heat, and the four drive ICs that drive the 64th scan electrode from the 129th to the 192nd. The heat generation is relatively small. Since the operation of the entire circuit is limited by the IC with the maximum heat generation amount, it is not preferable that the heat generation amount is uneven. Therefore, it is desirable to distribute the unused output to each drive IC. The third embodiment is an embodiment that satisfies such a requirement.

  FIG. 14 is a diagram showing the connection between the scan (Y) electrode and the output of the driving IC in the PDP apparatus of the third embodiment of the present invention. The PDP apparatus of the third embodiment is an ALIS system, the number of scanning (Y) electrodes is 384, 192 are connected by two bundles of output terminal groups C1 and C2, and the Y scan driver has a 64-bit driving IC. Configure and use to connect the outputs of two different drive ICs. As shown in the figure, 16 drive ICs are used and divided into odd electrode drive ICs 21-O1 to 21-O8 and even electrode drive ICs 21-E1 to 21-E8. The first to 48th outputs of the first and second odd-numbered electrode driving ICs 21-O1 and 21-O2 are combined, and the odd-numbered scan electrodes Y1, Y3,. Connect to Y95. The first to 48th outputs of the first and second even electrode drive ICs 21-E1 and 21-E2 are combined, and the even-numbered scan electrodes Y2, Y4,. Connect to Y96. Similarly, the first to 48th outputs of each drive IC are combined and sequentially connected to 48 scan electrodes. As described above, in the third embodiment, the first to 48th outputs of all the driving ICs are used, and the 49th to 64th 16 outputs are not used.

  In order to control the driving ICs arranged as described above, three odd counters 51-O1 to 51-O3 that count 48 clocks are provided. These odd counters may be, for example, 48-bit shift registers. The input data ODin for one clock input to the first and second odd electrode driving ICs 21-O1 and 21-O2 is input to the first odd counter 51-O1, and 48 clocks are counted. During this period, the first and second odd-numbered electrode driver ICs 21-O1 and 21-O2 perform a shift operation up to 48 bits. When the first odd counter 51-O1 counts 48 clocks, the carry output of the counter is input to the third and fourth odd electrode driving ICs 21-O3 and 21-O4 and the second odd counter 51-O2. Thereby, the fourth and fourth odd-numbered electrode driver ICs 21-O3 and 21-O4 perform the shift operation, sequentially output the scan pulses, and the second odd-numbered counter 51-O2 counts 48 clocks. The first and second odd electrode drive ICs 21-O1 and 21-O2 perform the shift operation after performing the shift operation up to 48 bits, and output the scan pulse to the 49th and subsequent outputs. Since no output is connected anywhere, it does not become a driving load and heat generation can be almost ignored, so no problem occurs.

  As described above, the operation is continued until the scan pulse is output to the 48th output of the seventh and eighth odd electrode driving ICs 21-O7 and 21-O8.

  Similarly, three even counters 51-E1 to 51-E3 are provided, and the even electrode driving ICs 21-E1 to 21-E8 perform the same operation.

  As described above, in the third embodiment, outputs that are not used are generated, but since they are evenly distributed to all the drive ICs, it is possible to reduce the bias of heat generation in each drive IC.

  As described above, according to the present invention, a driver of a plasma display panel having a large driving capacity can be configured using an off-the-shelf driving IC, and the cost of the driver can be reduced and the time to commercialization can be shortened. Is possible. This facilitates commercialization of a PDP device having a larger plasma display panel.

It is a figure which shows the basic composition of a plasma display (PDP) apparatus. It is a figure which shows the drive waveform of a PDP apparatus. It is a figure which shows the structural example of the conventional drive circuit. It is a figure which shows schematic structure of the PDP apparatus of the ALIS system of 1st Example of this invention. It is a figure which shows the drive waveform of 1st Example. It is a figure which shows the structure of the drive IC used in 1st Example. It is a figure which shows the wiring of a scanning (Y) electrode and drive IC output in 1st Example. It is a figure which shows the connection state of the output part in 1st Example. It is a figure which shows the drive waveform of a scan driver. It is a figure which shows the structure of the address driver of 1st Example. It is a figure which shows the drive waveform of an address driver. It is a figure which shows the structure of the scan driver in 2nd Example of this invention. It is a figure which shows the modification of 2nd Example. It is a figure which shows the structure of the scan driver in 3rd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Plasma display panel 11 ... Address driver 12 ... Y scan driver 12O ... Odd Y scan driver 12E ... Even Y scan driver 13 ... Y sustain circuit 13O ... Odd Y sustain circuit 13E ... Even Y sustain circuit 14 ... X sustain circuit 14O ... Odd X sustain circuit 14E ... Even X sustain circuit 21 ... Drive IC

Claims (8)

A plasma display device comprising a plurality of electrodes and a drive circuit for driving the plurality of electrodes,
The driving circuit includes at least one driving IC having a plurality of outputs capable of independently outputting a plurality of driving signals, and drives one electrode by combining the plurality of driving signals of the driving IC. A plasma display device.   The plasma display apparatus of claim 1, wherein the electrode driven by combining the plurality of drive signals is a scan electrode to which a scan pulse is applied during an address operation of one of the sustain electrodes in which sustain discharge is performed.   The plasma display apparatus of claim 1, wherein the electrode driven by combining the plurality of driving signals is an address electrode to which an address pulse is applied during an address operation.   4. The plasma display device according to claim 1, wherein the plurality of drive signals for driving the one electrode are output from the same drive IC. 5.   4. The plasma display device according to claim 1, wherein the plurality of drive signals for driving the one electrode are output from different drive ICs. 5. The driving IC includes a shift register that sequentially shifts input data according to a clock, a latch circuit that latches and outputs an output of the shift register according to a latch signal, and a driving signal according to each output of the latch circuit With multiple drivers that output
5. The plasma display according to claim 4, wherein the input data is continuously input by the number of clocks corresponding to the number of drive signals to be combined, and the latch signal is generated for each clock corresponding to the number of drive signals to be combined. apparatus. The driving IC includes a shift register that sequentially shifts input data according to a clock, a latch circuit that latches and outputs an output of the shift register according to a latch signal, and a driving signal according to each output of the latch circuit With multiple drivers that output
5. The plasma according to claim 4, wherein the input data is continuously input by the number of clocks corresponding to the number of the drive signals to be combined, and the latch signal is generated when all the input data are arranged at the output of the shift register. Display device.   The plasma display apparatus is an ALIS system in which a plurality of common sustain electrodes and a plurality of scan electrodes are alternately arranged, and a display line is formed between all of the common sustain electrodes and the scan electrodes. The plasma display device according to any one of the above.

Images