JP2005018032A - Driver ic packaging module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver IC packaging module which constitutes a driving circuit of a display device using a flat plate type display panel and stabilizes display operation by suppressing the impedance of a line of the driving voltage system wiring within the module to a lower level. <P>SOLUTION: The driver IC chip packaging module is equipped with a driving power source system wiring section formed with driving power source system wiring which has a driver IC chip 9 for driving the display electrode of a flat plate type display panel and a wiring board for performing electrical connection to the driver IC chip and supplies a power source voltage inputted in at least the driver IC chip to drive the flat plate type display panel through the driver IC chip, a control system wiring section formed with control system wiring which supplies various kinds of signals inputted to the driver IC chip to control the driver IC chip, and an output terminal wiring section formed with output terminal wiring which converts the array sequence of the output signals outputted from the driver IC chip to a different array sequence and connects the same to the display electrode of the flat plate type display panel. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a driver IC mounting module that constitutes a driving circuit for driving display electrodes of a flat panel display panel, that is, a display device using a flat display panel. The present invention provides a new driver IC (Integrated Circuit) mounting module structure capable of stably supplying such a large current to a display panel through which current flows.

  The driver IC mounting module having such a structure is typically a plasma display panel (Plasma Display Panel: Usually, the entire plasma display device including a plasma display panel and peripheral circuits is called a PDP) or EL (Electroluminescence). It is applied to a display device having a large-capacity flat display panel constituted by a set of display cells having capacitive load characteristics, such as a sense panel or a large LCD (Liquid Crystal Display) panel.

  Recent progress in the development of flat display panels is remarkable. Especially, the three-electrode surface discharge type AC plasma display panel (AC plasma display panel) has a large screen and easy color display. It is applied to various uses and is being put to practical use.

  The AC plasma display panel described above performs discharge display by alternately applying a voltage waveform to two sustain discharge electrodes to perform light emission display. One discharge (lighting) is completed in several μs after applying the pulse. Ions that are positive charges generated by the discharge are accumulated in the insulating layer on the electrode to which a negative voltage is applied, and similarly electrons that are negative charges are on the electrode to which a positive voltage is applied. Accumulated in the insulating layer.

  Therefore, when wall charges are generated by first discharging with a high voltage (write voltage) pulse (write pulse), and then applying a lower voltage pulse (sustain voltage pulse, that is, a sustain pulse) than the previous one with a different polarity. The previously accumulated wall charges are superposed, the voltage to the discharge space becomes large, and discharge is started beyond the threshold of the discharge voltage. In other words, a cell that has once written discharge and generated wall charges has a feature of sustaining discharge by alternately applying a sustain voltage pulse with a reverse polarity. This is called a memory effect or memory drive. The AC type plasma display panel realizes display using this memory effect.

  AC plasma display panels include a two-electrode type in which selective discharge (address discharge) and sustain discharge are performed with two electrodes, and a three-electrode type in which address discharge is performed using a third electrode. In a color plasma display panel that performs multi-gradation display, the phosphor in the cell is excited by ultraviolet rays generated by discharge, but this phosphor is very sensitive to the impact of positive ions that are simultaneously generated by discharge. There is a disadvantage of being weak. In the above two-electrode type, since the structure is such that ions directly hit the phosphor, the lifetime of the phosphor may be reduced. In order to avoid this, a color plasma display panel generally uses a three-electrode AC plasma display panel using surface discharge (usually called a surface discharge AC plasma display panel).

FIG. 22 is a plan view schematically showing the configuration of a general surface discharge AC plasma display panel, and FIG. 23 is a cross-sectional view schematically showing the configuration of a general surface discharge AC plasma display panel. However, FIG. 23 shows a schematic cross-sectional view in the horizontal direction of FIG.
As shown in FIGS. 22 and 23, a display panel 300 constituting a general surface discharge AC plasma display panel is composed of two glass substrates, a front glass substrate 310 and a rear glass substrate 320, and the front glass. The substrate 310 includes sustain electrodes (X1, X2,... Xj... Xn, n are arbitrary positive integers) composed of bus electrodes and transparent electrodes, and scanning electrodes (Y1, Y2,... Yj... Yn). Is arranged.

  Further, on the rear glass substrate 320, address electrodes (A1, A2, Ai..., Am: i, m are arbitrary positive integers) are arranged so as to be orthogonal to the sustain electrodes, and these three kinds of electrodes Is a region (Y1-X1, Y2-X2,...) Between a plurality of scan electrodes and sustain electrodes sandwiched by the same number of scan electrodes and sustain electrodes. It is formed by the area | region which cross | intersects. The sustain electrodes (Xj), the scan electrodes (Yj), and the address electrodes (for example, Ai-1, Ai, and Ai + 1) are covered with a dielectric layer 350 for retaining wall charges. Further, on the dielectric layer on the address electrode side, a partition wall 330 for separating display cells from each other is formed, and a phosphor 360 that emits light by ultraviolet rays generated by discharge is formed.

FIG. 24 is a block diagram showing a main part of a driving circuit for the surface discharge AC plasma display panel as shown in FIGS.
As shown in FIG. 24, the surface discharge AC plasma display panel driving apparatus for operating the display panel 300 has interface signals (for example, a clock signal CLK, a data signal DATA, a vertical synchronization signal VSYNC, and a horizontal signal) input from the outside. A control circuit 370 for forming a control signal for controlling the driving circuit of the surface discharge AC plasma display panel by the synchronization signal HSYNC), a sustain electrode driving circuit for driving the display electrode of the display panel by this control signal, and scanning An electrode drive circuit and an address electrode drive circuit are provided. These sustain electrode drive circuit, scan electrode drive circuit, and address electrode drive circuit constitute the main part of the drive circuit for the surface discharge AC plasma display panel.

  Here, the sustain electrode driving circuit has an X common driver 390 for generating a sustain voltage pulse, and the scan electrode driving circuit similarly includes a Y common driver 391 for generating a sustain voltage pulse, and A scanning circuit 392 for driving and scanning the scanning electrodes independently is provided. On the other hand, the address electrode drive circuit includes an address circuit 380 for applying an address voltage pulse corresponding to display data to each address electrode. A data signal DATA indicating display data to be displayed on the display panel is temporarily held by the frame memory 372 of the display data control unit 371 in the control circuit in synchronization with the clock signal CLK, and then supplied to the address circuit 380. The Further, the scanning circuit 392 is controlled by the scanning driver control unit 373 in the control circuit based on the vertical synchronization signal VSYNC. Furthermore, the X common driver 390 and the Y common driver 391 are controlled by the common driver control unit 374 in the control circuit based on the horizontal synchronization signal HSYNC.

  FIG. 25 is a timing chart for explaining the operation of the drive circuit of FIG. This timing chart shows the drive voltage waveform for performing image display on the display panel as the operation of the drive circuit of FIG. 24 by the essence of the voltage application waveform to each electrode. It consists of a full erase period, an address discharge period and a sustain discharge period.

Among them, the driving period directly related to the image display is an address discharge period and a sustain discharge period, and a pixel to be displayed in the address discharge period is selected and light is emitted from the selected pixel in the next sustain discharge period. Display at a predetermined brightness.
In the address discharge period, a voltage of −Vmy, which is an intermediate potential, is applied simultaneously to the scan electrodes (Y1 to Yn), and then sequentially switched to a scan voltage pulse (scan pulse) of voltage level −Vy. The same scanning voltage pulse is applied, but by applying an address voltage pulse of voltage level Va to each address electrode (A1 to Am) in synchronization with the application of the scanning voltage pulse to each scanning electrode. Then, pixel selection on each scanning line is performed.

  In the next sustain period, the sustain voltage pulse of the common voltage level + Vs is alternately applied to all the scan electrodes (Y1 to Yn) and the X electrodes (X1 to Xn) to thereby select the previously selected pixel. Is caused to emit light, and display with a predetermined luminance is performed by this continuous application. Further, by controlling the number of times of light emission by combining the basic operations of such a series of drive voltage waveforms, it is also possible to perform grayscale display.

The entire writing period is for activating each display cell by applying a writing voltage pulse of the voltage level Vwx to all the display cells on the entire surface of the panel, and maintaining a uniform display characteristic. Is inserted.
Also, during the entire surface erasing period, a blunt wave having a peak voltage level Vey is applied as an erasing voltage pulse to all display cells on the entire surface of the panel before starting a new address discharge operation and sustain discharge operation for image display. By doing so, the previous display contents are erased.

  26 is a plan view showing a connection structure between the driver IC mounting module on the scanning electrode side and the panel electrode in FIG. 24, FIG. 27 is a block diagram showing a circuit configuration of the driver IC mounting module in FIG. 26, and FIG. FIG. 27 is a circuit diagram showing a circuit configuration of each driver IC chip in the driver IC mounting module of FIG. 26; 26 to 28 show the state of connection to the display panel with respect to the driver IC mounting module on the scanning electrode side of the surface discharge type AC plasma display panel having three electrodes as described above, and the driver IC mounting module. A specific circuit configuration is shown.

  The driver IC mounting module on the scan electrode side shown in FIG. 26 and FIG. 27 is a configuration example when the number of scan electrodes of the display panel 300 is 480 (Y1 to Y480), and the driver connected to these scan electrodes Since each IC chip 400 normally has a 64-bit output, a total of eight driver IC chips are used. In an embodiment of the present invention to be described later, these driver IC chips are divided and mounted on two driver IC mounting modules 401 and 402, and each driver IC mounting module includes four driver ICs composed of M1 to M4. A chip is mounted. Input connectors 461 and 462 are respectively provided in the input portions of these driver IC mounting modules, and output terminal portions 471 and 472 for connecting to the scanning electrodes are provided in the output portions thereof.

FIG. 28 shows a specific circuit inside each driver IC chip, and this circuit includes an output circuit unit that outputs scan electrode drive signals OUT1 to OUT64 for 64 bits.
These output circuit sections include push-pull type P-channel field effect transistors (hereinafter abbreviated as P-channel type FETs) 406-1 to 406-64 and N-channel type field effect transistors (hereinafter referred to as N-types) in the final output stage. A high-voltage power supply wiring VH for supplying a high-voltage power supply voltage and a ground wiring GND for supplying a ground potential are connected across a 407-1 to 407-64 (abbreviated as a channel FET). Furthermore, diodes 408-1 to 408-64 are connected in reverse polarity between the sources and drains of the P-channel FETs 406-1 to 406-64, respectively. The cathodes of these diodes 408-1 to 408-64 are all connected to the high voltage power supply wiring VH, and operate so that the drive current is absorbed by the high voltage power supply wiring. On the other hand, diodes 409-1 to 409-64 are connected in reverse polarity between the drain and source of the N-channel FETs 407-1 to 407-64, respectively. The anodes of these diodes 409-1 to 409-64 are all connected to the ground wiring GND, and operate so that the drive current flows from the ground wiring to the output side.

  Further, the circuit inside the driver IC chip of FIG. 28 includes a logic circuit for controlling the push-pull type P-channel FET and N-channel FET. This logic circuit is an N-channel type for controlling on / off operations of P-channel FETs 406-1 to 406-64 via a pair of resistors R1-1 to R1-64 and R2-1 to R2-64, respectively. The FETs 405-1 to 405-64, the inverters 404-1 to 404-64 for controlling the on / off operations of the N-channel FETs 407-1 to 407-64, respectively, and the N channel based on the strobe signal STB. Type FETs 405-1 to 405-64 and NAND gates 403-1 to 403-64 for inputting control signals to inverters 404-1 to 404-64, respectively, and are operated by a low voltage power supply VCC for logic. .

  Further, the circuit inside the driver IC chip in FIG. 28 temporarily holds a 64-bit shift register 411 for selecting a 64-bit output circuit section and a control signal output from the 64-bit shift register. And a latch circuit 412 for sending out to gates 403-1 to 403-64. The control signal includes a clock signal CLK and a data signal DATA input to the 64-bit shift register 411, a latch signal LATCH input to the 64-bit latch circuit 412, a strobe signal STB for controlling the logic circuit, and the like. The

FIG. 29 is a cross-sectional view showing a structure of a first example of a conventional driver IC mounting module. The driver IC mounting module having such a configuration is generally called a COB (Chip on Board) structure.
In the driver IC mounting module shown in FIG. 29, the driver IC chip 400 is mounted on a rigid type printed circuit board 430 having rigidity. Further, the driver IC mounting module includes a pad terminal 410 on the driver IC chip, a connection terminal connected to the input signal line and the power supply line wiring pattern 440 formed on each layer of the multilayer wiring type printed circuit board 430. They are connected by wire bonding. Further, an input connector 461 (or 462) is provided in the input portion of the driver IC mounting module. The input connector 461 is an input terminal formed on the upper layer of the multilayer wiring type printed circuit board 430. In addition to being connected to the wiring pattern 445, it is connected to the input signal line and the power supply line wiring pattern 440 on the other layers of the printed circuit board 430 through the through hole 446 for conduction.

  Further, the high voltage power supply voltage, the low voltage power supply voltage, the ground potential and various signals are transmitted from the input connector 461 and the input signal line and power supply line wiring pattern 440 to the driver IC chip 400 through the corresponding pad terminals 410 on the driver IC chip. Supplied. On the other hand, an output terminal connection pattern 450 formed on the upper layer of the printed circuit board 430 is provided in the output portion of the driver IC mounting module. The output terminal connection pattern 450 functions as a connection terminal 420, and a wire is provided between the connection terminal 420 (that is, the output terminal connection pattern 450) and the pad terminal 410 that outputs a drive signal from the driver IC chip 400. Connected directly by bonding.

  Further, the output terminal connection pattern 450 is drawn to the end face side of the printed circuit board 430 to form an output terminal connection portion. A driver IC mounting module is formed by connecting a flexible flexible wiring board 480 provided with an output terminal wiring pattern 490 having the same shape as the output terminal connecting portion to the output terminal connecting portion by thermocompression bonding. The A terminal for connecting to the display electrode of the display panel is provided at the tip of the flexible wiring board 480, and an output terminal portion 471 (or 472) including these terminals is thermocompression bonded to the display electrode. It is connected and used by the method of.

FIG. 30 is a cross-sectional view showing a structure of a second example of a conventional driver IC mounting module. The driver IC mounting module having such a configuration is generally called a COM (Chip on Multiple Board) structure.
The driver IC mounting module shown in FIG. 30 constitutes the entire board as a composite board 500 in which a rigid type printed board 510 serving as a base and a flexible wiring board 530 on which an output terminal wiring pattern 540 is formed are bonded together. Is.

  Further, in the driver IC mounting module of FIG. 30, the driver IC chip 400 is mounted on a rigid-type printed circuit board 510 having rigidity. Further, the driver IC mounting module includes a pad terminal 410 on the driver IC chip, connection terminals connected to input signal lines and power supply line wiring patterns 520 formed on each layer of the multilayer wiring type printed circuit board 510, and They are connected by wire bonding. Further, an input connector 460 is provided in the input portion of the driver IC mounting module. The input connector 460 is connected to an input terminal wiring pattern 515 formed on the upper layer of the multilayer wiring type printed circuit board 510. In addition to being connected, it is connected to the input signal line and the power line wiring pattern 520 of the other layer of the printed circuit board 510 through the conduction through hole 516.

  Further, the high voltage power supply voltage, the low voltage power supply voltage, the ground potential, and various signals are transmitted from the input connector 460 and the input signal line and power supply line wiring pattern 520 to the driver IC chip 400 through the corresponding pad terminals 410 on the driver IC chip. Supplied. On the other hand, an output terminal wiring pattern 540 formed on the upper layer of the flexible wiring board 530 in the composite substrate is provided at the output portion of the driver IC mounting module. The output terminal wiring pattern 540 functions as a connection terminal 420, and a wire is provided between the connection terminal 420 (that is, the output terminal wiring pattern 540) and the pad terminal 410 that outputs a drive signal from the driver IC chip 400. Connected directly by bonding.

Furthermore, terminals for connecting to the display electrodes of the display panel are provided at the tips of the output terminal wiring patterns 540, and these terminals are connected to the display electrodes by a technique such as thermocompression bonding. used.
In both modules shown in FIGS. 29 and 30, a predetermined insulating coating (for example, a resist film or a coverlay film) is applied to portions other than the terminal portions and IC mounting portions on the surface of each wiring board. Although it is normal, it is omitted in FIGS.

  As shown in FIG. 22 and FIG. 23, the structure inside the display panel of a general AC plasma display panel including a three-electrode surface discharge AC plasma display panel is that all display electrodes are insulating layers (dielectric layers). Since a display cell is formed by sandwiching a discharge gas in the gap, the display electrode exhibits capacitive load characteristics when viewed from a drive circuit for driving these electrodes. . For example, in the surface discharge type AC plasma display panel shown in FIG. 23, the inter-address electrode capacitance Ca and the counter electrode capacitance Cg exist in addition to the sustain electrode-scan electrode capacitance Cs.

FIG. 31 is a timing chart showing the relationship between scan electrode drive voltage and drive current in a general surface discharge AC plasma display panel.
The timing chart shown in FIG. 31 shows how the drive current flowing in the scan electrode changes when a sustain voltage pulse is specifically applied between the scan electrode and the sustain electrode of the surface discharge AC plasma display panel. The charge current and gas discharge current to the cell capacity (that is, the capacity Cs between the sustain electrode and the scan electrode and the capacity Cg between the counter electrodes) flow in a peak shape in synchronization with the rise of the sustain voltage pulse, and synchronize with the fall of the pulse. The discharge current from the cell capacity flows in a peak shape. It should be noted that most of the above-described cell capacitance contributes to the sustain electrode / scan electrode capacitance Cs.

  The peak current values of these drive currents vary depending on the size of the display panel and the structure of the display cell. However, in the case of the 42-inch class, the value is generally 0.2 A to 0.4 A per sustain electrode. For a single driver IC chip on the scan electrode side having 64 outputs, the peak current is about 25 A at maximum. Therefore, in one driver IC mounting module shown in FIG. 26, a peak current exceeding 90 A at the maximum flows.

Therefore, it is necessary for the drive circuit to be configured so that the above-described peak current can be stably supplied. First, a sustainer circuit composed of an X common driver and a Y common driver has a drive corresponding to the above peak current. It is necessary to use a device for the operation.
Of particular importance is the configuration of the drive wiring system such as the high-voltage power supply wiring and the ground wiring from the sustainer circuit to the display panel. The wiring length of the drive wiring system should be as short as possible and sufficient wiring can be provided. It is necessary to secure the width and area to form a low impedance line.

  If the impedance of these drive wiring systems cannot be reduced, even if the sustainer circuit itself has sufficient drive capability, a peak current of the required magnitude will be caused by a decrease in drive voltage due to the impedance of the drive wiring system. Not enough supply. As a result, the light emission luminance of the discharge is reduced or the luminance variation occurs, so that the display quality of the plasma display panel is deteriorated, and it is difficult to ensure a sufficient drive voltage margin. Defect) occurs and normal display operation is not performed.

  The number of display cells to be lit among a plurality of display cells provided in each scanning line (display line) of the display panel is determined according to display data. Is different. That is, the load on the drive circuit changes for each scan line. Therefore, when the impedance of the drive wiring system is high, there is a difference in the voltage drop value of the drive voltage supplied to the display panel for each display line. As a result, a portion of the display line where a drive voltage having a required magnitude is not sufficiently supplied occurs, resulting in variations in luminance on the display panel. On the other hand, when the drive voltage is increased in consideration of the decrease in the drive voltage due to the impedance of the drive wiring system, there is a risk that light will be emitted even to a display cell that is not selected, and normal display operation will not be performed.

  On the other hand, especially when the impedance of the ground wiring (earth line) becomes high, the flow of high-frequency peak current acts as noise on the entire drive circuit, and the drive circuit itself and other circuits malfunction. Not only does it cause normal operation to occur, but it also causes problems such as radiating electromagnetic waves to the surrounding environment and adversely affecting them.

A particularly problematic part in such a drive wiring system is a part of the driver IC mounting module that is directly connected to the display electrode of the display panel and drives the display electrode. It is important to reduce the impedance of the line.
However, the first example of the conventional driver IC mounting module as shown in FIG. 29 has a clock signal and a latch via a wiring pattern such as an input terminal wiring pattern 445 formed on a printed circuit board of a limited size. Since various signals such as signals and strobe signals are supplied from the input connector 461 to the driver IC chip, it is necessary to perform multi-layer wiring using a large number of through holes on the printed circuit board. It becomes. That is, since the input-related wiring system as described above uses a plurality of through holes for conduction, the wiring system is wired in a crossing manner with drive wiring systems such as high-voltage power supply wiring and ground wiring. Further, in the output-related wiring system of the driver IC mounting module, the output pad terminal 410 of the driver IC chip is connected to the output terminal portion via the output terminal connection pattern 450 on the printed board. For this reason, since the width and area of the drive wiring system are restricted by the conductive through-holes and the output terminal connection pattern, it is difficult to realize a sufficiently low impedance for the drive wiring system.

  On the other hand, the second example of the conventional driver IC mounting module as shown in FIG. 30 includes a flexible wiring board 530 on which an output terminal wiring pattern 540 of an output-related wiring system is formed, and a printed circuit board 500. The output pad terminal of the driver IC chip 400 is directly connected to the output terminal wiring pattern by wire bonding. For this reason, since the output-related wiring system does not affect the drive wiring system, the width and area of the drive wiring system can be made slightly larger than in the case of the first example. However, the input-related wiring system in the driver IC mounting module of the second example is wired in a crossing manner with the driving wiring system such as the high-voltage power supply wiring and the ground wiring, as in the case of the first example. become. For this reason, the width and area of the drive wiring system are still limited by the amount of the conductive through hole.

  As a prior art related to a conventional driver IC mounting module, as shown in JP-A-10-215038, a flexible circuit board having a wiring pattern for display driving is provided. There is disclosed a configuration of a composite circuit board that constitutes a composite driver capable of mounting an IC in which a power bus bar and a ground bus bar (earth bus bar) are integrally joined to a part or the back surface. In this composite circuit board, the drive wiring system including the power supply bus bar and the ground bus bar seems to be separated from the input-related wiring system and the output-related wiring system shown in the present invention. However, in this case, the wiring of the driving wiring system including the power bus bar and the ground bus bar is connected to the display driving IC once through the wiring pattern in the flexible circuit board. The system and the wiring system related to output are restricted.

Further, as another prior art related to a conventional driver IC mounting module, as shown in Japanese Patent Laid-Open No. 5-198603 (registered as Japanese Patent No. 2803699 on July 17, 1998), an IC chip is mounted. A first substrate and a second substrate made of a flexible substrate are provided. A drive wiring system such as a high-voltage power supply wiring and a ground wiring is formed on the first substrate, and an output-related wiring system is formed on the second substrate. An IC chip mounting structure is disclosed. In this mounting structure, it is considered that the input-related wiring system is also formed on the first substrate, so that the input-related wiring system is the same as the driving wiring system as in the conventional example of FIGS. 29 and 30 described above. Wiring will be crossed. For this reason, the width and area of the drive wiring system are still limited.
Patent documents that are prior arts related to the conventional driver IC mounting module as described above are summarized below.

JP-A-10-215038 Japanese Patent Laid-Open No. 5-198603

  The present invention has been made in view of the above-mentioned problems, and by reducing the impedance of the line of the drive wiring system of the driver IC mounting module applied to the flat panel display panel or the like as much as possible, the drive wiring system has a low impedance. It is an object of the present invention to provide a driver IC mounting module capable of easily realizing the above.

  In order to solve the above problems, a driver IC mounting module of the present invention includes a driver IC chip for driving display electrodes of a flat panel display panel, and a wiring board for electrical connection with the driver IC chip. And at least a first wiring portion formed with a drive power supply system wiring that supplies a power supply voltage that is input to the driver IC chip and drives the flat panel display panel via the driver IC chip. A second wiring portion formed with a control system wiring for supplying various signals to be input to the driver IC chip and controlling the driver IC chip; and the flat panel display panel derived from the driver IC chip And a third wiring portion on which output terminal wiring for connecting to the display electrode is formed.

Preferably, in the driver IC mounting module of the present invention, the drive power supply system wiring is formed as a solid wiring pattern in the first wiring portion, and the power supply voltage is directly applied to the driver IC chip from the solid wiring pattern. Configured to supply.
On the other hand, a driver IC mounting module according to an embodiment of the present invention includes a driver IC chip for driving display electrodes of a flat panel display panel, and a wiring board for electrical connection with the driver IC chip. Drive power supply wiring for supplying a power supply voltage for driving the flat panel display panel via the driver IC chip, and input to the driver IC chip. The fourth wiring part in which the control system wiring for supplying various signals for controlling the driver IC chip is formed, and the arrangement order of the output signals output from the driver IC chip is converted to a different arrangement order. And a fifth wiring portion on which output terminal wiring for connecting to the display electrode of the flat panel display panel is formed.

Preferably, in the driver IC mounting module according to one embodiment of the present invention, the drive power supply system wiring is formed as a solid wiring pattern in the fourth wiring portion, and from the solid wiring pattern to the driver IC chip, The power supply voltage is directly supplied.
Preferably, in the driver IC mounting module according to an embodiment of the present invention, the drive power supply system wiring formed in the fourth wiring portion is provided as the first sub wiring portion, and the fourth wiring portion is provided with the driving power supply system wiring. The control system wiring thus formed is provided as a second sub-wiring portion.

  Further preferably, the driver IC mounting module according to one embodiment of the present invention includes an odd number circuit driver IC group connected to the odd numbered output terminal wiring and an even number connected to the even numbered output terminal wiring. Circuit driver IC group, driving power supply wiring for driving the flat panel display panel via the odd circuit driver IC group, and the driver input to the odd circuit driver IC group The flat panel display panel is driven via a fourth wiring section for odd circuits on which control system wiring for supplying various signals for controlling the IC chip is formed and the driver IC group for even circuits. Drive power supply wiring, and control system wiring for supplying various signals for controlling the driver IC chip formed in the driver IC group for the even circuit are formed. A fourth wiring section for the even circuit, and the fifth wiring section leads the output signal of the odd circuit driver IC group to the odd-numbered corresponding output terminal wiring for the even circuit. A wiring layer for leading the output signal of the driver IC group to the even-numbered corresponding output terminal wiring is formed.

  On the other hand, a driver IC mounting module according to another embodiment of the present invention includes a driver IC chip for driving display electrodes of a plasma display panel, and a wiring board for electrical connection with the driver IC chip. And at least a first wiring portion formed with a drive power supply system wiring that is input to the driver IC chip and supplies a power supply voltage for driving the plasma display panel via the driver IC chip. A second wiring portion formed with a control system wiring that is input to the driver IC chip and supplies various signals for controlling the driver IC chip, and is derived from the driver IC chip and is connected to the plasma display panel. And a third wiring portion on which output terminal wiring for connecting to the display electrode is formed.

  On the other hand, a driver IC mounting module according to still another embodiment of the present invention includes a driver IC chip for driving display electrodes of a plasma display panel, and wiring for electrically connecting the driver IC chip. A power supply wiring for supplying a power supply voltage for driving the plasma display panel via the driver IC chip, and an input to the driver IC chip. The fourth wiring part in which the control system wiring for supplying various signals for controlling the driver IC chip is formed, and the arrangement order of the output signals output from the driver IC chip is converted to a different arrangement order. The output terminal wiring for connecting to the display electrode of the plasma display panel is formed And a fifth wiring portion.

  In the driver IC mounting module of the present invention, the driver IC chip includes a first wiring portion on which a driving voltage system wiring (that is, a driving wiring system) for supplying a power supply voltage for driving the flat panel display panel is formed, and a driver IC chip. A second wiring portion in which a control system wiring (that is, an input side wiring system) for supplying various signals for control is formed, and an output terminal wiring (that is, an output side wiring system) is formed. Therefore, the input wiring system is not crossed with the drive wiring system, and a sufficient wiring area can be secured for the drive wiring system of the driver IC mounting module. become able to. As a result, it is possible to realize a driver IC mounting module in which the impedance of the lines of the drive wiring system of the display panel is kept low.

Such a configuration of the driver IC mounting module of the present invention makes it possible to supply a sufficient peak current to the display panel, thereby obtaining sufficient luminance and stable display characteristics, and an operating margin. It is possible to ensure a normal display operation.
Furthermore, in the driver IC mounting module of the present invention, it is possible to realize a display device capable of suppressing the generation of noise during the operation of the flat panel display device and performing a stable control operation.

  Hereinafter, typical examples of the present invention will be described with reference to the accompanying drawings (FIGS. 1 to 21). These embodiments are preferably applied to a driving circuit for driving scanning electrodes of a surface discharge type AC plasma display panel having three electrodes.

FIG. 1 is a plan view showing the structure of a driver IC mounting module according to the first embodiment of the present invention, and FIG. 2 is a sectional view of the structure of the driver IC mounting module according to the first embodiment of the present invention. FIG.
The first embodiment shown in FIGS. 1 and 2 is an application example to a driver IC mounting module on the scanning electrode side of a driver IC mounting module such as a surface discharge type AC plasma display panel. The driver IC mounting modules are distributed and mounted. However, FIGS. 1 and 2 show the configuration of one of the driver IC mounting modules 9.

  The mounting board used for the driver IC mounting module 9 shown in FIGS. 1 and 2 is, roughly speaking, a base board 10 serving as a mother body, input control signal wiring for input and logic on the surface of the base board 10. The cross wiring board 20 including the cross wiring pattern 21 on which the power supply wiring is formed is bonded, and the flexible wiring board 30 on which the output terminal wiring pattern 31 for output is further bonded.

Here, four driver IC chips are used as the driver IC chip 4, and these four driver IC chips are used by being bonded and fixed to the surface of the base substrate 10.
An input connector 5 for connecting to an external board is installed in the input portion of the driver IC mounting module of the first embodiment, and the input control signal line and the input connector 5 are connected from the outside via the input connector 5. The logic power supply line is configured to be connected to the cross wiring pattern 21 of the cross wiring substrate 20. On the other hand, the high-voltage power supply line and the ground line that supply the high-voltage power supply voltage and the ground potential from the outside via the input connector 5 are connected to the high-voltage power supply pattern 12 and the ground pattern 11 of the base substrate 10, respectively. Configured.

  The cross wiring board 20 requires wiring including a cross wiring pattern 21 that crosses the four driver IC chips 4 so that the input control signal lines and the logic power supply lines are input in parallel to each other. Manufactured using printed circuit boards on both sides of wiring (or multilayer wiring). Preferably, a rigid type printed circuit board having rigidity is used as this type of printed circuit board. After the printed circuit board having such a structure is manufactured, the printed circuit board is bonded to a predetermined position on the surface of the base substrate 10 via the insulating plate 15. On the surface of the cross wiring substrate 20, each wiring is connected to the driver IC chip. In addition to the connection terminals for connecting, a connection terminal for connecting a bypass capacitor between the logic power supply line and the ground line is also provided. The cross wiring pattern 21 of the cross wiring substrate 20 corresponds to the second wiring portion 2 in which a control system wiring for controlling the driver IC chip is formed.

  Similarly, the base substrate 10 is manufactured using a rigid-type double-sided printed circuit board. On the front surface side on which the driver IC chip is mounted, a ground pattern 11 is formed as a solid ground wiring layer over almost the entire surface, and the back surface. On the side, a high-voltage power supply pattern 12 is formed as a solid high-voltage power supply wiring layer. However, a terminal 13 for connecting a high-voltage power supply wiring layer to the driver IC chip is provided around the driver IC chip on the surface side of the base substrate 10. In this case, the high-voltage power supply pattern 12 is connected to the pad terminal 40 of the driver IC chip through the conduction through hole 14 and the connection terminal 13. The ground pattern 11 and the high voltage power supply pattern 12 of the base substrate 10 correspond to the first wiring part 1 in which the drive power supply system wiring (that is, the drive wiring system including the high voltage power supply wiring and the ground wiring) is formed.

  The output flexible wiring board 30 is composed of a single-layer wiring board in which a copper foil is bonded onto an insulating film made of a flexible polyimide material or the like, and a plurality of output terminal wiring pattern wirings 31 from a driver IC chip are connected to each other. This is manufactured so as to be led out to the output terminal portion in parallel, and this is similarly bonded to a predetermined position on the surface of the base substrate 10 after manufacturing the single-layer wiring substrate. Also for these output terminal wiring patterns 31, a plurality of connection terminals 41 with the pad terminals 40 for output of the driver IC chip are provided. The output terminal wiring pattern 31 of the flexible wiring board 30 corresponds to a third wiring portion on which output terminal wiring is formed.

After bonding the above three types of substrates in a predetermined positional relationship, four driver IC chips are bonded and fixed to predetermined positions on the base substrate, and then each pad terminal of the driver IC chip and each corresponding substrate Electrical connection is made by connecting the connection terminals to each other by wire bonding.
After this electrical connection is completed, a sealing resin is applied to the area where the driver IC chip and the wire bonding are performed to protect it from moisture and the surrounding environment.

The connection between the input connector 5 and each substrate is performed by soldering between the connection pins of the input connector 5 and the terminals of the corresponding wiring layer, and the entire driver IC mounting module is completed through this soldering process. To do.
According to the first embodiment, the input control signal-related wiring system of the input part of the driver IC mounting module and the high-voltage power supply and GND-related drive wiring system are installed on separate wiring boards, respectively. Therefore, the wiring system related to the high-voltage power supply wiring and the ground wiring can be arbitrarily arranged without being affected by the wiring related to the input as in the conventional configuration, and a sufficient area can be secured to secure the wiring area. It becomes like this.

As a result, a driver IC mounting module that can keep the impedance of the line of the drive system wiring related to the high-voltage power supply wiring and the ground wiring sufficiently low is realized, and a stable display operation of the display panel is enabled.
FIG. 3 is a plan view showing the structure of the driver IC mounting module according to the second embodiment of the present invention. FIG. 4 is a cross-sectional view of the structure of the driver IC mounting module according to the second embodiment of the present invention. FIG. Hereinafter, the same components as those described above are denoted by the same reference numerals.

  In the second embodiment shown in FIGS. 3 and 4, the driver IC mounting module on the scanning electrode side of the driver IC mounting module such as a surface discharge type AC plasma display panel is the same as the case of the first embodiment described above. In this example, eight driver IC chips are distributed and mounted on two driver IC mounting modules. 3 and 4 also show the configuration of one of the driver IC mounting modules 9 among them.

The configuration of the base substrate 10 shown in FIGS. 3 and 4 is substantially the same as that of the first embodiment described above, and the description of the base substrate is omitted here.
The configuration of the second embodiment is greatly different from that of the first embodiment described above. The cross wiring board of the input part of the driver IC mounting module and the flexible wiring board of the output part are formed by the same board. It is a point that has been configured. That is, in the second embodiment, both the cross wiring board of the input unit and the flexible wiring board of the output unit are formed by a single common flexible wiring board 22.

  More specifically, a double-sided wiring board in which a double-sided wiring pattern (upper surface side wiring pattern 23 and lower surface side wiring pattern 24) is formed by bonding two layers of copper foil with an insulating film made of a polyimide material or the like interposed therebetween is used. In addition, a portion corresponding to the cross wiring board of the input unit in the first embodiment described above is formed, and a plurality of output terminal wiring patterns of the output unit are formed using one side of the double-sided wiring pattern. Is. In the second embodiment, the output terminal wiring pattern is formed on the copper foil portion (for example, the upper surface side wiring pattern 23) on the upper surface side in FIG. The upper surface side wiring pattern 23 and the lower surface side wiring pattern 24 formed on the common flexible wiring board 22 of the input part constitute the common cross wiring part 2c, and the upper surface side wiring pattern formed on the common flexible wiring board 22 of the output part. 23 constitutes an output terminal portion 3c.

In this way, the substrate of the driver IC mounting module is obtained by bonding the wiring pattern of the input portion and the output portion formed on one common flexible wiring substrate 22 to a predetermined position of the base substrate 10 via the insulating plate 15. Complete the production of the part.
Thereafter, the four driver IC chips are bonded and fixed at predetermined positions on the base substrate 10 and wire bonding is used between each pad terminal of the driver IC chip and each terminal of the base substrate 10 and the common flexible wiring substrate 22. Connecting. That is, the input control signal pad terminal and the logic power supply pad terminal of the driver IC chip are electrically connected by wire bonding to the corresponding terminals on the shared flexible substrate forming the cross wiring pattern. . On the other hand, the pad terminal for output of the driver IC chip is electrically connected by wire bonding with the corresponding terminal of the output terminal wiring pattern on the common flexible substrate. Further, the high voltage power supply pad terminal and the grounding pad terminal of the driver IC chip are electrically connected by wire bonding to the corresponding terminals on the base substrate.

Further, the driver IC chip and the region where the wire bonding is performed are sealed, and the input connector 5 is soldered to complete the assembly of the driver IC mounting module.
The feature of the second embodiment is that, unlike the first embodiment, the cross wiring pattern and the output terminal wiring pattern are formed by a single common flexible substrate, so that the overall configuration is simplified. Thus, the number of parts can be reduced and the number of handling steps can be reduced, and the cost of the entire driver IC mounting module can be reduced.

  The applicant of the present application has previously developed a driving method and a circuit method capable of adding a new display function to a conventional surface discharge type AC plasma display panel as disclosed in JP-A-9-160525. This driving method is an interlaced surface discharge AC plasma display panel driving method called an Alis (Alternate lighting of surfaces) driving method.

  This Alis drive system forms all the regions sandwiched between the sustain electrodes and scan electrodes of the display panel symmetrically as display cells, and enables a normal display operation for all these display cells by a new drive technology. Thus, high-definition display was realized by expanding the display capacity to twice that of a conventional surface discharge AC plasma display panel (see, for example, FIG. 22). The third to sixth embodiments to be described below provide a configuration of a driver IC mounting module for realizing the above driving method while keeping the impedance of the line of the driving wiring system at a sufficiently low value.

Here, before explaining the third to sixth embodiments, referring to FIGS. 5 to 12, a surface discharge AC plasma using the Aris driving system which is the premise of the third to sixth embodiments. A display panel driving device and a driving method thereof will be described.
FIG. 5 is a plan view showing a schematic configuration of an interlaced surface discharge AC plasma display panel.

  In the plasma display panel 100 shown in FIG. 5, pixels are indicated by dotted lines only for the display line (display row) L1. Here, in order to simplify the description, the number of pixels of the plasma display panel 100 is 6 × 8 = 48 in terms of monochrome pixels. The present invention can be applied to either color or monochrome, and one color pixel corresponds to three monochrome pixels.

  The plasma display panel 100 has a configuration in which row-direction barrier ribs are removed from a general plasma display panel in order to facilitate manufacture and reduce the pixel pitch for higher definition. In order to prevent erroneous discharge due to the influence between adjacent display lines by this removal, the voltage waveform of the sustain pulse (sustain voltage pulse) is different between the odd-numbered and even-numbered lines between the surface discharge electrodes L1 to L8 as described later. Interlace scanning is performed so that the phases are reversed.

FIG. 6 is a perspective view showing a state in which the interval between the color pixels 100a of the plasma display panel of FIG. 5 is widened, and FIG. 7 is a longitudinal section along the sustain electrode X1 of the color pixels 100a of the plasma display panel of FIG. FIG.
6 and 7, transparent electrodes 121 and 122 such as an ITO film are arranged in parallel on one surface of the glass substrate 110, and in order to reduce a voltage drop along the longitudinal direction of the transparent electrodes 121 and 122, Metal electrodes 131 and 132 such as copper (Cu) are formed along the center lines on the transparent electrodes 121 and 122, respectively. The transparent electrode 121 and the metal electrode 131 constitute the sustain electrode X1, and the transparent electrode 122 and the metal electrode 132 constitute the scan electrode Y1. On the glass substrate 110, the electrode X1, and the electrode Y1, a wall charge holding dielectric 140 is deposited, and an MgO protective film 150 is further deposited thereon.

  On the other hand, on the surface of the glass substrate 160 facing the MgO protective film 150, the address electrodes A 1, A 2 and A 3 and the partitions 171 to 173 partitioning them are arranged in a direction orthogonal to the sustain electrodes X 1 and the scan electrodes Y 1. Is formed. By these barrier ribs, discharge cells (usually simply called cells or slits) are formed in regions where the address electrodes, the sustain electrodes, and the scan electrodes intersect. Further, between the partition wall 171 and the partition wall 172, between the partition wall 172 and the partition wall 173, and between the partition wall 173 and the partition wall 174, a phosphor 181 that emits red light when ultraviolet light generated by discharge is incident. A phosphor 182 that emits green light and a phosphor 183 that emits blue light are attached. In the discharge space between the phosphors 181 to 183 and the MgO protective film 150, for example, Ne + Xe Penning mixed gas is enclosed.

The partition walls 171 to 174 prevent the ultraviolet rays generated by the discharge from entering the adjacent pixels, and function as spacers for forming a discharge space. If the phosphors 181 to 183 are made of the same material, the plasma display panel 100 is for monochrome display.
In a plasma display panel driving apparatus using a plasma display panel as shown in FIG. 5, a plurality of types of driving voltage pulses necessary for writing predetermined display data to selected cells are applied to sustain electrodes and scanning. A drive circuit for supplying electrodes and address electrodes and a control circuit for controlling the order of supplying these drive voltage pulses are provided. The drive circuit includes odd and even X sustain circuits (common drivers) that supply write pulses and sustain pulses to the sustain electrodes X1 to X5, and odd and even numbers that supply scan pulses and sustain pulses to the scan electrodes Y1 to Y4. A Y sustain circuit (common driver) and an address circuit for supplying an address voltage pulse or the like to the address electrodes A1 to A6 are included.

FIG. 8 is a diagram showing a configuration example of a frame for forming a color image of the plasma display panel of FIG. 5, and FIG. 9 is a diagram showing the order of display scanning in the address period of the frame of FIG.
The frame shown in FIG. 8 is divided into an odd field and an even field, and each field is composed of first to third subfields. For each subfield, in the odd field, a voltage having a waveform shown in FIG. 10 to be described later is supplied to each electrode of the plasma display panel 100 to display the display lines L1, L3, L5 and L7 in FIG. A voltage having a waveform shown in FIG. 11 to be described later is supplied to each electrode of the panel 100 to display the display lines L2, L4, L6 and L8 in FIG. The sustain discharge periods in the first to third subfields are T1, T2 and 4T1, respectively. In each subfield, the sustain discharge is performed a number of times proportional to the length of the period. As a result, the luminance becomes 8 gradations. Similarly, if the number of subfields is 8, and the ratio of the sustain discharge period is 1: 2: 4: 8: 16: 32: 64: 128, the luminance is 256 gradations.

The scanning of the display lines in the address period is performed in the order of numbers in the circles in the part (A) of FIG. That is, in the odd field, scanning is performed in the order of the display lines L1, L3, L5, and L7, and in the even field, scanning is performed in the order of the display lines L2, L4, L6, and L8.
FIG. 10 is an electrode applied voltage waveform diagram in an odd field showing a conventional plasma display panel driving method according to the first example, and FIG. 11 is an even field showing a plasma display panel driving method according to the conventional first example. It is an electrode applied voltage waveform diagram. Actually, as shown in FIG. 8, the odd field and the even field each have a plurality of subfields having different sustain discharge lengths, but only one subfield is shown here for the sake of simplicity. .

First, the operation in the odd field will be described with reference to FIG. W, E, A, and S in FIG. 10 indicate the time points at which full write discharge, full self erasure discharge, address discharge, and sustain discharge occur, respectively. Hereinafter, for simplification, they are generically named as follows.
Sustain electrode (ie, X electrode): Electrodes X1 to X5
Odd sustain electrodes: electrodes X1, X3 and X5
Even sustain electrodes: electrodes X2 and X4
Scan electrode (ie, Y electrode): electrodes Y1 to Y4
Odd scan electrodes: electrodes Y1 and Y3
Even scan electrodes: electrodes Y2 and Y4
Address electrode (ie, A electrode): Address electrodes A1 to A6
On the other hand,
Vfxy: discharge start voltage between adjacent sustain electrode and scan electrode Vfay: discharge start voltage between opposite address electrode and scan electrode Vwall: wall generated by discharge between adjacent sustain electrode and scan electrode Voltage between positive wall charge and negative wall charge due to charge (wall voltage)
And

Typically, Vfxy = 290V and Vfay = 180V. Further, the voltage between the address electrode and the sustain electrode is abbreviated as the voltage between the A and X electrodes, and the voltage between the address electrode and the scan electrode is abbreviated as the voltage between the A and Y electrodes. Is also abbreviated with the same symbol.
(1) Reset period In the reset period, the voltage waveforms supplied to the sustain electrodes are identical to each other by a full-face write pulse (usually simply referred to as a write pulse), and the voltage waveforms supplied to the scan electrodes are the same at 0V. The voltage waveforms supplied to the address electrodes are the same in the intermediate voltage pulse.

  Initially, the applied voltage of each electrode is 0V. Due to the last sustain pulse in the sustain discharge period before the reset period, positive wall charges are present on the sustain electrode side on the cells (pixels) that have been lit, that is, on the MgO protective film 150 of the display slit. Negative wall charges are present (ie, positive polarity wall charges remain). There is almost no wall charge on the cells that have been turned off, that is, on the sustain electrode side and the scan electrode side of the non-display slit.

  In a period of a ≦ t ≦ b, a reset discharge pulse (that is, a write pulse) having a voltage Vw is supplied to the sustain electrode, and an intermediate voltage pulse having a voltage Vaw is supplied to the address electrode. For example, Vw = 310 V, Vw> Vfxy, and the entire surface write discharge (lighted cell or non-charged) between the adjacent XY electrodes, that is, between the XY electrodes of the display lines L1 to L8 regardless of the presence or absence of wall charges. Regardless of the lighted cell, it is performed for all the cells, so it is also called all-cell write discharge.) W is generated, and the generated electrons and positive ions are attracted by the electric field due to the voltage Vw between the XY electrodes and have the opposite polarity Wall charges (that is, negative polarity wall charges) are generated, thereby reducing the electric field strength in the discharge space and terminating the discharge in 1 μs to several μs. The voltage Vaw is about Vw / 2, and when the reset discharge pulse is applied, the voltage between the A-X electrodes and the voltage between the A-Y electrodes are opposite to each other and are almost equal in absolute value. The average wall charge is almost zero (0).

  When the reset discharge pulse falls at t = b, that is, when the applied voltage having the opposite polarity to the wall voltage disappears, the wall voltage Vwall between the XY electrodes becomes larger than the discharge start voltage Vfxy, and the entire self-erase discharge (all cells E) (also called self-erasing discharge) occurs. At this time, since all of the sustain electrode, the scan electrode, and the address electrode are 0 V, ideally, the wall charge is hardly generated by the entire self-erase discharge, and the ions and electrons are recombined in the discharge space and almost all. Completely neutralized. However, in actuality, in this full-surface self-erasing discharge, all wall charges are not completely neutralized, and some negative wall charges remain in the cells.

(2) Address period In the address period, the voltage waveforms supplied to the odd sustain electrodes are the same, the voltage waveforms supplied to the even sustain electrodes are the same, and the voltage waveforms supplied to the non-selected scan electrodes Are identical to each other at the voltage −Vsc. The scan electrodes are selected in the order of Y1 to Y4, a scan pulse of voltage −Vy (that is, a scan pulse) is supplied to the selected scan electrode, and the non-selected scan electrode is set to voltage −Vsc. For example,
Vsc = Va = 50V, Vy = 150V
It is.

(C ≦ t ≦ d) A scan pulse of voltage −Vy is supplied to the scan electrode Y1, and an address voltage pulse of voltage Va is supplied to the address electrode for the cell to be lit. The relationship
Va + Vy> Vfay
Thus, address discharge is generated only for the cells to be lit, reverse wall charges are generated, and the discharge is terminated. During this address discharge, a pulse of voltage Vx is supplied only to electrode X1 among electrodes X1 and X2 adjacent to electrode Y1. When the discharge start voltage between the XY electrodes when triggered by this address discharge is Vxyt,
Vx + Vsc <Vxyt <Vx + Vy <Vfxy
Is established, writing discharge is generated between the X1-Y1 electrodes of the display line L1, wall charges having a reverse polarity to the extent that self-discharge is not generated are generated between the X1-Y1 electrodes, and the discharge is terminated. On the other hand, no discharge occurs between the X2 and Y1 electrodes of the display line L2.

  (D ≦ t ≦ e) A scan pulse of voltage −Vy is supplied to the electrode Y2, a pulse of voltage Vx is supplied to the even sustain electrode, and an address voltage pulse of voltage Va is applied to the address electrode. Similarly, writing discharge occurs between the X2 and Y2 electrodes of the display line L3, and reverse polarity wall charges are generated. On the other hand, no discharge occurs between the X3 and Y2 electrodes of the display line L4.

Thereafter, the same operation as described above is performed at e ≦ t ≦ g.
In this manner, display data write discharge occurs in the cells to be lit in the order of the display lines L1, L3, L5 and L7, and positive wall charges are generated on the scan electrode side, and on the sustain electrode side. Negative wall charges are generated. That is, a positive polarity wall charge is formed in the selected cell (display slit), but no wall charge is formed in the non-selected cell (non-display slit).

(3) Sustain Discharge Period In the sustain discharge period, sustain pulse trains of the same phase and the same voltage Vs are supplied to the odd sustain electrodes and the even scan electrodes, and the phase of these sustain pulse trains is 180 ° (1/2 cycle). ) A shifted series of sustain pulses is supplied to the even sustain electrodes and odd scan electrodes. On the other hand, in synchronization with the rising edge of the first sustain pulse, the voltage Ve is supplied to the address electrode and held until the sustain discharge period ends.

(H ≦ t ≦ p) A sustain pulse of voltage Vs is supplied to the odd-numbered scan electrodes and even-number sustain electrodes. The effective voltage of the cell between the odd-numbered Y and the odd-numbered X electrode is Vs + Vwall, the effective voltage of the cell between the even-numbered Y-even-numbered X electrode is Vs-Vwall, and between the odd-numbered X-even-numbered scan electrodes and The effective voltage of the cell is 2Vwall. The relationship
Vs <Vfxy <Vs + Vwall, 2Vwall <Vfxy
Is established, sustain discharge is generated between the odd-numbered Y and odd-numbered X electrodes, wall charges of opposite polarity are generated, and the discharge is terminated. No sustain discharge occurs between the other electrodes. Accordingly, only the odd display lines L1 and L5 in the odd field are displayed. A sustain discharge does not occur between the even-numbered Y and the even-numbered X electrodes only for the first time.

  (Q ≦ t ≦ r) A sustain pulse of voltage Vs is supplied to the odd sustain electrodes and the even scan electrodes. The effective voltage of the cell between the odd-numbered X and the odd-numbered Y electrode and between the even-numbered Y and the even-numbered X electrode is Vs + Vwall, and the effective voltage between the odd-numbered Y and the even-numbered X electrode and between the odd-numbered X and the even-numbered X-even Y electrode is zero. As a result, a sustain discharge is generated between the odd-numbered X and odd-numbered Y electrodes and between the even-numbered Y and even-numbered X electrodes, and wall charges with reverse polarity are generated to terminate the discharge. No sustain discharge occurs between the other electrodes. Therefore, the display of all odd display lines L1, L3, L5 and L7 in the odd field becomes effective at the same time.

Thereafter, the sustain discharge similar to the above case is repeated. In this case, as apparent from the wall charges shown in FIG. 10, the effective voltage of the cell between the odd-numbered Y-even-numbered X electrodes and between the odd-numbered X-even-numbered Y electrodes of the non-display line becomes zero. The last sustain discharge in the sustain discharge period is such that the polarity of the wall charges is in the initial state of the reset period.
Next, the operation in the even field will be described. In FIG. 11, in the odd field, the display of the display lines L1, L3, L5 and L7 of the pairs of the scan electrodes Y1 to Y4 and the sustain electrodes X1 to X4 adjacent on the upper side of FIG. In the even field, the display of the display lines L2, L4, L6, and L8 of the pair of the electrodes Y1 to Y4 and the electrodes X2 to X5 adjacent to the lower side of FIG. This may be achieved by reversing the roles of the electrode X1 and the electrode X2 with respect to the electrode Y1, reversing the roles of the electrode X2 and the electrode X3 with respect to the electrode Y2, and so on. That is, the voltage waveforms supplied to the grouped odd sustain electrodes and even sustain electrodes may be interchanged. FIG. 11 shows such an electrode applied voltage waveform in an even field.

  The operation in the even field is clear from the above description and FIG. 11. In general, the entire write discharge W and the entire self-erase discharge E are performed in the reset period, and the electrodes Y1 to Y4 are sequentially selected in the address period. Display data write discharge is performed in the order of the display lines L2, L4, L6, and L8, and the simultaneous sustain discharge in these display lines L2, L4, L6, and L8 is repeated in the sustain discharge period.

  Furthermore, in FIGS. 10 and 11, if the number of pulses can be reduced, power consumption can be reduced. If the pulses supplied to the odd sustain electrodes and the even sustain electrodes can be continued in the address period, the number of pulses can be reduced. In order to realize this, the scanning order may be as shown in part (B) of FIG. That is, the display lines L1, L3, L5, and L7 in the odd field are further divided into odd and even lines, one of which is sequentially scanned and the other is sequentially scanned. The same can be said for the even field.

FIG. 12 is a block diagram showing a schematic configuration of a driving apparatus for the surface discharge type AC plasma display panel of FIG.
In the plasma display panel driving apparatus 200 of FIG. 12, the control circuit 210 converts the data signal DATA supplied from the outside into data for the display panel 100 including the plasma display panel and supplies the data to the shift register 221 of the address circuit 220. To do. Further, the control circuit 210 generates a plurality of control signals based on the clock signal CLK, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC supplied from the outside, and supplies them to various drive circuits.

  In order to apply the drive voltage waveforms as shown in FIGS. 10 and 11 to the various electrodes, the voltages Vaw, Va and Ve are supplied from the power supply circuit 290 to the address circuit 220, and the odd-number Y common driver 240 and The voltages -Vsc, -Vy and Vs are supplied to each of the even Y common driver 250, and the voltages Vw, Vx and Vs are supplied to each of the odd X common driver 260 and the even X common driver 270.

The numerical values in the shift register 221 are for identifying elements having the same configuration, and for example, 221 (3) represents the third bit of the shift register 221. The same applies to other components.
In the address circuit 220, when display data for one row (one display line) is supplied from the control circuit 210 to the shift register 221 in the address period, bits 221 (1) to (6) are respectively stored in the latch circuit 222. The switch elements (not shown) in the address drivers 223 (1) to (6) are turned on / off according to the values held in the bits 222 (1) to (6), and the voltage Va or 0V is controlled. The binary voltage pattern is supplied to the address electrodes A1 to A6.

  The scanning circuit 230 includes a shift register 231 and a scanning driver 232. In the address period, “1” is supplied to the serial data input terminal of the shift register 231 only in the first address cycle of each cycle of the vertical synchronization signal VSYNC, and this is shifted in synchronization with the address cycle. The switch elements (not shown) in the scan drivers 232 (1) to (6) are turned on / off by the values of the bits 231 (1) to (4) of the shift register 231 to select the selection voltage −Vy or non- The selection voltage −Vsc is applied to the scan electrodes Y1 to Y4. That is, the scan electrodes Y1 to Y4 are sequentially selected by the shift of the shift register 231, the selection voltage -Vy is applied to the selected scan electrode Y, and the non-selection voltage -Vsc is applied to the non-selected scan electrode Y. These voltages −Vy and −Vsc are supplied from the odd-numbered Y common driver 240 and the even-numbered Y common driver 250. In the sustain discharge period, the first sustain pulse train is supplied from the odd-numbered Y common driver 240 to the odd-numbered scan electrodes Y1 and Y3 among the scan electrodes via the scan drivers 232 (1) and (3). A second sustain whose phase is shifted from the first sustain pulse train by 180 ° from the Y common driver 250 to the even-numbered scan electrodes Y2 and Y4 among the scan electrodes via the scan drivers 232 (2) and (4). A train of pulses is provided.

  In the sustain electrode X circuit, the second sustain pulse train is supplied from the odd-numbered X common driver 260 to the odd-numbered sustain electrodes X1, X3, and X5 among the sustain electrodes in the sustain discharge period. The first sustain pulse train is supplied from the driver 270 to the even-numbered sustain electrodes X2 and X4 among the sustain electrodes. In the reset period, the entire-surface write pulse is supplied from the odd X common driver 260 and the even X common driver 270 to the sustain electrodes X1 to X5 in common. In the address period, a pulse train of two address cycles is supplied from the odd X common driver 260 to the odd-numbered sustain electrodes X1, X3, and X5 among the sustain electrodes in correspondence with the scan pulse, and the phase of the pulse train is set to 180. The pulse train shifted by ° is supplied from the even-numbered X common driver 270 to the even-numbered sustain electrodes X2 and X4 among the sustain electrodes.

In other words, the circuits 223, 232, 240, 250, 260 and 270 are switching circuits for turning on / off the voltage supplied from the power supply circuit 290.
In order to realize the driving method of the interlaced surface discharge AC plasma display panel as described above, as described above, the sustain voltage pulse (sustain pulse) generating circuits on the scan electrode side and the sustain electrode side of the drive circuit are respectively provided. The circuit is separated into two circuits for the odd-numbered electrode side and the even-numbered electrode side, and the driver IC chip is similarly separated into the odd-numbered circuit driver IC group and the even-numbered circuit driver IC group according to this separated configuration. Make it. Then, after extracting the outputs from both the driver IC groups, a predetermined output terminal array is obtained by crossing the wirings and rearranging them at odd-numbered and even-numbered positions.

  In this case, in the configuration of the conventional driver IC mounting module, the cross wiring for rearranging the output terminal wiring pattern requires a multilayer wiring board, and therefore, the wiring board on which the driver IC chip is mounted (that is, the base board) However, in order to cross a large number of output terminal wirings, a huge wiring area is required and conductive through holes between different wiring layers are provided for at least half of the number of wirings. It is necessary to provide it.

As a result, it becomes difficult to secure a sufficient wiring area for the drive wiring system including the ground wiring layer and the high-voltage power wiring layer of the base substrate, and the above-described problems occur.
Therefore, the configurations of the driver IC mounting modules that have been devised to solve the above problems are the third to sixth embodiments.

FIG. 13 is a block diagram showing a circuit configuration of a driver IC mounting module according to the third embodiment of the present invention, and FIG. 14 is a plan view showing a structure of the driver IC mounting module according to the third embodiment of the present invention. FIG. 15 is a sectional view showing the structure of the driver IC mounting module according to the third embodiment of the present invention.
In the third embodiment of the present invention, as apparent from FIGS. 13 and 14, the driver IC mounting modules 25-1 and 25 on the two scan electrode sides are the same as in the first and second embodiments described above. 2 shows a configuration of one driver IC mounting module (9) in FIG.

  This driver IC mounting module uses four driver IC chips 4-1 to 4-4 (M1 to M4), and the odd-number circuit driver IC chips 4-1 and 4-2 are odd-numbered circuits. A driver IC group for odd circuits for driving the output terminal section of the even number, and driver IC chips 4-3 and 4-4 for even circuit for the even circuit for driving the even output terminal section for the even circuit. Separated and mounted as a driver IC group.

  The configuration of the mounting substrate of the third embodiment is roughly as follows. The base substrate 60 is a mother body, and the odd-numbered circuit driver IC group (M1, M2) and the even-numbered circuit driver IC are formed on the surface of the base substrate 60. A cross-wiring board 70 for rearranging the output arrangement of the group (M3, M4) is bonded to form a composite board, and the connection part of the input connector 5 of the input part and the output terminal row 71 of the output part are connected. It is provided.

  First, details of the base substrate 60 include signals (control signals and five logic power supplies) SG1 to SG4, high-voltage power supply wirings VH1 and VH2, and ground wiring necessary for operating the driver IC chips 4-1 to 4-4. GND1 and GND2 are applied, and a multilayer wiring board having 2 to 4 layers is used. The input signal line and the power line are connected to a predetermined wiring pattern (for example, the input signal line and the power line wiring pattern 61) through the input connector 5 of the input unit, and are formed on the surface of the substrate by the multilayer wiring having the conduction through hole 62. A connection terminal with the driver IC chip is formed by being drawn out to the periphery of the IC chip mounting portion. The input signal line and power line wiring pattern 61 formed on the base substrate 60 correspond to the fourth wiring portion 6 of the present invention.

Further, the cross wiring board 70 is a two-layer wiring board, and is provided with a connection terminal 41 and a cross wiring pattern 72 for the pad terminal 40 for output of the driver IC chip in the vicinity of the end face close to the driver IC chip on the surface. The output terminal row 71 is provided on the end surface side opposite to the driver IC chip.
The wiring structure of the cross wiring pattern 72 is such that the output terminal wiring from the odd-numbered circuit driver IC chip is extended as it is using the surface and led out as an odd-numbered terminal of the output terminal part, while from the even-numbered circuit driver IC chip. The output terminal wiring is led to the back surface side through the conduction through hole, and is pulled up from the back surface side before the output terminal portion to the front surface side through the conduction through hole, and is derived as an even terminal of the output terminal portion. The cross wiring pattern 72 and the output terminal row 71 formed on the cross wiring substrate 70 correspond to the fifth wiring portion 7 of the present invention.

The cross wiring substrate 70 as described above is laminated on the base substrate 60, but the cross wiring substrate 70 is bonded via an insulating material or an insulating plate 63 in order to insulate the substrates.
The driver IC chip and the board are electrically connected by mounting and fixing the driver IC chip on the die bonding pad on the base board, and then the input terminals of the driver IC chip, the power-related pad terminals, and the corresponding terminals on the base board. Are connected by wire bonding, and the pad terminals for output of the driver IC chip and the corresponding output terminal portions of the cross wiring board 70 are connected by wire bonding.

After the connection by the wire bonding, the driver IC chip itself, the wires and the connection terminals are sealed with resin to provide moisture-proof protection.
When the driver IC mounting module manufactured in this way is incorporated in a display device, an output terminal portion of the driver IC mounting module and a display electrode terminal of the display panel are connected in a one-to-one correspondence. A flexible cable or the like of the member is prepared, and the terminals are connected via the flexible cable or the like.

  According to the configuration of the third embodiment described above, since the cross wiring of the output line from the driver IC chip is configured by a substrate separate from the substrate on which the driver IC chip is mounted, the ground wiring to the driver IC chip In addition, a sufficient wiring area can be secured for the high-voltage power supply wiring, and the impedance of the lines of these drive wiring systems can be kept low. As a result, while ensuring stable display characteristics and an operation margin for the display panel, a new driving method (that is, an Alis driving method) that uses display cells between all the scan electrodes and the sustain electrodes is surely realized. Can do.

FIG. 16 is a plan view showing the structure of the driver IC mounting module according to the fourth embodiment of the present invention, and FIG. 17 is a sectional view of the structure of the driver IC mounting module according to the fourth embodiment of the present invention. FIG.
The fourth embodiment of the present invention is an application example to the driver IC mounting module on the scan electrode side for realizing a new driving method as in the third embodiment, and the configuration for separating and mounting the driver IC chip. Is the same as in the third embodiment.

In the driver IC mounting module 9 of the fourth embodiment, the configuration of the base substrate 60 serving as a base is almost the same as that of the third embodiment described above, but a cross wiring board for rearranging the output terminal wiring patterns is used. The third embodiment is different from the third embodiment in that the flexible wiring board 73 is made of polyimide film or the like.
In this flexible wiring board 73, an output terminal wiring pattern 72 for rearrangement is formed by a two-layer wiring structure in substantially the same manner as in the third embodiment described above, and an output terminal array is formed on the end face side opposite to the driver IC chip. 71 is provided. However, as in the first and second embodiments described above, the output terminal section is connected to the display electrode terminal by pulling out the output terminal section longer than the bonding area with the base substrate 60. It is formed so that it can be used directly as a terminal.

The electrical connection between the driver IC chip and each substrate is almost the same as that in the third embodiment, and the description thereof is omitted here.
When the driver IC mounting module of the fourth embodiment is incorporated in the display device, unlike the third embodiment, the output terminal row 71 is directly drawn out by the flexible wiring board 73. It is possible to directly connect to the terminal side of the display electrode by thermocompression bonding, thereby reducing costs by reducing the number of members, reducing man-hours by reducing the number of connections, and improving reliability.

As described above, according to the configuration of the fourth embodiment, it is possible to easily realize a new driving method such as the Aris driving method, and to achieve cost reduction and reliability improvement.
FIG. 18 is a plan view showing the structure of the driver IC mounting module according to the fifth embodiment of the present invention, and FIG. 19 is a sectional view of the structure of the driver IC mounting module according to the fifth embodiment of the present invention. FIG.

The fifth embodiment of the present invention is an application example to the driver IC mounting module on the scan electrode side for realizing a new driving method as in the third and fourth embodiments described above. The mounting configuration is the same as in the third and fourth embodiments described above.
In the driver IC mounting module 9 of the fifth embodiment, the shared flexible wiring board 80 of double-sided wiring made of polyimide film or the like is used as the cross wiring board of the input part and the output part.

  The feature of the configuration of the fifth embodiment is that, similarly to the second embodiment described above, an input-related wiring system is configured by cross-wiring using a double-sided common flexible wiring board. An output-related wiring system is configured by cross wiring. That is, in the driver IC mounting module of the fifth embodiment, both wiring pattern portions including the upper surface side wiring pattern 83 and the lower surface side wiring pattern 84 are all realized by a single flexible wiring board. The upper surface side wiring pattern 83 and the lower surface side wiring pattern 84 formed on the shared flexible wiring substrate 80 of the double-sided wiring constitute the shared flexible wiring portion 8.

Further, the common cross wiring substrate 80 is provided with a connection terminal 41 and a cross wiring pattern 82 for the output pad terminal 40 of the driver IC chip in the vicinity of the end face close to the driver IC chip on the surface, An output terminal row 81 is provided on the opposite end face side.
The wiring configuration of the cross wiring pattern 82 described above is that the output terminal wiring from the odd-numbered circuit driver IC chip is extended as it is using the surface and led out as an odd-numbered terminal of the output terminal section, while the even-numbered circuit driver IC chip The output terminal wiring from is routed to the back surface side through a conduction through hole, and is pulled up from the back surface side before the output terminal portion to the front surface side through the conduction through hole, and is derived as an even terminal of the output terminal portion.

Then, the substrate portion of the driver IC mounting module is completed by bonding the completed body of the shared flexible wiring board 80 to the base substrate 60.
18 and 19, as the wiring pattern of the base substrate 60, a two-layer pattern of a high-voltage power supply pattern 66 that constitutes the high-voltage power supply wiring VH and a ground pattern 65 that constitutes the ground wiring GND is provided on the base substrate 60. It is formed. The high voltage power supply voltage of the high voltage power supply pattern 66 is connected to the driver IC chip through the conduction through hole 62 and the connection terminal 64.

  More specifically, in the embodiments of FIGS. 18 and 19, drive power supply system wiring (drive wiring system) for driving the display panel via the odd circuit driver IC group, and the odd circuit driver IC group. A fourth wiring section for odd circuits in which a control system wiring (input-related wiring system) for supplying various signals for controlling the driver IC chip is formed, and a driver IC group for even circuits Drive power supply system wiring (drive wiring system) for driving the display panel, and control system wiring (input relation) for supplying various signals to be input to the driver IC group for the even number circuit to control the driver IC chip And a fourth wiring portion for an even circuit in which a wiring system) is formed. Further, the fifth wiring section in the above embodiment derives the output signal of the odd circuit driver IC group to the odd-numbered corresponding output terminal row (output terminal wiring), and outputs the output circuit of the even circuit driver IC group. A cross wiring pattern (wiring layer) for deriving a signal to an even-numbered corresponding output terminal row (output terminal wiring) is formed.

  Further, in the embodiment of FIGS. 18 and 19, the driving power supply system wiring and the control system wiring in the fourth wiring section for the odd number circuit are used as the first wiring pattern and the second wiring pattern, respectively. In addition, the driving power supply system wiring and the control system wiring in the fourth wiring section for the even number circuit are provided as a third wiring pattern and a fourth wiring pattern, respectively.

18 and FIG. 19, the first wiring pattern and the third wiring pattern are formed on a rigid base substrate, and the second wiring pattern and the third wiring pattern are formed. The fourth wiring pattern and the fifth wiring portion are formed by a flexible wiring board.
In other words, the base substrate 60 of the fifth embodiment needs almost no wiring other than the high-voltage power supply wiring VH and the ground wiring GND, so that a sufficient area for these drive wiring systems is secured. This makes it possible to reduce the number of wiring layers of the base substrate itself (for example, about two layers), to reduce the size, etc., compared to the third and fourth embodiments described above. Significant cost reduction can be realized.

20 is a plan view showing the structure of the driver IC mounting module according to the sixth embodiment of the present invention, and FIG. 21 is a cross-sectional view of the structure of the driver IC mounting module according to the sixth embodiment of the present invention. FIG.
The sixth embodiment of the present invention is an application example to the driver IC mounting module on the scan electrode side for realizing a new driving method as in the third to fifth embodiments, and the driver IC chip is separated. The mounting configuration is the same as in the third to fifth embodiments described above.

In the driver IC mounting module 9 of the sixth embodiment, the common substrate 68 including the cross wiring substrate portion 77 is formed by devising complicated cross wiring on the base substrate itself, and the entire driver IC mounting module is simplified. I am doing so.
That is, the common substrate 68 used in the driver IC mounting module of the sixth embodiment is formed by laminating the common cross wiring substrate portion 77 including the cross wiring layer on the surface layer of the base substrate portion 67, The whole is integrally formed and manufactured as a common substrate.

In the manufacturing process of the common substrate, first, a cross wiring substrate (common cross wiring substrate portion 77) is created by a through hole for conduction using the front and back layers of a double-sided substrate made of glass epoxy material.
The common cross wiring board 77 includes an input cross wiring pattern similar to that of the first embodiment, and an output cross wiring pattern 82 and cross wiring pattern similar to those of the third embodiment. The output terminal array 81 derived from the above is formed, and necessary wiring such as the die bonding pattern of the driver IC chip mounting portion and the related connection terminals with the input / output pad terminals is formed. The cross wiring pattern of the input part of the driver IC mounting module constitutes the common wiring part 6c, and the cross wiring pattern of the output part and the output terminal row constitute the output terminal part.

Next, the base substrate portion is manufactured by a double-sided glass epoxy substrate in which a solid ground pattern 65 is disposed on the front surface layer and a solid high voltage power supply pattern 66 is disposed on the back surface layer, as in the fifth embodiment.
After the double-sided glass epoxy substrate having such a structure is manufactured, the entire common substrate is completed by pasting and combining the common cross wiring substrate portion 77 and the base substrate portion 67 together. At this time, it is necessary to establish continuity with the wiring of the base substrate for the connection terminals for the ground wiring and the high-voltage power supply wiring around the driver IC chip mounting portion. In the process of obtaining such conduction, after the two substrates are bonded together, a through hole hole (that is, a portion corresponding to the conduction through hole 62) is formed in the through hole. This is done by applying conductive plating.

In other words, in the sixth embodiment, the first wiring pattern, the second wiring pattern, the third wiring pattern, the fourth wiring pattern, and the fifth wiring portion described above are used. All have a structure formed of a rigid type common substrate.
In the above driver IC chip, after being mounted and fixed on a die bonding pattern on the surface of the common substrate, each pad terminal and a corresponding terminal on the substrate surface are connected by wire bonding.

  Also in the sixth embodiment, the cross wiring pattern of the input part and the output part can be limited to the upper layer part of the common substrate, so that it is possible to avoid a large number of through holes for cross wiring penetrating the substrate. It is possible to secure a sufficient wiring area for the ground wiring and the high-voltage power supply wiring provided in the lower layer portion of the common substrate, and the same effect as the above-described embodiment can be expected.

In addition, since the entire board of the driver IC mounting module is configured by a single rigid board, the structure is simplified, thereby reducing the size and cost of the entire apparatus.
In the first to sixth embodiments described above, in areas other than the portions that require electrical connection of the terminal portions, driver IC chips, and other component mounting portions on the surface of each wiring board, Usually, an insulating coating (for example, a resist film or a cover lay film) is applied, but the description thereof is omitted.

  As described above, the configuration of the embodiment of the present invention has been described with respect to the case where it is applied to a three-electrode surface discharge AC plasma display panel. However, according to the gist of the present invention, Is of course applicable. Furthermore, the characteristics of the charge / discharge current flowing to the capacitive component during driving are similar to those of EL display panels and large LCD panels that exhibit capacitive load characteristics. It is clear that the module is applicable.

(Supplementary Note 1) In a driver IC mounting module having a driver IC chip for driving display electrodes of a flat panel display panel and a wiring board electrically connected to the driver IC chip, at least
A drive power supply system wiring section formed with a drive power supply system wiring that is input to the driver IC chip and supplies a power supply voltage for driving the flat panel display panel via the driver IC chip;
A control system wiring section formed with a control system wiring for supplying various signals to be input to the driver IC chip and for controlling the driver IC chip;
An output terminal wiring portion that is derived from the driver IC chip and is formed with an output terminal wiring for connecting to the display electrode of the flat panel display panel;
Each of the drive power supply system wiring section, the control system wiring section, and the output terminal wiring section is arranged separately in different wiring layers or wiring areas, and between each wiring section and the driver IC chip. A driver IC mounting module having a configuration in which electrical connection is made.
(Supplementary Note 2) The driving power supply system wiring is a solid wiring pattern including a solid high voltage power supply wiring layer formed over substantially the entire region or a solid ground wiring layer formed over the entire region. The driver IC mounting module according to claim 1, wherein the driver IC mounting module is configured to be directly supplied to the driver IC chip from the solid wiring pattern.
(Additional remark 3) The wiring part which consists of all the three wiring parts of the said drive power supply system wiring part, the said control system wiring part, and the said output terminal wiring part, or the combination of two of these wiring parts is one wiring. The driver IC mounting module according to appendix 1 or 2, formed in a substrate.

(Supplementary Note 4) In a driver IC mounting module having a driver IC chip for driving display electrodes of a flat panel display panel and a wiring board electrically connected to the driver IC chip, at least
A drive power supply system wiring section formed with a drive power supply system wiring that is input to the driver IC chip and supplies a power supply voltage for driving the flat panel display panel via the driver IC chip;
A control system wiring section formed with a control system wiring for supplying various signals to be input to the driver IC chip and for controlling the driver IC chip;
An output terminal wiring section in which an output terminal wiring for converting the arrangement order of output signals output from the driver IC chip into a different arrangement order and connecting to display electrodes of the flat panel display panel is provided. A featured driver IC mounting module.
(Additional remark 5) The said drive power supply system wiring is the said drive power supply system wiring as a solid wiring pattern including the solid-shaped high voltage power supply wiring layer formed over substantially the whole area, or the solid-like earth wiring layer formed over the substantially whole area. 5. The driver IC mounting module according to appendix 4, wherein the driver IC mounting module is configured to be directly supplied to the driver IC chip from the solid wiring pattern.
(Supplementary Note 6) A connection terminal is provided around the driver IC chip on the surface of the drive power supply system wiring section, the control system wiring section, and the output terminal wiring section on which the driver IC chip is mounted. 6. The driver IC mounting module according to appendix 4 or 5, wherein the driver IC mounting module is configured to connect the corresponding pad terminals on the driver IC chip.

(Additional remark 7) It has the driver IC group for odd circuits connected to the odd-numbered output terminal wiring, and the driver IC group for even circuits connected to the even-numbered output terminal wiring,
A drive power supply system wiring section for odd circuits in which a drive power supply system wiring for supplying a drive voltage for driving the flat panel display panel via the odd circuit driver IC group is formed;
A control system wiring section for odd circuits formed with a control system wiring for supplying various signals to be input to the odd number driver IC group and to control the driver IC chip;
A drive power supply system wiring section for even circuits formed with drive power supply system wiring for supplying a power supply voltage for driving the flat panel display panel via the even circuit driver IC group;
A control system wiring section for even circuits formed with a control system wiring for supplying various signals to be input to the driver IC group for the even circuit and to control the driver IC chip,
The output terminal wiring portion derives an output signal of the odd-numbered circuit driver IC group to the odd-numbered corresponding output terminal wiring, and outputs an output signal of the even-numbered circuit driver IC group to the even-numbered corresponding output terminal. The driver IC mounting module according to any one of appendices 4 to 6, wherein the driver IC mounting module has a structure in which a wiring layer for leading to wiring is formed.
(Supplementary Note 8) The drive power supply system wiring and the control system wiring in the drive power supply system wiring section and the control system wiring section for the odd circuit are respectively used as a drive power supply system wiring pattern and a control system wiring pattern for the odd circuit. While providing
The drive power supply system wiring and the control system wiring in the drive power supply system wiring section and the control system wiring section for the even number circuit are provided as a drive power supply system wiring pattern and a control system wiring pattern for the even number circuit, respectively. The driver IC mounting module according to appendix 7.
(Supplementary note 9) All three wiring parts of the drive power supply system wiring part, the control system wiring part and the output terminal wiring part, or a wiring part formed by a combination of the two wiring parts among them is one wiring. The driver IC mounting module according to any one of appendices 4 to 8 formed in the substrate.

(Supplementary note 10) Any one of Supplementary notes 1 to 9, wherein a plurality of input terminals are provided in the input unit, and the plurality of input terminals are connected to the drive power supply system wiring and the control system wiring, respectively. The driver IC mounting module described in 1.
(Supplementary Note 11) An input connector is mounted on the input unit, and the power supply voltage and various signals are input from the external substrate to the drive power supply system wiring and the control system wiring via the input connector, respectively. The driver IC mounting module according to any one of appendices 1 to 10.

(Supplementary Note 12) In a driver IC mounting module having a driver IC chip for driving display electrodes of a flat panel display panel and a wiring board electrically connected to the driver IC chip, at least
Drive power supply system wiring that is input to the driver IC chip and supplies a power supply voltage for driving the flat panel display panel via the driver IC chip;
Control system wiring that is input to the driver IC chip and supplies various signals for controlling the driver IC chip;
An output terminal wiring for converting the arrangement order of output signals output from the driver IC chip into a different arrangement order and connecting to the display electrodes of the flat panel display panel;
A base substrate on which at least the driving system wiring is formed;
A driver IC mounting module comprising: a sub-board on which at least the output terminal wiring is formed, wherein at least a part of the sub-board is bonded to the base board.
(Supplementary note 13) The driver IC mounting module according to supplementary note 12, wherein the control system wiring is formed on at least a part of the base substrate.
(Supplementary note 14) The driver IC mounting module according to supplementary note 12, wherein the control system wiring is formed on at least a part of the sub-board.
(Additional remark 15) The driver IC mounting module of Additional remark 12 or 14 with which the said sub board | substrate is comprised with the flexible substrate.
(Supplementary Note 16) The driver IC mounting module according to any one of Supplementary notes 1 to 15, wherein the flat display panel is a plasma display panel.

It is a top view which shows the structure of the driver IC mounting module which concerns on 1st Example of this invention. It is a figure which shows the structure of the driver IC mounting module which concerns on 1st Example of this invention in a cross section. It is a top view which shows the structure of the driver IC mounting module which concerns on the 2nd Example of this invention. It is a figure which shows the structure of the driver IC mounting module which concerns on 2nd Example of this invention in a cross section. 1 is a plan view showing a schematic configuration of an interlaced surface discharge AC plasma display panel. FIG. FIG. 6 is a perspective view showing a state in which the facing distance between color pixels of the surface discharge type AC plasma display panel of FIG. FIG. 6 is a longitudinal sectional view taken along a sustain electrode X1 of a color pixel of the surface discharge AC plasma display panel of FIG. It is a figure which shows the structural example of the flame | frame for forming the color pixel of the surface discharge type AC plasma display panel of FIG. It is a figure which shows the order of the display scan in the address period of the flame | frame of FIG. FIG. 6 is an electrode applied voltage waveform diagram in an odd field showing the surface discharge AC plasma display panel driving method of FIG. 5. FIG. 6 is an electrode applied voltage waveform diagram in an even field showing a method of driving the surface discharge AC plasma display panel of FIG. 5. FIG. 6 is a block diagram illustrating a schematic configuration of a driving device for the surface discharge AC plasma display panel of FIG. 5. It is a block diagram which shows the circuit structure of the driver IC mounting module which concerns on the 3rd Example of this invention. It is a top view which shows the structure of the driver IC mounting module which concerns on the 3rd Example of this invention. It is a figure which shows the structure of the driver IC mounting module which concerns on the 3rd Example of this invention in a cross section. It is a top view which shows the structure of the driver IC mounting module which concerns on the 4th Example of this invention. It is a figure which shows the structure of the driver IC mounting module which concerns on the 4th Example of this invention in a cross section. It is a top view which shows the structure of the driver IC mounting module which concerns on the 5th Example of this invention. It is a figure which shows the structure of the driver IC mounting module which concerns on the 5th Example of this invention in a cross section. It is a top view which shows the structure of the driver IC mounting module which concerns on the 6th Example of this invention. It is a figure which shows the structure of the driver IC mounting module which concerns on the 6th Example of this invention in a cross section. It is a top view which shows typically the structure of a general surface discharge type AC plasma display panel. It is sectional drawing which shows typically the structure of a general surface discharge type AC plasma display panel. It is a block diagram which shows the principal part of the drive circuit with respect to a general surface discharge type AC plasma display panel. 25 is a timing chart for explaining the operation of the drive circuit of FIG. FIG. 25 is a plan view showing a connection structure between the driver IC mounting module on the scanning electrode side and the panel electrode in FIG. 24. FIG. 27 is a block diagram illustrating a circuit configuration of the driver IC mounting module of FIG. 26. FIG. 27 is a circuit diagram showing a circuit configuration of each driver IC chip in the driver IC mounting module of FIG. 26; It is a figure which shows the structure of the 1st example of the conventional driver IC mounting module in a cross section. It is a figure which shows the structure of the 2nd example of the conventional driver IC mounting module in a cross section. 6 is a timing chart showing a relationship between a drive voltage and a drive current of a scan electrode in a general surface discharge AC plasma display panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st wiring part 2 ... 2nd wiring part 2c ... Shared cross wiring part 3 ... 3rd wiring part 3c ... Output terminal part 4 ... Driver IC chip 5 ... Input connector 6 ... 4th wiring part 6c ... Common wiring portion 7 ... Fifth wiring portion 8 ... Common flexible wiring portion 9 ... Driver IC mounting module 10 ... Base substrate 11 ... Earth pattern 12 ... High voltage power supply pattern 13 ... Connecting terminal 14 ... Conduction through hole 15 ... Insulating plate DESCRIPTION OF SYMBOLS 20 ... Cross wiring board 21 ... Cross wiring pattern 22 ... Shared flexible wiring board 23 ... Upper surface side wiring pattern 24 ... Lower surface side wiring pattern 30 ... Flexible wiring board 31 ... Output terminal wiring pattern 40 ... Pad terminal 41 ... Connection terminal 60 ... Base substrate 61... Input signal line and power line wiring pattern 62... Through hole 63 for conduction 63. Insulation plate 64. 66 ... High voltage power supply pattern 67 ... Base substrate portion 68 ... Common substrate 70 ... Cross wiring substrate 71 ... Output terminal array 72 ... Cross wiring pattern 73 ... Flexible wiring substrate 77 ... Common cross wiring substrate portion 80 ... Common flexible wiring substrate 81 ... output terminal row 82 ... cross wiring pattern 83 ... upper surface side wiring pattern 84 ... lower surface side wiring pattern 100 ... display panel (101-1) to (101-3) ... single color pixel 100a ... color pixels 121 and 122 ... transparent electrode 131 132 ... Metal electrodes 171-174 ... Branches 181-183 ... Phosphor 200 ... Plasma display panel driving device 210 ... Control circuit 220 ... Address circuit 230 ... Scanning circuit 240 ... Odd Y common driver 250 ... Even Y common driver 260 ... Odd X common driver 270 ... even X common driver 300 ... table Panel 310 ... Front glass substrate 320 ... Rear glass substrate 330 ... Partition wall 340 ... Display cell 360 ... Phosphor 370 ... Control circuit 380 ... Address circuit 390 ... X common driver 391 ... Y common driver 392 ... Scan circuit 400 ... Driver IC chip 410 ... Pad terminal 420 ... Connection terminal 430 ... Printed circuit board 440 ... Input signal line and power line wiring pattern 450 ... Output terminal connection pattern 460 ... Input connector 461,462 ... Input connector 471,472 ... Output terminal part 480 ... Flexible wiring board 490 ... Output terminal wiring pattern 500 ... Composite substrate 510 ... Printed circuit board 520 ... Input signal line and power line wiring pattern 530 ... Flexible wiring board 540 ... Output terminal wiring pattern

Claims (8)

In a driver IC mounting module having a driver IC chip for driving display electrodes of a flat panel display panel, and a wiring board electrically connected to the driver IC chip, at least
A drive power supply system wiring section formed with a drive power supply system wiring that is input to the driver IC chip and supplies a power supply voltage for driving the flat panel display panel via the driver IC chip;
A control system wiring section formed with a control system wiring for supplying various signals to be input to the driver IC chip and for controlling the driver IC chip;
An output terminal wiring section in which an output terminal wiring for converting the arrangement order of output signals output from the driver IC chip into a different arrangement order and connecting to display electrodes of the flat panel display panel is provided. A featured driver IC mounting module.   The drive power supply system wiring is formed in the drive power supply system wiring section as a solid wiring pattern including a solid high-voltage power supply wiring layer formed over almost the entire region or a solid earth wiring layer formed over the entire region. The driver IC mounting module according to claim 1, wherein the power supply voltage is directly supplied from the solid wiring pattern to the driver IC chip.   All three wiring sections of the driving power supply system wiring section, the control system wiring section, and the output terminal wiring section, or a wiring section composed of a combination of the two wiring sections is formed in one wiring board. 3. The driver IC mounting module according to claim 1, wherein the driver IC mounting module is used. In a driver IC mounting module having a driver IC chip for driving display electrodes of a flat panel display panel, and a wiring board electrically connected to the driver IC chip, at least
Drive power supply system wiring that is input to the driver IC chip and supplies a power supply voltage for driving the flat panel display panel via the driver IC chip;
Control system wiring that is input to the driver IC chip and supplies various signals for controlling the driver IC chip;
An output terminal wiring for converting the arrangement order of output signals output from the driver IC chip into a different arrangement order and connecting to the display electrodes of the flat panel display panel;
A base substrate on which at least the driving system wiring is formed;
A driver IC mounting module comprising: a sub-board on which at least the output terminal wiring is formed, wherein at least a part of the sub-board is bonded to the base board.   The driver IC mounting module according to claim 4, wherein the control system wiring is formed on at least a part of the base substrate.   The driver IC mounting module according to claim 4, wherein the control system wiring is formed on at least a part of the sub-board.   The driver IC mounting module according to claim 4 or 6, wherein the sub-board is a flexible board.   The driver IC mounting module according to claim 1, wherein the flat display panel is a plasma display panel.

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