JP2005108946A - Failure detection method and failure-detecting apparatus of stacked ceramic capacitor - Google Patents

Failure detection method and failure-detecting apparatus of stacked ceramic capacitor Download PDF

Info

Publication number
JP2005108946A
JP2005108946A JP2003337117A JP2003337117A JP2005108946A JP 2005108946 A JP2005108946 A JP 2005108946A JP 2003337117 A JP2003337117 A JP 2003337117A JP 2003337117 A JP2003337117 A JP 2003337117A JP 2005108946 A JP2005108946 A JP 2005108946A
Authority
JP
Japan
Prior art keywords
ceramic capacitor
multilayer ceramic
internal electrodes
insulation
failure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003337117A
Other languages
Japanese (ja)
Inventor
Kazunori Ito
和則 伊東
Yusaku Horie
優作 堀江
Kazuyuki Hasebe
和幸 長谷部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP2003337117A priority Critical patent/JP2005108946A/en
Publication of JP2005108946A publication Critical patent/JP2005108946A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide the failure detecting method of a stacked ceramic capacitor wherein a defective insulation layer can be specified accurately. <P>SOLUTION: In a stacked ceramic capacitor set as the application object of the failure detection method, a plurality of internal electrodes 36, 37 are embedded in layers in the inside of a dielectrics substrate 31. The internal electrodes 36, 37 are constituted, by electrically conducting to a pair of terminal electrodes 32, 33 which are applied to the external surface of the dielectrics substrate 31. When a failure is detected, the stacked ceramic capacitor is set under a temperature environment of at least 60°C and so ground that the ground surface perpendicular to the direction of lamination of the internal electrodes 36, 37 is produced, and the insulation resistance between the terminal electrodes 32-33 is measured. Poor insulation is detected by increase of measuring resistance value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、積層セラミックコンデンサの不良検出方法、及び、その不良検出方法に用いられる不良検出装置に関する。   The present invention relates to a failure detection method for a multilayer ceramic capacitor and a failure detection apparatus used in the failure detection method.

積層セラミックコンデンサは、内部電極パターンを印刷したセラミックグリーンシート(未焼成セラミックシート)を所定枚数積層し、その後、ラミネート(加熱圧縮一体化)、切断、脱脂、焼成等の必要な工程を経て製造される。   Multilayer ceramic capacitors are manufactured by laminating a predetermined number of ceramic green sheets (unfired ceramic sheets) printed with internal electrode patterns, and then performing necessary steps such as laminating (heat compression integration), cutting, degreasing, and firing. The

この種の積層セラミックコンデンサにおいて、セラミック層の絶縁不良から生じる不良品の発生を防止するには、絶縁不良を生じている層を特定し、その結果を製品の設計や製造等に反映させる必要がある。   In this type of multilayer ceramic capacitor, in order to prevent the occurrence of defective products caused by defective insulation of the ceramic layer, it is necessary to identify the layer causing the defective insulation and reflect the result in the design and manufacture of the product. is there.

絶縁不良層を特定する方法としては、様々な方法が今まで提案されてきている。例えば特許文献1は、研磨装置を用いて積層磁器コンデンサを研磨すると共に、両端子電極間の絶縁抵抗(IR)を測定し、測定抵抗値の上昇を検出することにより絶縁不良層を特定する方法を開示している。かかる方法で絶縁不良層を特定するには、測定抵抗値が上昇して充分な有意差を生じることが必要となる。   Various methods have been proposed so far for identifying a poor insulation layer. For example, Patent Document 1 discloses a method of identifying a poor insulation layer by polishing a laminated ceramic capacitor using a polishing apparatus, measuring an insulation resistance (IR) between both terminal electrodes, and detecting an increase in the measured resistance value. Is disclosed. In order to identify a poor insulation layer by such a method, it is necessary that the measured resistance value rises to produce a sufficiently significant difference.

しかし、積層セラミックコンデンサの研磨及び絶縁抵抗の測定を、常温(25℃)環境下で行うと、測定抵抗値について充分な有意差が得られず、絶縁不良層を特定するのが難しい。   However, if the polishing of the multilayer ceramic capacitor and the measurement of the insulation resistance are performed in a room temperature (25 ° C.) environment, a sufficient significant difference cannot be obtained in the measured resistance value, and it is difficult to specify a poor insulation layer.

特許文献2は、積層セラミックコンデンサを加熱した状態で絶縁抵抗を測定し、測定抵抗の異常品を特性不良品として選別除去する技術を開示している。しかし、研磨と共に絶縁抵抗を測定する点については言及がない。   Patent Document 2 discloses a technique for measuring an insulation resistance in a state where a multilayer ceramic capacitor is heated, and selecting and removing a product having an abnormal measurement resistance as a defective product. However, there is no mention of measuring the insulation resistance with polishing.

特許文献3は、キュリー温度以上かつ125℃以上の温度に加熱する点は記載があるが、インピーダンスの位相角、周波数と位相角との関係から、IRおよびIR寿命を予測し判定するものであり、IRを直接に測定する技術を開示するものではない。更に、研磨処理と共に絶縁抵抗を測定する点についても言及がない。   Although Patent Document 3 describes that heating is performed at a temperature equal to or higher than the Curie temperature and equal to or higher than 125 ° C., IR and IR lifetime are predicted and determined from the relationship between the impedance phase angle and the frequency and phase angle. It does not disclose a technique for directly measuring IR. Furthermore, there is no mention of measuring the insulation resistance together with the polishing treatment.

特許文献4は、直流電圧を印加して絶縁抵抗値を算出した後、キュリー温度以上に加熱する技術を開示するものであり、加熱状態で絶縁抵抗を測定する技術を開示するものではない。更に、研磨処理と共に絶縁抵抗を測定する点についても言及がない。
特開平5−107291号公報 特開平9−205037号公報 特開2000−260653号公報 特開2002−168897号公報
Patent Document 4 discloses a technique of heating the insulation resistance value by applying a DC voltage to the Curie temperature or higher, and does not disclose a technique of measuring the insulation resistance in a heated state. Furthermore, there is no mention of measuring the insulation resistance together with the polishing treatment.
Japanese Patent Laid-Open No. 5-107291 JP-A-9-205037 JP 2000-260653 A JP 2002-168897 A

本発明の課題は、絶縁不良層を、正確に特定し得る積層セラミックコンデンサの不良検出方法、及び、その不良検出方法に用いられる不良検出装置を提供することである。   An object of the present invention is to provide a method for detecting a defect of a multilayer ceramic capacitor capable of accurately specifying a defective insulation layer, and a defect detection device used in the defect detection method.

上述した課題を解決するため、本発明は、積層セラミックコンデンサの不良検出方法及び不良検出装置に向けられている。   In order to solve the above-described problems, the present invention is directed to a failure detection method and failure detection apparatus for a multilayer ceramic capacitor.

1.積層セラミックコンデンサの不良検出方法
前記積層セラミックコンデンサは、誘電体基体の内部に、複数の内部電極を、層状に埋設してあり、前記内部電極は前記誘電体基体の外面に付与された対の端子電極に導通させてある。
1. Defect detection method for multilayer ceramic capacitor The multilayer ceramic capacitor has a plurality of internal electrodes embedded in a dielectric substrate, and the internal electrodes are a pair of terminals provided on the outer surface of the dielectric substrate. Conducted to the electrode.

不良検出にあたっては、前記積層セラミックコンデンサを、60℃以上の温度環境下におき、前記積層セラミックコンデンサを、前記内部電極の積層方向に垂直な研磨面を生じるように研磨すると共に前記端子電極間の絶縁抵抗を測定し、測定抵抗値の上昇により絶縁不良を検出する。   In detecting defects, the multilayer ceramic capacitor is placed in a temperature environment of 60 ° C. or higher, and the multilayer ceramic capacitor is polished so as to produce a polished surface perpendicular to the stacking direction of the internal electrodes, and between the terminal electrodes. Measure the insulation resistance and detect insulation failure by increasing the measured resistance value.

上述したように、積層セラミックコンデンサについて内部電極の積層方向に垂直な研磨面を生じるように研磨すると共に端子電極間の絶縁抵抗を測定すると、研磨位置が絶縁不良層まで到達したとき、測定抵抗値が上昇する。このような方法で絶縁不良層を特定するには、測定抵抗値が充分な有意差を伴って上昇することが必要となる。   As described above, when the multilayer ceramic capacitor is polished so as to produce a polished surface perpendicular to the stacking direction of the internal electrodes and the insulation resistance between the terminal electrodes is measured, the measured resistance value is measured when the polishing position reaches the poor insulation layer. Rises. In order to identify a poor insulation layer by such a method, it is necessary to increase the measured resistance value with a sufficiently significant difference.

発明者らの実験によれば、60℃以上の温度環境下で、積層セラミックコンデンサの両端子電極間の絶縁抵抗を測定すると、積層セラミックコンデンサの絶縁良好品と絶縁不良品との間で、測定抵抗値に充分な有意差が生じることがわかった。   According to the experiments by the inventors, when the insulation resistance between both terminal electrodes of a multilayer ceramic capacitor is measured in a temperature environment of 60 ° C. or higher, the measurement is performed between a good insulation product and a poor insulation product of the multilayer ceramic capacitor. It was found that there was a significant difference in resistance value.

従って、積層セラミックコンデンサの研磨及び絶縁抵抗の測定を、60℃以上の温度環境下で行うと、研磨に伴う測定抵抗値の上昇に、充分な有意差を生じさせることが可能となる。測定抵抗値が充分な有意差を伴って上昇するようになると、測定抵抗値の上昇を明確に検出することが可能となり、これにより、絶縁不良層を正確に特定することができる。   Therefore, when the polishing of the multilayer ceramic capacitor and the measurement of the insulation resistance are performed in a temperature environment of 60 ° C. or higher, it is possible to cause a sufficiently significant difference in the increase in the measured resistance value accompanying the polishing. When the measured resistance value rises with a sufficiently significant difference, it is possible to clearly detect an increase in the measured resistance value, thereby accurately identifying a poor insulation layer.

2.積層セラミックコンデンサの不良検出装置
積層セラミックコンデンサの不良検出装置は、研磨装置と、加熱手段と、抵抗測定装置とを含む。前記積層セラミックコンデンサは、誘電体基体の内部に、複数の内部電極を、層状に埋設してあり、前記内部電極は前記誘電体基体の外面に付与された対の端子電極に導通させてある。
2. Multilayer Ceramic Capacitor Defect Detection Device The multilayer ceramic capacitor defect detection device includes a polishing device, a heating means, and a resistance measurement device. In the multilayer ceramic capacitor, a plurality of internal electrodes are embedded in layers inside a dielectric substrate, and the internal electrodes are electrically connected to a pair of terminal electrodes provided on the outer surface of the dielectric substrate.

前記研磨装置は、前記積層セラミックコンデンサを、前記内部電極の積層方向に垂直な研磨面を生じるように研磨する。前記加熱手段は、前記積層セラミックコンデンサに60℃以上の温度環境を与える。前記抵抗測定装置は、前記積層セラミックコンデンサの前記端子電極間の絶縁抵抗を測定する。   The polishing apparatus polishes the multilayer ceramic capacitor so as to produce a polishing surface perpendicular to the stacking direction of the internal electrodes. The heating means gives a temperature environment of 60 ° C. or higher to the multilayer ceramic capacitor. The resistance measuring device measures an insulation resistance between the terminal electrodes of the multilayer ceramic capacitor.

かかる不良検出装置によれば、上述した本発明に係る不良検出方法を実施することができる。   According to such a defect detection apparatus, the above-described defect detection method according to the present invention can be implemented.

以上述べたように、本発明によれば、絶縁不良層を、正確に特定し得る積層セラミックコンデンサの不良検出方法、及び、その不良検出方法に用いられる不良検出装置を提供することができる。   As described above, according to the present invention, it is possible to provide a failure detection method for a multilayer ceramic capacitor that can accurately identify an insulation failure layer, and a failure detection device used in the failure detection method.

本発明の他の目的、構成及び利点については、実施例を参照して更に具体的に説明する。   Other objects, configurations and advantages of the present invention will be described more specifically with reference to examples.

図1〜図3を参照し、本発明に係る不良検出方法を説明する。まず、図1を参照すると、本発明に係る不良検出方法の適用対象となる積層セラミックコンデンサが、断面図として表示されている。図示の積層セラミックコンデンサは、誘電体基体31の内部に、複数の内部電極36、37を、層状に埋設してある。隣接する2つの内部電極36、37は、例えば、10μm以下の誘電体層を介して向き合っている。内部電極36、37は、例えば、NiまたはCuなどによって構成される。内部電極36、37の層数は、要求される静電容量に応じて変化するもので、数十層〜数百層になる。   A defect detection method according to the present invention will be described with reference to FIGS. First, referring to FIG. 1, a multilayer ceramic capacitor to which a defect detection method according to the present invention is applied is displayed as a cross-sectional view. In the illustrated multilayer ceramic capacitor, a plurality of internal electrodes 36 and 37 are embedded in a dielectric substrate 31 in layers. Two adjacent internal electrodes 36 and 37 face each other through a dielectric layer of 10 μm or less, for example. The internal electrodes 36 and 37 are made of, for example, Ni or Cu. The number of layers of the internal electrodes 36 and 37 varies depending on the required capacitance, and is several tens to several hundreds.

内部電極36は、誘電体基体1の外面に付与された対の端子電極32、33のうち、端子電極32に導通させてあり、内部電極37は端子電極33に導通させてある。端子電極32、33は、端子電極32、33の電極面に平行な方向でみた誘電体基体1の両端面に備えられている。   The internal electrode 36 is electrically connected to the terminal electrode 32 of the pair of terminal electrodes 32 and 33 provided on the outer surface of the dielectric substrate 1, and the internal electrode 37 is electrically connected to the terminal electrode 33. The terminal electrodes 32 and 33 are provided on both end surfaces of the dielectric substrate 1 viewed in a direction parallel to the electrode surfaces of the terminal electrodes 32 and 33.

かかる構成の積層セラミックコンデンサについて、図示のように内部電極36‐37間の層に絶縁不良部分Fを生じたと仮定する。この場合、絶縁抵抗計9などで端子電極32−33間の抵抗値を確認することにより、積層セラミックコンデンサの絶縁不良が検出される。   In the multilayer ceramic capacitor having such a configuration, it is assumed that a defective insulation portion F is generated in the layer between the internal electrodes 36-37 as shown in the figure. In this case, the insulation failure of the multilayer ceramic capacitor is detected by confirming the resistance value between the terminal electrodes 32-33 with the insulation resistance meter 9 or the like.

図1のステップによれば、積層セラミックコンデンサの絶縁不良を検出することはできるが、絶縁不良を生じた層を特定することはできない。そこで、図1に示した検査ステップにおいて、絶縁不良とされた積層セラミックコンデンサについて、絶縁不良を生じた層を特定するため、図2〜図3に示す不良検出方法を実行する。   According to the steps of FIG. 1, it is possible to detect insulation failure of the multilayer ceramic capacitor, but it is not possible to identify the layer in which insulation failure has occurred. Accordingly, in the inspection step shown in FIG. 1, the failure detection method shown in FIGS. 2 to 3 is executed in order to identify the layer in which the insulation failure has occurred in the multilayer ceramic capacitor that has been determined to have insulation failure.

図2は、本発明に係る積層セラミックコンデンサの不良検出方法の実施に用いられる不良検出装置の構成を示す図である。図示において、1は研磨装置、2は抵抗測定装置、3は不良品検査対象となる積層セラミックコンデンサをそれぞれ示している。   FIG. 2 is a diagram showing a configuration of a defect detection apparatus used for carrying out the multilayer ceramic capacitor defect detection method according to the present invention. In the figure, reference numeral 1 denotes a polishing device, 2 denotes a resistance measuring device, and 3 denotes a multilayer ceramic capacitor to be inspected for defective products.

研磨装置1は、積層セラミックコンデンサ3について内部電極36、37の積層方向に垂直な研磨面を生じるように研磨する。言い換えれば、内部電極36、37の電極面に平行な研磨面を生じるように研磨する。具体的には、研磨装置1は、テーブル11と、研磨具12とを有する。テーブル11は、図示しないモータ等の駆動源により、矢印aまたはbの方向の直線送りが加えられる。テーブル11の上には積層セラミックコンデンサ3が固定して搭載されている。積層セラミックコンデンサ3の固定に当っては、テーブル11の上に基板13を配置すると共に、基板13を固定具14、15によってテーブル11の上に固定し、更に基板13の上に積層セラミックコンデンサ3を固定する。基板13に対する積層セラミックコンデンサ3の固定手段としては、はんだ等が挙げられる。図示と異なり、エポキシ樹脂、または、松やに系などのアドフィックスに積層セラミックコンデンサを埋め込んでも固定することができる。   The polishing apparatus 1 polishes the multilayer ceramic capacitor 3 so that a polishing surface perpendicular to the stacking direction of the internal electrodes 36 and 37 is generated. In other words, the polishing is performed so as to produce a polishing surface parallel to the electrode surfaces of the internal electrodes 36 and 37. Specifically, the polishing apparatus 1 includes a table 11 and a polishing tool 12. The table 11 is linearly fed in the direction of arrow a or b by a drive source such as a motor (not shown). A multilayer ceramic capacitor 3 is fixedly mounted on the table 11. In fixing the multilayer ceramic capacitor 3, the substrate 13 is disposed on the table 11, the substrate 13 is fixed on the table 11 by the fixtures 14 and 15, and the multilayer ceramic capacitor 3 is further mounted on the substrate 13. To fix. As a means for fixing the multilayer ceramic capacitor 3 to the substrate 13, solder or the like can be cited. Unlike the illustrated example, it can be fixed by embedding a multilayer ceramic capacitor in an epoxy resin or a pine or other adhesive.

研磨具12はテーブル11の上方に配置され、積層セラミックコンデンサ3を研磨するように矢印cで示す如く回転駆動される。研磨具12は、図示しないモータ等の回転駆動源に連結されたスピンドル121の先端に砥石取付部122を有し、砥石取付部122の先端面に砥石123を取付けた構造となっている。17はドレッシング用砥石、18は研磨具12を回転駆動する駆動系を制御する制御回路、19はテーブル12を駆動する駆動系を制御する制御回路をそれぞれ示している。   The polishing tool 12 is disposed above the table 11 and is driven to rotate as indicated by an arrow c so as to polish the multilayer ceramic capacitor 3. The polishing tool 12 has a structure in which a grindstone mounting portion 122 is provided at the tip of a spindle 121 connected to a rotational drive source such as a motor (not shown), and a grindstone 123 is attached to the tip surface of the grindstone mounting portion 122. Reference numeral 17 denotes a dressing grindstone, 18 denotes a control circuit that controls a drive system that rotationally drives the polishing tool 12, and 19 denotes a control circuit that controls a drive system that drives the table 12.

加熱手段は、積層セラミックコンデンサ3に60℃以上の温度環境を与える。このような加熱手段としては、様々なものが考えられる。例えば、積層セラミックコンデンサ3を載せる基板13を、電熱線などにより加熱してもよいし、または、加熱されたシリコン液を、ノズル16から積層セラミックコンデンサ3に流してもよいし、または、恒温槽を利用してもよい。積層セラミックコンデンサ3に与えられる温度環境は、例えば、積層セラミックコンデンサ3の付近に設置された温度センサーにより制御することができる。上限温度については、積層セラミックコンデンサ3の構成材料や、研磨装置1の構成部品が耐え得る温度に設定すればよい。   The heating means gives a temperature environment of 60 ° C. or higher to the multilayer ceramic capacitor 3. Various heating means can be considered. For example, the substrate 13 on which the multilayer ceramic capacitor 3 is placed may be heated by a heating wire or the like, or the heated silicon liquid may be flowed from the nozzle 16 to the multilayer ceramic capacitor 3 or a thermostatic chamber. May be used. The temperature environment given to the multilayer ceramic capacitor 3 can be controlled by, for example, a temperature sensor installed in the vicinity of the multilayer ceramic capacitor 3. The upper limit temperature may be set to a temperature that can be withstood by the constituent material of the multilayer ceramic capacitor 3 and the constituent parts of the polishing apparatus 1.

抵抗測定装置2は、積層セラミックコンデンサ3の端子電極32、33に、電気配線d、eを介して電気的に接続され、端子電極32−33間の絶縁抵抗を測定する。21は電源、22は抵抗測定回路である。   The resistance measuring device 2 is electrically connected to the terminal electrodes 32 and 33 of the multilayer ceramic capacitor 3 via electric wirings d and e, and measures the insulation resistance between the terminal electrodes 32-33. Reference numeral 21 denotes a power source, and 22 denotes a resistance measurement circuit.

図1に示された積層セラミックコンデンサ3について絶縁不良層を特定するには、積層セラミックコンデンサ3を図2に示したような状態で、テーブル11上に固定して搭載する。そして、図3(a)に示すように、テーブル11に矢印aまたはb方向の直線送りを加えながら、研磨具12を矢印cの方向に回転駆動し、積層セラミックコンデンサ3を研磨する。これにより、積層セラミックコンデンサ3について内部電極36、37の積層方向に垂直な研磨面を生じるように研磨することができる。   In order to identify a poor insulation layer for the multilayer ceramic capacitor 3 shown in FIG. 1, the multilayer ceramic capacitor 3 is fixedly mounted on the table 11 in the state shown in FIG. Then, as shown in FIG. 3A, the polishing tool 12 is rotationally driven in the direction of arrow c while applying linear feed in the direction of arrow a or b to the table 11, and the multilayer ceramic capacitor 3 is polished. Thus, the multilayer ceramic capacitor 3 can be polished so as to produce a polished surface perpendicular to the stacking direction of the internal electrodes 36 and 37.

積層セラミックコンデンサ3を研磨すると端子電極32−33間の絶縁抵抗を測定すると、図3(b)に示すように、研磨位置が誘電体基体1内の絶縁不良部分Fまで到達したとき、測定抵抗値が上昇する。このような方法で絶縁不良層を特定するには、測定抵抗値が充分な有意差を伴って上昇することが必要となる。   When the multilayer ceramic capacitor 3 is polished, the insulation resistance between the terminal electrodes 32-33 is measured. As shown in FIG. 3B, when the polishing position reaches the defective insulation portion F in the dielectric substrate 1, the measured resistance is measured. The value rises. In order to identify a poor insulation layer by such a method, it is necessary to increase the measured resistance value with a sufficiently significant difference.

図4は、積層セラミックコンデンサの絶縁良好品と絶縁不良品とについて環境温度に対する測定抵抗値を示すデータである。積層セラミックコンデンサの誘電体基体を構成する誘電体材料としてはチタン酸バリウムを主成分とする(B特性)材料を用いた。   FIG. 4 is data showing measured resistance values with respect to environmental temperature for a multilayer ceramic capacitor with good insulation and poor insulation. As a dielectric material constituting the dielectric substrate of the multilayer ceramic capacitor, a material mainly composed of barium titanate (B characteristic) was used.

図4を参照すると、60℃未満の温度環境下で、積層セラミックコンデンサの両端子電極間の絶縁抵抗を測定しても、積層セラミックコンデンサの絶縁良好品と絶縁不良品との間には、測定抵抗値に充分な有意差が認められないことがわかる。   Referring to FIG. 4, even if the insulation resistance between both terminal electrodes of a multilayer ceramic capacitor is measured under a temperature environment of less than 60 ° C., the measurement is performed between a good insulation product and a poor insulation product of the multilayer ceramic capacitor. It can be seen that there is no significant difference in resistance value.

これに対し、60℃以上の温度環境下で絶縁抵抗の測定を行うと、絶縁良好品と絶縁不良品との間で、測定抵抗値に充分な有意差が生じることがわかる。   On the other hand, when the insulation resistance is measured in a temperature environment of 60 ° C. or higher, it can be seen that there is a sufficiently significant difference in the measured resistance value between the good insulation product and the poor insulation product.

従って、積層セラミックコンデンサ3の研磨及び絶縁抵抗の測定を、60℃以上の温度環境下で行うと、研磨に伴う測定抵抗値の上昇に、充分な有意差を生じさせることが可能となる。測定抵抗値が充分な有意差を伴って上昇するようになると、測定抵抗値の上昇を明確に検出することが可能となり、これにより、絶縁不良層を正確に特定することができる。   Therefore, when the polishing of the multilayer ceramic capacitor 3 and the measurement of the insulation resistance are performed in a temperature environment of 60 ° C. or higher, a sufficiently significant difference can be caused in the increase in the measured resistance value accompanying the polishing. When the measured resistance value rises with a sufficiently significant difference, it is possible to clearly detect an increase in the measured resistance value, thereby accurately identifying a poor insulation layer.

実施例の抵抗測定装置2は、測定抵抗値の上昇を検出したとき、研磨装置1に制御信号を与える。具体的には、抵抗測定装置2は、抵抗測定回路22から研磨装置1の制御回路18、19に制御信号を送り、研磨装置1の動作を停止させる。   The resistance measuring device 2 of the embodiment gives a control signal to the polishing device 1 when detecting an increase in the measured resistance value. Specifically, the resistance measuring apparatus 2 sends a control signal from the resistance measuring circuit 22 to the control circuits 18 and 19 of the polishing apparatus 1 to stop the operation of the polishing apparatus 1.

以上、好ましい実施例を参照して本発明を詳細に説明したが、本発明はこれらに限定されるものではなく、当業者であれば、その基本的技術思想および教示に基づき、種々の変形例を想到できることは自明である。   The present invention has been described in detail with reference to the preferred embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made by those skilled in the art based on the basic technical idea and teachings. It is self-evident that

本発明に係る不良検出方法の適用対象となる積層セラミックコンデンサの一例を示す断面図である。It is sectional drawing which shows an example of the multilayer ceramic capacitor used as the application object of the defect detection method which concerns on this invention. 本発明に係る積層セラミックコンデンサの不良検出方法の実施に用いられる不良検出装置の構成を示す図である。It is a figure which shows the structure of the defect detection apparatus used for implementation of the defect detection method of the multilayer ceramic capacitor which concerns on this invention. 本発明に係る積層セラミックコンデンサの不良検出方法を説明する図である。It is a figure explaining the defect detection method of the multilayer ceramic capacitor which concerns on this invention. 積層セラミックコンデンサの絶縁良好品と絶縁不良品とについて環境温度に対する測定抵抗値を示すデータである。It is data which shows the measured resistance value with respect to environmental temperature about the insulation good product of a multilayer ceramic capacitor, and a poor insulation product.

符号の説明Explanation of symbols

3 積層セラミックコンデンサ
31 誘電体基体
36、37 内部電極
31、32 端子電極

3 Multilayer Ceramic Capacitor 31 Dielectric Substrate 36, 37 Internal Electrode 31, 32 Terminal Electrode

Claims (2)

積層セラミックコンデンサの不良検出方法であって、
前記積層セラミックコンデンサは、誘電体基体の内部に、複数の内部電極を、層状に埋設してあり、前記内部電極は前記誘電体基体の外面に付与された対の端子電極に導通させてあり、
前記積層セラミックコンデンサを、60℃以上の温度環境下におき、
前記積層セラミックコンデンサを、前記内部電極の積層方向に垂直な研磨面を生じるように研磨すると共に前記端子電極間の絶縁抵抗を測定し、測定抵抗値の上昇により絶縁不良を検出するステップを含む
不良検出方法。
A method for detecting defects in a multilayer ceramic capacitor,
In the multilayer ceramic capacitor, a plurality of internal electrodes are embedded in layers inside a dielectric substrate, and the internal electrodes are electrically connected to a pair of terminal electrodes provided on the outer surface of the dielectric substrate,
The multilayer ceramic capacitor is placed in a temperature environment of 60 ° C. or higher,
A defect including steps of polishing the multilayer ceramic capacitor so as to produce a polished surface perpendicular to the stacking direction of the internal electrodes, measuring an insulation resistance between the terminal electrodes, and detecting an insulation failure by increasing a measured resistance value Detection method.
積層セラミックコンデンサの不良検出装置であって、研磨装置と、加熱手段と、抵抗測定装置とを含んでおり、
前記積層セラミックコンデンサは、誘電体基体の内部に、複数の内部電極を、層状に埋設してあり、前記内部電極は前記誘電体基体の外面に付与された対の端子電極に導通させてあり、
前記研磨装置は、前記積層セラミックコンデンサを、前記内部電極の積層方向に垂直な研磨面を生じるように研磨し、
前記加熱手段は、前記積層セラミックコンデンサに60℃以上の温度環境を与え、
前記抵抗測定装置は、前記積層セラミックコンデンサの前記端子電極間の絶縁抵抗を測定する
不良検出装置。


A failure detection device for a multilayer ceramic capacitor, which includes a polishing device, a heating means, and a resistance measurement device,
In the multilayer ceramic capacitor, a plurality of internal electrodes are embedded in layers inside a dielectric substrate, and the internal electrodes are electrically connected to a pair of terminal electrodes provided on the outer surface of the dielectric substrate,
The polishing apparatus polishes the multilayer ceramic capacitor so as to produce a polishing surface perpendicular to the stacking direction of the internal electrodes,
The heating means gives a temperature environment of 60 ° C. or higher to the multilayer ceramic capacitor,
The resistance measurement device is a defect detection device that measures an insulation resistance between the terminal electrodes of the multilayer ceramic capacitor.


JP2003337117A 2003-09-29 2003-09-29 Failure detection method and failure-detecting apparatus of stacked ceramic capacitor Pending JP2005108946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003337117A JP2005108946A (en) 2003-09-29 2003-09-29 Failure detection method and failure-detecting apparatus of stacked ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003337117A JP2005108946A (en) 2003-09-29 2003-09-29 Failure detection method and failure-detecting apparatus of stacked ceramic capacitor

Publications (1)

Publication Number Publication Date
JP2005108946A true JP2005108946A (en) 2005-04-21

Family

ID=34533026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003337117A Pending JP2005108946A (en) 2003-09-29 2003-09-29 Failure detection method and failure-detecting apparatus of stacked ceramic capacitor

Country Status (1)

Country Link
JP (1) JP2005108946A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102253089A (en) * 2011-04-27 2011-11-23 西安交通大学 Method for nondestructively detecting and evaluating mass defect level of high-voltage ceramic capacitors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102253089A (en) * 2011-04-27 2011-11-23 西安交通大学 Method for nondestructively detecting and evaluating mass defect level of high-voltage ceramic capacitors

Similar Documents

Publication Publication Date Title
KR102005274B1 (en) Multi layer ceramic substrate and method of manufacturing the same
TWI624148B (en) Ultrasonic motor, drive control system, optical apparatus, and vibrator
JP5348238B2 (en) Capacitor manufacturing method, capacitor manufacturing apparatus, capacitor manufacturing program, and recording medium
TWI632007B (en) Back-drilling processing method for multilayer printed wiring substrate and processing depth Substrate processing device of control mechanism
JP2000228338A (en) Screening method for multilayer ceramic capacitor
JP2005108946A (en) Failure detection method and failure-detecting apparatus of stacked ceramic capacitor
JP2009135322A (en) Defect detecting method for multilayer electronic component, and method of manufacturing multilayer electronic component
JP2007251150A (en) Piezo-component and method for manufacturing the same and method for determining disposition structure of electrode in component
KR100877041B1 (en) Screening method of multilayer ceramic capacitor
KR101670097B1 (en) System and method for testing an electrostatic chuck
TW202211273A (en) Resonant multilayer ceramic capacitors
JP2008192994A (en) Method of manufacturing electronic component
JPH10293107A (en) Internal defect inspection method for multilayer ceramic capacitor
KR20110048186A (en) Rogowski coil and sensor for measuring current using the same
KR20110109226A (en) Fabrication method of rogowski coil for current sensing and current sensor
Pilgrim et al. Fabrication and characterization of PZT multilayer actuators
WO2010119585A1 (en) Method for detecting amount of processing and processing apparatus
JPH08227826A (en) Method for screening laminated ceramic capacitor
Alam et al. Reliability of embedded planar capacitors under temperature and voltage stress
JP2002168897A (en) Screening method for ceramic electronic part
JP4853316B2 (en) Manufacturing method of electronic parts
JPH08288174A (en) Multilayer ceramic capacitor for high frequency power
CN103650646A (en) Method for verifying correct adhesion of a substrate on an electrically and thermally conductive body
JPH0521933A (en) Thin-film substrate correction device
JP2022089962A (en) Mechanism for detecting abnormal current

Legal Events

Date Code Title Description
A977 Report on retrieval

Effective date: 20060623

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Effective date: 20060628

Free format text: JAPANESE INTERMEDIATE CODE: A131

A02 Decision of refusal

Effective date: 20061025

Free format text: JAPANESE INTERMEDIATE CODE: A02