JP2005094938A - Inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter in which an influence of high frequency noise is eliminated through an inexpensive arrangement, and overcurrent protection is carried out with high detection accuracy such that instantaneous overcurrent is also detected. <P>SOLUTION: A current signal CDET flowing through a power supply unit 20 is detected by means of a current detector 10 and compared with a reference value by an overcurrent detector 50 to produce an overcurrent detection signal. A PWM mask signal being fed to a gate drive circuit 40 as a switching signal and becoming low level for a predetermined time in synchronism with the edge of each PWM control signal (PWMU, PWMV, PWMW) is then produced. Noise included in the overcurrent detection signal is masked by that mask signal before it is fed to the gate drive circuit 40 as an overcurrent detection signal OCDET. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an inverter device that is switched and driven by a pulse width modulation signal using a carrier wave, and more particularly to an inverter device that includes an overcurrent protection device for the purpose of overcurrent protection.

  FIG. 11 shows an inverter device provided with a conventional overcurrent protection device, and its operation will be briefly described. A power supply 20 having a three-phase bridge configuration in which one end (P side) is connected to the DC power supply 1 and the other end (N side) is connected to GND via a current detection resistor (shunt resistor) 100 is a driving circuit. By the switching operation by the control signal from 400, AC power is supplied to the motor 5 to drive it. The current flowing through the power supply 20 is detected from the voltage across the current detection resistor 100.

  The detected current detection signal is filtered by a filter composed of a resistor 61 and a capacitor 62 and then input to the comparison input terminal of the comparator 65, and the reference voltage Vref is applied to the reference input terminal of the comparator 65. , 64 is input. When the filter output exceeds the divided voltage value, the overcurrent protection circuit 70 turns off the lower switching elements (25, 26, 27) and the upper switching elements (21, 22, 23) to shut off the output. Performs current protection. A technique for performing an overcurrent protection operation by filtering a signal detected by a current detection resistor and comparing it with a reference voltage is disclosed in, for example, Patent Document 1.

  FIG. 12 shows still another conventional overcurrent protection device, and its operation will be briefly described. The current flowing through the power supply 20 is detected by the current detection resistor 100 as in the circuit of FIG. The detection signal is input to an S & H (sample and hold) circuit 110, and is sampled and held by a sample and hold signal described later. The sample-and-hold signal is A / D converted by the A / D converter 120. The PWM control circuit 130 outputs a PWM signal that performs switching control of the power supply 20 based on the A / D converted signal, and also outputs a sample hold signal synchronized with the PWM signal to the S & H circuit 110.

The sample hold signal is also output to the error detection circuit 140. The error detection circuit 140 determines whether or not the signal sampled and held in the S & H circuit 110 is erroneously detected. That is, the sample hold process is performed in consideration of the influence of high frequency noise generated by the high frequency switching operation. The overcurrent protection circuit 150 responds to the output of the error detection circuit 140 and performs an overcurrent protection operation when it is determined that an overcurrent occurs. A technique for performing a sample-and-hold process on a signal detected by a current detection resistor (shunt resistor) and performing an overcurrent protection operation in consideration of the influence of high-frequency noise is disclosed in Patent Document 2, for example.
JP 2000-819591 A JP 2002-262579 A

However, the configuration of Patent Document 1 has the following problems.
The current detection signal includes high-frequency noise due to high-frequency switching. In the above-described conventional configuration using a filter, high-frequency noise can be processed by performing filter processing, but instantaneous overcurrent other than noise can be processed. As a result of performing the filtering process, the signal component of the overcurrent cannot be detected from the current detection signal, and there is a concern that the overcurrent detection accuracy may be reduced. Further, additional components such as a resistor and a capacitor constituting the filter are also required. Furthermore, in a protection circuit that performs overcurrent protection by turning off the lower and upper switching elements when overcurrent is detected, recovery from an overcurrent state is slow, and overcurrent protection and normal operation are repeated at high frequencies. However, there is a problem that noise is generated when the switching loss is large and the repeated frequency is in the audible range.

  Further, in the configuration of Patent Document 2 using sample hold, the influence of high frequency noise due to high frequency switching is taken into account by the false detection circuit. However, since the sample hold operation is performed, instantaneous overcurrent other than noise is generated. If it flows, the sample hold will not be in time, and there is a concern that the overcurrent detection accuracy will decrease. Further, a capacitor constituting the sample and hold circuit and a false detection circuit are also required.

  The present invention has been made in view of the above problems, has a simple (inexpensive) configuration, is not affected by high-frequency noise, can detect instantaneous overcurrent with high accuracy, and further speeds up recovery from an overcurrent state. Accordingly, an object of the present invention is to provide an overcurrent protection device that suppresses noise generation by reducing the switching loss and eliminating the repeated operation of the overcurrent protection operation and the normal operation.

  An inverter device according to the present invention includes a power supply comprising a switching element group, a drive circuit for switching the switching element group using a pulse width modulation signal, and a current detector for detecting a current flowing through the power supply. An overcurrent detection circuit for supplying an overcurrent detection signal to the drive circuit for overcurrent protection when a current value detected by the current detector exceeds a reference value, the overcurrent detection circuit comprising: In order to mask the noise included in the overcurrent detection signal using this PWM mask signal, a PWM mask signal having a low level for a predetermined time is generated in synchronization with the edge of each pulse width modulation signal. A logical product signal of the PWM mask signal and the overcurrent detection signal is created, and the logical product signal is supplied to the drive circuit as an overcurrent detection signal.

  When an overcurrent detection signal is input, the drive circuit may turn on one of the upper switching element group and the lower switching element group constituting the power supply and turn off the other (claims). 2).

  The overcurrent detection signal created by the overcurrent detection circuit may be directly input to the drive circuit, but it is provided with latch means for latching the overcurrent detection signal, and the overcurrent detection signal latched by the latch means is You may supply to a drive circuit (Claim 3).

  Latch release means for releasing the latch operation of the latch means may be provided, and the latch operation of the latch means may be released after a predetermined time has elapsed.

  The latch release means may take in a motor speed detection signal and release the latch operation of the latch means in synchronization with the speed detection signal.

  The speed detection signal may be an FG signal indicating a rotation speed of the motor.

  The reference value of the overcurrent may be adjusted by adjusting the reference value by an external input.

  The predetermined time may be adjusted by an external input, and noise generated during switching may be effectively removed (claim 8).

  The overcurrent detection means may output the overcurrent detection signal only when the generated overcurrent detection signal is detected for a predetermined time or a predetermined number of times.

According to the overcurrent protection device of the present invention, an inexpensive configuration is not affected by high-frequency noise, and an instantaneous overcurrent can be detected because a noise removing filter is not used. Furthermore, during overcurrent protection operation, either the upper switching element group or the lower switching element group is turned on, and the other is turned off. Recovery is quicker. Further, since the overcurrent detection signal is latched and output, it is possible to eliminate the repeated operation of the overcurrent protection operation and the normal operation, thereby eliminating the noise generated. Moreover, no noise is generated because the short brake operation is performed during the overcurrent protection operation. In addition, the higher the speed, the faster the recovery from the overcurrent state is caused by the short brake operation, and the latch output is released in synchronization with the speed detection signal, so that the normal operation can be quickly recovered from the overcurrent protection state.
These and other configurations and operations will be described in detail in the description of the embodiments.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIGS. 1 to 4 show diagrams relating to the overcurrent protection device according to Embodiment 1 of the present invention. FIG. 1 shows an overall configuration diagram. A power supply 20 having a three-phase bridge configuration in which one end (P side) is connected to the DC power source 1 and the other end (N side) is connected to the GND via the current detector 10 is supplied from the switching controller 30. Switching driving is performed by the control signals UU, VU, WU, UL, VL, WL, and the AC power is supplied to the motor 5 to drive it. The current flowing through the power supply 20 is detected by the current detector 10.

  The power supply unit 20 includes upper switching elements 21d, 22d, and 23d connected in reverse parallel to the upper switching elements 21, 22, and 23, and lower switching elements 25, 26, and 27, respectively. Are connected to the lower switching element group composed of the lower freewheeling diodes 25d, 26d, and 27d connected in reverse parallel to each other, and the three-phase terminals of the motor 5 are connected to the connection points of the upper switching element group and the lower switching element group, respectively. It is connected. Note that an N-channel field effect transistor may be used as the switch element, and the freewheeling diode may be formed using a parasitic diode.

  The switching controller 30 includes signal wave input terminals 31, 32, 33, a carrier wave input terminal 35, comparators 36, 37, 38, and a gate drive circuit 40. Terminals 31, 32, and 33 receive a three-phase signal wave from a signal wave generation circuit (not shown), and terminal 35 receives a high frequency carrier wave (20 kHz to 200 kHz) from a carrier wave generation circuit (not shown). Comparators 36, 37, and 38 perform pulse width modulation by comparing the signal wave and the carrier wave, output three-phase PWM control signals PWMU, PWMV, and PWMW to the gate drive circuit 40, and also to the overcurrent detector 50. Is also output.

  In response to the three-phase PWM control signals PWMU, PWMV, and PWMW, the gate drive circuit 40 causes each switching element of the power supply 20 to perform a high-frequency switching operation to perform PWM driving. The overcurrent detector 50 detects an overcurrent based on the current detection signal from the current detector 10 and the three-phase PWM control signals PWMU, PWMV, and PWMW, and outputs an overcurrent detection signal OCDET to the gate drive circuit 40. Detailed operation of the overcurrent detector 50 will be described later. In response to the overcurrent detection signal OCDET, the gate drive circuit 40 turns on the upper switching element group of the power supplier 20 and turns off the lower switching element group to perform overcurrent protection.

  Hereinafter, each part will be described in detail. FIG. 2 is a diagram showing a specific configuration of the overcurrent detector 50. The overcurrent detector 50 includes a noise remover 51, a reference voltage Vref, a comparator 52, and an AND circuit 53. The three-phase PWM control signals PWMU, PWMV, and PWMW are input to the noise remover 51 to generate a PWM mask signal PWMMASK for removing the influence of the high frequency noise generated by the high frequency switching operation, and one input of the AND circuit 53 Supply to the department.

  The current detector 10 is configured by a resistor, for example, and detects the total current flowing through the power supply unit 20. The detected current detection signal CDET is input to one input portion (+) of the comparator 52 of the overcurrent detector 50, and the reference voltage Vref is input to the other input portion (−). The comparison output CPOUT of the comparator 52 is input to the other input portion of the AND circuit 53.

  FIG. 3 is a timing chart showing the operation of the noise remover 51. In synchronization with the rising edges of the three-phase PWM control signals PWMU, PWMV, and PWMW obtained by comparing the three-phase signal wave with the high-frequency carrier wave, the mask signals PWMUM, PWMVM, and PWMWM that are set to the “L” level for a predetermined time Ta are output. . The PWM mask signal PWMMASK is a signal obtained by ANDing these mask signals. That is, the PWM mask signal PWMMASK is a signal that is masked for a predetermined time Ta from each edge of the three-phase PWM control signals PWMU, PWMV, and PWMW.

  FIG. 4 is a timing chart showing the operation of each part of the overcurrent detector 50. The current detection signal CDET is a signal as shown in FIG. 4 and includes a whisker-like noise generated by high-frequency switching or a ringing as shown in a broken-line circle.

  The peak of the current detection signal CDET becomes the peak of the total current flowing through the current supplier 20. That is, a current having a value obtained by dividing the peak value of the current detection signal CDET by the resistance value of the current detector 10 flows through the power supply 20.

  Therefore, by monitoring the peak value of the current detection signal CDET, it is possible to detect the overcurrent flowing through the power supplier 20. Therefore, the reference voltage Vref is set to a voltage value calculated from the level of the overcurrent to be detected and the resistance value of the current detector 10, and the comparator 52 compares the current detection signal CDET with the reference voltage Vref to thereby detect the overcurrent. Can be detected.

  However, if the overcurrent is determined based on the comparator output CPOUT which is simply compared by the comparator 52, false detection occurs due to whiskers due to high frequency noise. Since the whisker-like noise is output in synchronization with the ON timing of the PWM control signals PWMU, PWMV, and PWMW, if the predetermined time Ta is set to a time that can mask the whisker-like noise and ringing, the PWM The mask signal PWMMASK can remove whiskers and ringing.

  The whisker-like noise is also output at the OFF timing of the PWM control signals PWMU, PWMV, and PWMW, and may be masked against the edge falling timing of the control signal.

  For this purpose, the AND circuit 53 performs a logical product of the comparator output CPOUT and the PWM mask signal PWMMASK of the noise remover 51, thereby obtaining an overcurrent detection signal OCDET that eliminates the influence of high frequency noise.

  As described above, the current detection signal is directly compared with the reference voltage Vref without performing the filtering process, and the overcurrent detection is performed while removing the influence of the high frequency noise by the PWM mask signal PWMMASK. Even when it flows, the overcurrent can be detected. Furthermore, since no filter, sample hold circuit or the like is used, the configuration is simplified, and an inexpensive overcurrent protection device can be provided.

  The overcurrent detection signal OCDET is input to the gate drive circuit 40 and performs an overcurrent protection operation for each switch element of the power supply device 20. Specifically, when the overcurrent detection signal becomes “H” level, all the lower switching element groups of the power supply device 20 are turned off and all the upper switching element groups are turned on. By doing so, a so-called short brake operation is performed, and power is actively consumed, so that it is possible to quickly recover from the overcurrent state.

  As described above, the current detector 10 detects the total current flowing through the power supplier 20, the overcurrent detector 50 compares the current detection signal CDET with the reference voltage Vref, and further affects the influence of high frequency noise. High-frequency noise is masked by the PWM mask signal PWMMASK for removal, and is output to the gate drive circuit 40 as the overcurrent detection signal OCDET. The gate drive circuit 40 performs an overcurrent protection operation by controlling each switch element of the power supplier 20 to perform a short brake operation according to the overcurrent detection signal OCDET. With this configuration, instantaneous overcurrent can also be detected, and overcurrent protection is performed as a short brake operation in consideration of the effects of high-frequency noise with a simple configuration. Recover.

  In the first embodiment, the current detector 10 is connected between the power supply 20 and GND, and when the overcurrent protection is performed, all the lower switching elements of the power supply 20 are turned off, The overcurrent protection operation was performed as a short brake operation for turning on all the upper side switching elements. However, when the current detector 10 is connected between the DC power source 1 and the power supply 20 and the overcurrent protection is performed, the power The overcurrent protection operation may be performed as a short brake operation in which all the upper side switching element groups of the supplier 20 are turned off and all the lower side switching element groups are turned on. Although recovery from the overcurrent state is delayed, the upper and lower switching element groups may be simultaneously turned on as in the conventional example.

  The reference voltage Vref may be operated to be adjustable by an external input, for example, and the predetermined time Ta of the PWM mask signal PWMMASK may be operated to be adjustable by an external input. However, the predetermined time Ta must be set within a range in which the influence of high frequency noise can be removed. Although the current detector 10 has been described as a resistor, the same effect can be obtained when a current sensor or the like is used, and various changes and modifications can be made without changing the spirit of the present invention. It goes without saying that such a configuration is also included in the present invention.

(Embodiment 2)
5 to 7 show diagrams relating to the overcurrent protection device according to the second embodiment of the present invention. FIG. 5 shows an overall configuration diagram. The difference from FIG. 1 is that an overcurrent detector 50A that outputs a latch signal PROTECT1 is employed in FIG. 5 instead of the overcurrent detector 50 that outputs an overcurrent detection signal OCDET.

  FIG. 6 shows a specific configuration of the overcurrent detector 50A. This overcurrent detector 50A has a configuration in which a latch circuit 54 is added to the output part of the AND circuit 53 in the overcurrent detector 50 of FIG. In addition, since the thing of the same code | symbol as Embodiment 1 of this invention performs the same operation | movement as Embodiment 1 of this invention, description here is abbreviate | omitted.

  FIG. 7 shows a timing chart of the latch circuit 54. The overcurrent detection signal OCDET that is the output of the AND circuit 53 is input to the latch circuit 54. The latch circuit 54 latches the overcurrent detection signal OCDET and outputs a latch signal PROTECT1. When the overcurrent is detected by the overcurrent detection signal OCDET, the latch circuit 54 outputs the latch signal PROTECT1 in synchronization with the rising edge of the overcurrent detection signal OCDET. The latch signal PROTECT1 is input to the gate drive circuit 40, responds to the latch signal PROTECT1, turns off all lower switching element groups of the power supply device 20 as in the first embodiment of the present invention, and turns all upper switching element groups on. Turns on and performs overcurrent protection as a short brake operation.

  In this way, if the overcurrent detection signal OCDET is latched and output by the latch circuit 54, the repeated operation of the overcurrent protection operation and the normal operation (overcurrent protection operation release) is eliminated. I can do it. Further, since unnecessary switching is not repeated, power consumption due to switching loss can be suppressed. Furthermore, it is possible to suppress noise generated when an overcurrent protection operation and a release operation are repeatedly performed in the audible region. At that time, since the overcurrent protection operation performs a so-called short brake operation, no noise is generated. The latch circuit 54 can be released by performing a reset operation after a reliable overcurrent protection operation is performed.

  Further, as shown in FIG. 7C, the latch operation may be performed after the latch timing of the overcurrent detection signal OCDET is counted several times instead of the first rising edge of the overcurrent detection signal OCDET. Although the overcurrent detection signal OCDET masks the influence of high-frequency noise by the PWM mask signal PWMMASK, it can be considered that it includes erroneous detection due to some noise. Therefore, it is possible to prevent malfunction of the overcurrent protection operation due to erroneous detection by latching and outputting the overcurrent detection signal OCDET after counting it several times.

  Further, as shown in FIGS. 7D and 7E, latch output may be performed only when the overcurrent detection signal OCDET continues for a predetermined time Td. With this configuration, it is possible to reliably determine an overcurrent that is not erroneous detection due to noise or the like, and it is possible to reliably perform an overcurrent protection operation. In addition, various changes and modifications can be made without changing the gist of the present invention, and it goes without saying that such a configuration is also included in the present invention.

(Embodiment 3)
8 to 10 show diagrams relating to the overcurrent protection device according to Embodiment 3 of the present invention. FIG. 8 shows an overall configuration diagram. The difference from FIG. 5 is that, instead of the overcurrent detector 50A that outputs the latch signal PROTECT1, in FIG. 8, an overcurrent detector 50B that outputs the latch signal PROTECT2 is provided.

  FIG. 9 shows a specific configuration of the overcurrent detector 50B. This overcurrent detector 50B has a configuration in which a latch release circuit 54 is added to the output part of the latch circuit 54 in the overcurrent detector 50A of FIG. 6 and a terminal 56 for inputting a latch release signal is provided. . In addition, since the thing of the same code | symbol as Embodiment 2 of this invention performs the same operation | movement as Embodiment 2 of this invention, description here is abbreviate | omitted.

  A latch signal PROTECT1, which is an output of the latch circuit 54, is input to the latch release circuit 55. The latch release circuit 55 performs the latch release operation of the latch signal PROTECT1 by the latch release signal input from the terminal 56, and outputs the latch release signal PROTECT2. The latch release signal PROTECT2 is input to the gate drive circuit 40, and responds to the latch release signal PROTECT2, and the lower switching element group of the power supplier 20 as in the first embodiment or the second embodiment of the present invention. Are turned off and the overcurrent protection operation is performed as a short brake operation in which all the upper switching elements are turned on.

  According to this configuration, since the repeated operation of the overcurrent protection operation and the normal operation (overcurrent protection operation release) is eliminated until the latch release signal is input, a reliable overcurrent protection operation can be performed. Further, since unnecessary switching is not repeated, power consumption due to switching loss can be suppressed. Furthermore, it is possible to suppress noise generated when an overcurrent protection operation and a release operation are repeatedly performed in the audible region. At this time, since the overcurrent protection operation performs a short brake operation, no noise is generated.

  FIG. 10 shows a timing chart of the latch release circuit 55. FIG. 10 shows an example in which an FG signal indicating the rotation speed of the motor 5 is used as the latch release signal. The latch release signal PROTECT2 in (c) releases the latch signal PROTECT1 after the edge count of the FG signal a predetermined number of times.

  Thus, when the latch release operation is performed in synchronization with the FG signal, there are the following advantages. During the overcurrent protection operation by the short brake operation, the higher the rotation speed of the motor 5, the more power is consumed, and the recovery from the overcurrent state is faster. Therefore, if the latch release operation is performed in synchronization with the FG signal, the latch release operation can be performed faster as the rotation speed is higher, and the latch release operation can be performed later as the rotation speed is slower. That is, it is possible to eliminate the state in which the overcurrent protection operation is continued despite the recovery from the overcurrent state.

  Further, as shown in (d), the latch release operation may be performed after a predetermined time Tt from the latch operation. In this case, it is better to perform the predetermined time for the latch release operation at a frequency outside the audible range.

  Furthermore, although the description has been given using the FG signal as the latch release signal, a speed detection circuit for detecting the rotation speed of the motor 5 may be configured, and the latch release may be performed by the detected speed detection signal. The latch release signal is not limited to the above description, and may be configured to be released by an external input, or other control signals may be used instead of the FG signal.

  In addition, various changes and modifications can be made without changing the gist of the present invention, and it goes without saying that such a configuration is also included in the present invention.

It is a figure which shows the whole structure in Embodiment 1 of this invention. It is a circuit block diagram of the overcurrent detector of FIG. FIG. 3 is a timing diagram for explaining the operation of each unit in the noise eliminator of FIG. 2. FIG. 2 is a timing diagram for explaining the operation of each unit in the overcurrent detector of FIG. 1. It is a figure which shows the whole structure in Embodiment 2 of this invention. It is a circuit block diagram of the overcurrent detector of FIG. FIG. 7 is a timing chart for explaining the operation of each part in the latch circuit of FIG. 6. It is a figure which shows the whole structure in Embodiment 3 of this invention. It is a circuit block diagram of the overcurrent detector of FIG. FIG. 9 is another timing chart for explaining the operation of each part in the latch release circuit of FIG. 8. It is a figure which shows the whole structure in the conventional overcurrent protection apparatus. It is a figure which shows the whole structure in another conventional overcurrent protection apparatus.

Explanation of symbols

1: DC power supply 5: Motor 10: Current detector 20: Power supply 30: Switching controller 36, 37, 38: Comparator 40: Gate drive circuit 50, 50A, 50B: Overcurrent detector 70: Overcurrent protection Circuit 100: Current detection resistor 110: S & H circuit 120: A / D converter 130: PWM control circuit 140: Error detection circuit 150: Overcurrent protection circuit 400: Drive circuit

Claims (9)

A power supply comprising a switching element group; a drive circuit for switching and driving the switching element group using a pulse width modulation signal; a current detector for detecting a current flowing through the power supply; and a detection by the current detector An overcurrent detection circuit for supplying an overcurrent detection signal to the drive circuit for overcurrent protection when the current value exceeds a reference value;
The overcurrent detection circuit creates a PWM mask signal that is at a low level for a predetermined time in synchronization with the edge of each pulse width modulation signal, and outputs a logical product signal of the PWM mask signal and the overcurrent detection signal, An inverter device, characterized in that it is supplied to the drive circuit as an overcurrent detection signal.   2. The drive circuit according to claim 1, wherein an input of an overcurrent detection signal turns on one of an upper switching element group and a lower switching element group constituting the power supply and turns off the other. The inverter device described in 1.   The inverter device according to claim 1, further comprising a latch unit that latches an overcurrent detection signal created by the overcurrent detection circuit, and that supplies the overcurrent detection signal latched by the latch unit to the drive circuit.   4. The inverter device according to claim 3, further comprising latch release means for releasing the latch operation of the latch means, wherein the latch operation of the latch means is released after a lapse of a predetermined time.   The inverter device according to claim 4, wherein the latch release unit takes in a motor speed detection signal and releases the latch operation of the latch unit in synchronization with the speed detection signal.   The inverter device according to claim 5, wherein the speed detection signal is an FG signal.   The inverter device according to claim 1, wherein the reference value can be adjusted by an external input.   The inverter device according to claim 1, wherein the predetermined time can be adjusted by an external input. 9. The overcurrent detection unit outputs the overcurrent detection signal only when the generated overcurrent detection signal is detected for a predetermined time or a predetermined number of times. Inverter device.

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