JP2005092467A - Processor and interrupt control method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute safe interrupt handling in a processor highly responsively. <P>SOLUTION: Upon an external interrupt during the processing of a vector instruction, the processor 1 holds external interrupt handling until finishing the vector instruction processing. The external interrupt handling is executed after the vector instruction processing in progress is finished. This can prevent the situation wherein interrupt handling causes incorrect values of a vector instruction computation result to enable the safe execution of interrupt handling. A vector instruction execution detection part 109 implemented as hardware in the processor 1 detects whether a vector instruction is processed or not, and according to the detection result, the execution of interrupt handling is controlled. This can provide higher processing responsiveness than the software control of interrupt handling. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a processor that performs interrupt processing and an interrupt control method thereof.

Conventionally, interrupt processing is performed in a processor capable of executing an instruction over a plurality of cycles such as a vector instruction and a multi-cycle instruction.
Such interrupt processing includes external interrupt processing input from outside the processor and exception processing that occurs inside the processor.
FIG. 12 is a diagram showing a configuration of a conventional processor 200 capable of executing interrupt processing.

In FIG. 12, a processor 200 includes a fetch unit 201, a decode unit 202, an ALU (Arithmetic and Logical Unit) unit 203, a multiplication unit 204, an addition / subtraction unit 205, a load unit 206, a store unit 207, and a register. A file unit 208, a program control unit 209, an exception management unit 210, and an external interrupt control unit 211 are configured.
The fetch unit 201 fetches an instruction code from a memory (not shown). The fetch unit 201 temporarily stores the fetched instruction code, and then outputs the instruction code to the decoding unit 202.

The decoding unit 202 decodes the instruction code input from the fetch unit 201 and outputs the decoding result to the ALU unit 203, the multiplication unit 204, the addition / subtraction unit 205, the load unit 206, and the store unit 207. Similarly, the decoding unit 202 outputs the decoding result to the program control unit 209.
When the decoding result input from the decoding unit 202 is a logical operation, the ALU unit 203 reads data to be calculated from the register file unit 208 based on the decoding result. Then, the ALU unit 203 performs a logical operation on the read data and outputs the operation result to the register file unit 208.

When the decoding result input from the decoding unit 202 is multiplication, the multiplication unit 204 reads data to be multiplied from the register file unit 208 based on the decoding result. Then, the multiplication unit 204 performs multiplication of the read data and outputs the multiplication result to the register file unit 208.
The addition / subtraction unit 205 reads data to be added or subtracted from the register file unit 208 based on the decoding result when the decoding result input from the decoding unit 202 is addition or subtraction. Then, the addition / subtraction unit 205 performs addition or subtraction of the read data, and outputs the addition / subtraction result to the register file unit 208.

When the decoding result input from the decoding unit 202 is a load instruction, the load unit 206 outputs an address that is a target of the load instruction to the memory based on the decoding result. Then, when the data at the address is input from the memory, the load unit 206 outputs the input data to the register file unit 208.
When the decoding result input from the decoding unit 202 is a store instruction, the store unit 207 reads data that is the target of the store instruction from the register file unit 208 based on the decoding result. Then, the store unit 207 outputs the address that is the target of the store instruction and the data read from the register file unit 208 to the memory.

  The register file unit 208 includes a predetermined number of scalar registers and vector registers, and stores data to be operated by the ALU unit 203, the multiplication unit 204, the addition / subtraction unit 205, the load unit 206, and the store unit 207. Further, a control signal for reading or writing data is input from the program control unit 209 to the register file unit 208.

The program control unit 209 controls the entire processor 200, and includes a program counter 209a, a status register 209b, an interrupt processing program counter 209c, and an interrupt vector 209d.
The program counter (PC) 209a is a register that stores an address of a program to be executed next.

  The status register (ST) 209b stores data related to the operating state of the processor 200. For example, the status register 209b saves an interrupt permission flag (MIE) indicating whether or not interrupt processing is permitted, and an interrupt permission flag that stores an interrupt permission flag before the occurrence of interrupt processing when the interrupt processing occurs. The flag (PMIE) is stored.

The interrupt processing program counter (EPC) 209c is a register for saving an address stored in the program counter 209a when interrupt processing occurs.
The interrupt vector 209d stores a branch destination program address corresponding to the type of interrupt processing in a table format.

With this configuration, the program control unit 209 controls the reading or writing of data in the register file unit 208 based on the decoding result input from the decoding unit 202, or stores the program to be executed next. Or output to memory.
In addition, the program control unit 209 outputs a signal indicating the calculation contents of the processor 200 to the exception management unit 210, and executes an interrupt process when a signal indicating exception processing is input from the exception management unit 210.

Further, the program control unit 209 outputs a signal indicating the operation state of the processor to the external interrupt control unit 211. Further, the program control unit 209 executes interrupt processing if an interrupt processing factor and an interrupt level are input from the external interrupt control unit 211 and the external control unit 209 is in an operating state capable of executing external interrupts.
Based on the signal indicating the calculation contents input from the program control unit 209, the exception management unit 210 performs an address exception (violation of the address reference range) and a reserved instruction exception (input of an undefined instruction) in the calculation. And whether or not an internal exception such as division by zero has occurred. Then, when an internal exception occurs, the exception management unit 210 outputs a signal indicating exception processing corresponding to the generated internal exception to the program control unit 209.

The external interrupt control unit 211 receives an external interrupt request signal input from various devices connected to the processor 200. Then, the external interrupt control unit 211 outputs the interrupt processing factor and the interrupt level to the program control unit 209 based on the received external interrupt request signal.
In the configuration as described above, when an interrupt process such as an exception process or an external interrupt occurs, the processor 200 temporarily saves data related to the instruction being executed and executes the interrupt process as shown in FIG. Specifically, in FIG. 13, when an interrupt process occurs during execution of a normal program, the processor 200 sets an interrupt permission flag (MIE) in the save permission flag (PMIE), and the interrupt permission flag includes Set “0” to indicate that interrupt is prohibited. Further, the processor 200 sets the value of the program counter 209a in the interrupt processing program counter 209c, and sets an address indicating an interrupt processing instruction in the program counter 209a.

  Then, the processor 200 executes the interrupt process, and thereafter restores the saved data, and continues the process that was being executed before the occurrence of the interrupt process. That is, the value of the save enable flag is returned to the interrupt enable flag, and the address saved in the interrupt processing program counter 209c is returned to the program counter 209a. Then, the operation before the interrupt process is resumed.

Here, if an interrupt process occurs while executing a process that requires multiple cycles until an execution result is obtained, such as a vector instruction or a multi-cycle instruction, after the interrupt process is executed, before the interrupt process occurs The process that was being executed could not continue properly.
For example, it is assumed that an interrupt process occurs during execution of a process of writing the operation result of a vector instruction to a scalar register and storing the operation result in order.

  At this time, if no interrupt processing occurs, the operation result written to the scalar register is stored for each cycle, and appropriate vector data is obtained. On the other hand, when interrupt processing occurs, the operation results in the scalar register change sequentially during execution of interrupt processing, and after execution of interrupt processing, the last operation result of the vector instruction is stored in the scalar register. It becomes a state. Then, the calculation result is stored as the calculation result of the vector instruction for each cycle. For this reason, when interrupt processing occurs, all the data stored after the interrupt processing occurs have the same value (the last calculation result), and appropriate vector data cannot be obtained.

In order to solve such a problem, a technique described in a reference document “Structured computer configuration 4th edition” (Pearson Education, written by Andrew S. Tannenbaum) is known.
This document discloses a technique for preventing the above-described incorrect result from occurring by prohibiting execution of interrupt processing by software.
Andrew S. Tannenbaum "Structured Computer Configuration 4th Edition" Pearson Education

However, in the technique described in the above-mentioned document, it is possible to prevent an illegal result from being generated in interrupt processing (safe interrupt processing can be executed safely), but interrupt processing is controlled by software. There arises a problem that the response speed in controlling the execution of is reduced.
That is, in the conventional processor, it is difficult to safely execute interrupt processing with high responsiveness.

  An object of the present invention is to safely execute interrupt processing in a processor with high responsiveness.

In order to solve the above problems, the present invention provides:
A processor capable of processing a vector instruction or a multi-cycle instruction and capable of executing an interrupt process during the process, and detecting whether or not the vector instruction or the multi-cycle instruction is being processed (for example, The vector instruction execution detecting unit 109 in FIGS. 1 and 8 or the multi-cycle instruction execution detecting unit 113 in FIGS. 5 and 11 and the execution detecting unit are processing the vector instruction or multi-cycle instruction. Interrupt control means (for example, program control in FIG. 1, FIG. 5, FIG. 8 or FIG. 11) that, if detected, can suspend execution of interrupt processing until the processing of the vector instruction or multi-cycle instruction is completed. Part 110).

The present invention also provides:
An interrupt control method in a processor capable of processing a vector instruction or a multi-cycle instruction and executing an interrupt process during the processing, and detecting whether the vector instruction or the multi-cycle instruction is being processed When it is detected in the detection step and the execution detection step that the vector instruction or multicycle instruction is being processed, the execution of the interrupt process is suspended until the processing of the vector instruction or multicycle instruction is completed. And an interrupt control step.

As a result, when an interrupt occurs during the processing of a vector instruction or multicycle instruction, the interrupt processing is suspended until the processing of the vector instruction or multicycle instruction is completed. When the processing of the vector instruction or multicycle instruction being processed is completed, the interrupt process is executed.
Therefore, by performing the interrupt process, it is possible to prevent a situation in which the operation result of the vector instruction becomes an illegal value, and it is possible to execute the interrupt process safely.

This also detects whether or not a vector instruction or multi-cycle instruction is being processed by the execution detection means (or execution detection step) implemented in the processor, and based on the detection result, interrupt processing is performed. Execution is controlled.
Therefore, it is possible to perform processing with higher responsiveness than when interrupt processing is controlled by software.

That is, according to the present invention, it is possible to safely execute interrupt processing in a processor with high responsiveness.
Further, continuous execution detecting means for detecting whether the instruction following the vector instruction or multicycle instruction being processed is a vector instruction or multicycle instruction (for example, the vector instruction continuous execution detecting unit 109a in FIG. 8 or 11 further includes a multi-cycle instruction continuous execution detecting unit 113a), wherein the interrupt control means receives a vector instruction or a multi-cycle instruction following the vector instruction or multi-cycle instruction being processed by the continuous execution detecting means. When it is detected that the instruction is an instruction, it is possible to suspend execution of the interrupt process until the processing of the vector instruction or multicycle instruction being processed and the subsequent instruction are completed. It is a feature.

  Further, it further includes a continuous execution detecting step for detecting whether an instruction subsequent to the vector instruction or multi-cycle instruction being processed is a vector instruction or a multi-cycle instruction. In the interrupt control step, When it is detected that an instruction subsequent to the vector instruction or multi-cycle instruction is a vector instruction or multi-cycle instruction; It is characterized in that execution of interrupt processing is suspended until the process ends.

As a result, when an interrupt occurs during processing of a vector instruction or multicycle instruction, the interrupt processing is suspended until the vector instruction or multicycle instruction is not being continuously executed. When the vector instruction or the multi-cycle instruction is not being continuously executed, the interrupt process is executed.
Therefore, even when consecutive vector instructions or multi-cycle instructions share a register, it is possible to prevent a situation in which the operation result of a vector instruction becomes an illegal value more reliably and to interrupt safely. Processing can be executed.

  Also, determination means for determining the dependency relationship between the data related to the vector instruction or multi-cycle instruction being processed and the data related to the subsequent instruction (for example, in the case of having a function of checking the data dependency relationship) 1 and FIG. 8 or the multi-cycle instruction execution detection unit 113 in FIG. 5 and FIG. 11, and the interrupt control means is determined by the determination means to have the dependency. In such a case, the execution of the interrupt process is suspended, and the interrupt process is executed when it is determined that there is no dependency.

  The method further includes a determination step of determining a dependency relationship between the data related to the vector instruction or multicycle instruction being processed and the data related to the subsequent instruction. In the interrupt control step, the dependency relationship is If it is determined that there is an interrupt process, the interrupt process is suspended, and if it is determined that there is no dependency, the interrupt process is executed.

As a result, it is possible to prevent a situation in which the holding time until the interrupt process is executed becomes long.
The determining means determines the dependency relationship based on a relationship between a destination register of a vector instruction or multi-cycle instruction being processed and a source register of a subsequent instruction.

In the determination step, the dependency relationship is determined based on the relationship between the destination register of the vector instruction or multicycle instruction being processed and the source register of the subsequent instruction.
This makes it possible to appropriately execute interrupt processing according to the specific processing contents of successive vector instructions or multicycle instructions.

  In addition, for example, when the execution result of a vector instruction is a relationship that a subsequent instruction uses through a scalar register or a relationship in which multiple assignments of a register are performed to a destination register of a preceding instruction Can be said to be related to the destination register of the vector instruction or multi-cycle instruction being processed and the source register of the subsequent instruction.

Hereinafter, an embodiment of a processor according to the present invention will be described with reference to the drawings.
(First embodiment)
First, a first embodiment of the present invention will be described.
First, the configuration will be described.
FIG. 1 is a diagram showing a configuration of the processor 1 according to the present embodiment.

In FIG. 1, a processor 1 includes a fetch unit 101, a decode unit 102, an ALU unit 103, a multiplication unit 104, an addition / subtraction unit 105, a load unit 106, a store unit 107, a register file unit 108, a vector The instruction execution detection unit 109, the program control unit 110, the exception management unit 111, and the external interrupt control unit 112 are included.
In FIG. 1, the processor 1 has a configuration in which a vector instruction execution detection unit 109 is added to the conventional processor 200 shown in FIG. Therefore, only the configuration related to the vector instruction execution detection unit 109 will be described, and the description of the same configuration as the conventional one will be omitted.

The ALU unit 103, the multiplication unit 104, the addition / subtraction unit 105, the load unit 106, and the store unit 107 each output an execution status signal indicating whether or not the instruction being executed is a vector instruction to the vector instruction execution detection unit 109 To do.
The vector instruction execution detection unit 109 is provided as hardware in the processor 1. The vector instruction execution detection unit 109 includes an ALU unit 103 that executes instructions, a multiplication unit 104, an addition / subtraction unit 105, and a load unit 106. An execution status signal is input from the store unit 107.

When the execution status signal indicating that the instruction being executed is a vector instruction is input, the vector instruction execution detection unit 109 receives an instruction signal (hereinafter referred to as “interrupt disable signal”) indicating that external interrupt processing is not to be executed. Is output to the program control unit 110.
Since it can be determined whether or not the instruction is a vector instruction based on the content of the instruction code decoded by the decoding unit 102, an execution status signal is input from the decoding unit 102 to the vector instruction execution detection unit 109. Is also possible.

When an interrupt prohibition signal is input from the vector instruction execution detection unit 109, the program control unit 110 suspends execution of external interrupt processing until the processing of the currently executing vector instruction is completed. Then, the program control unit 110 executes external interrupt processing when the processing of the currently executing vector instruction is completed.
Next, the operation will be described.

The processor 1 performs state transition corresponding to the operation of interrupt processing mainly under the control of the program control unit 110.
FIG. 2 is a state transition diagram showing the operation of the processor 1.
In FIG. 2, the processor 1 transitions between states S1 to S5.
The state S1 (Reset) is a state in which the first cycle is executed when the processor 1 is reset as an interrupt process, and the state continues to transition to the state S2.

  State S2 (Normal) is a normal operating state in which no interrupt has occurred. In the state S2, when an external interrupt occurs (MI-Event), if a vector instruction is not being executed, the state transitions to the state S3. When an interrupt other than an external interrupt such as exception handling occurs (NMI-Event), the state S5 Transition to. Further, when the reset is performed in the state S2 (IntReset), the state transits to the state S1. Here, in the state S2, when an external interrupt occurs and the vector instruction is being processed, the state S2 is continued until the processing of the vector instruction is completed.

State S3 (MI) is a state in which external interrupt processing is executed. In the state S3, when the external interrupt process ends, the state transits to the state S4, and when the reset is performed, the state transits to the state S1.
State S4 (MI-PostProc) is a state in which the operation timing of the processor 1 is adjusted after execution of the external interrupt process. In state S4, after adjusting the operation timing, the state transitions to state S2, and when an interrupt other than an external interrupt occurs, the state transitions to state S5. Moreover, when reset is performed in state S4, it changes to state S1.

State S5 (NMI) is a state in which interrupt processing other than external interrupt, such as exception processing, is executed. In state S5, after executing interrupt processing other than external interrupt, the state transitions to state S2, and when reset is performed, the state transitions to state S1.
As a result of the transition of each state as shown in FIG. 2, the processor 1 specifically performs the following operation regarding the interrupt processing.

FIG. 3 is a timing chart showing an operation example when an external interrupt occurs during processing of a vector instruction.
In FIG. 3, instruction codes (Inst 1 to 11) are sequentially input every cycle defined by the clock signal (CLK). Each instruction code is composed of stages of fetch address calculation (Fadr), fetch (F), decode (D), and execution (E). The instruction code Inst2 is a vector instruction for reading data of 4 words, and the execution stage extends over 4 cycles (E1 to E4).

3, in cycles “1” to “3”, instruction codes Inst1 to Inst3 are sequentially input to the processor 1 to perform normal operations.
Then, in cycle “4”, when an external interrupt occurs (IRQ-EN = 1), since the instruction code Inst2 which is a vector instruction is being processed, external interrupt processing is suspended and the last execution of the instruction code Inst2 Normal operation continues until cycle “8” when the stage is started.

In cycle “8”, the processor 1 starts the external interrupt process Inst8 and calculates the fetch address of the external interrupt process. In addition, the operation state including the value of the program counter (PC) in the cycle “7” is temporarily saved.
Then, the processor 1 processes the instruction codes Inst8 to 10 related to the external interrupt processing in the cycles “8” to “10”, and returns to the normal operation state from the cycle “11”.

As described above, when an external interrupt occurs during the processing of a vector instruction, the processor 1 according to the present embodiment suspends the external interrupt processing until the processing of the vector instruction ends as shown in FIG. To do. When the processing of the vector instruction being processed ends, external interrupt processing is executed.
Therefore, by performing the interrupt process, it is possible to prevent a situation in which the operation result of the vector instruction becomes an illegal value, and it is possible to execute the interrupt process safely.

Further, the processor 1 detects whether or not vector instruction processing is being performed by the vector instruction execution detection unit 109 implemented as hardware in the processor 1, and executes interrupt processing based on the detection result. Control.
Therefore, it is possible to perform processing with higher responsiveness than when interrupt processing is controlled by software. In addition, when describing a program to be executed by the processor 1, it is possible to easily describe a program related to interrupt processing and to prevent a program error related to interrupt processing.

Even when the processor 1 processes a multi-cycle instruction, it is possible to perform the same interrupt processing control as in the case of a vector instruction as described above.
That is, as shown in FIG. 5, the processor 1 includes a multi-cycle instruction execution detection unit 113 corresponding to the vector instruction execution detection unit 109 of FIG. An execution status signal indicating whether or not the instruction is being executed is input.

When an execution status signal indicating that the instruction being executed is a multi-cycle instruction is input from each functional unit such as the ALU unit 103, the multi-cycle instruction execution detection unit 113 sends an interrupt prohibition signal to the program control unit. To 110.
With such a configuration, the processor 2 specifically performs the following operation regarding the interrupt processing.

FIG. 6 is a timing chart showing an operation example when an interrupt process occurs during the processing of a multi-cycle instruction.
In FIG. 6, every cycle defined by the clock signal (CLK),
MP% SR2,% SR0,% SR1;
ADD% SR4,% SR3,% SR2;
SUB% SR5,% SR3,% SR2;
ADD% SR7,% SR6,% SR2;
SUB% SR8,% SR6,% SR2;
Instructions are entered in the order.
(However, the first line is an instruction that multiplies the values of the scalar register SR0 and the scalar register SR1 and stores the result in the scalar register SR2. The second line adds the value of the scalar register SR2 to the value of the scalar register SR3. The third line is an instruction for subtracting the value of the scalar register SR2 from the value of the scalar register SR3 and storing it in the scalar register SR5, and the fourth line is the instruction for storing the scalar register SR4. An instruction for adding the value of the scalar register SR2 to the value of SR6 and storing it in the scalar register SR7 Further, the fifth line subtracts the value of the scalar register SR2 from the value of the scalar register SR6 and stores it in the scalar register SR8. Is an instruction to do.)
In these instructions, the first line is a multi-cycle instruction whose execution stage extends over four cycles, and the destination register SR2 is multiple-assigned as a source register in the instructions from the second line to the fourth line. .

Here, when external interrupt processing occurs in cycle “4”, the multi-cycle instruction (instruction on the first line) is being processed, so external interrupt processing is suspended and the last execution stage of the multi-cycle instruction is Normal operation continues until cycle "7" to be started.
Then, in the cycle “7”, the processor 2 starts external interrupt processing.
Therefore, the value of the scalar register SR2 used in the second to fourth line instructions does not reflect the execution result of the first line instruction, and the value of the scalar register SR2 used in the fifth line instruction is not reflected. The value is a state in which the execution result of the instruction on the first line is reflected. That is, the multiple assignment related to the scalar register SR2 is appropriately processed.

On the other hand, when executing external interrupt processing regardless of whether or not a multi-cycle instruction is being processed as in the prior art, as shown in FIG. 7, the scalars used in the second to fourth line instructions are used. The value of the register SR2 is also in a state in which the execution result of the instruction on the first line is reflected, and the multiple assignment relating to the scalar register SR2 is not appropriately processed.
Therefore, as in the case of the vector instruction described above, the present invention can solve the problem caused by the external interrupt processing being performed during the processing of the multi-cycle instruction.
(Second Embodiment)
Next, a second embodiment of the present invention will be described.

FIG. 8 is a diagram showing a configuration of the processor 2 according to the present embodiment.
In FIG. 8, the processor 2 has a configuration in which a vector instruction continuous execution detection unit 109 a is added to the vector instruction execution detection unit 109 in the processor 1 in the first embodiment. Therefore, only the configuration related to the vector instruction continuous execution detection unit 109a will be described, and the description of the same components as the processor 1 will be omitted.

  The decoding unit 102 determines whether or not the instruction code is a vector instruction based on a decoding result of an instruction code subsequent to the instruction code currently being executed (hereinafter referred to as “subsequent instruction code”). Then, the decoding unit 102 outputs a continuous execution status signal indicating whether or not an instruction subsequent to the instruction code currently being executed (hereinafter referred to as “subsequent instruction”) is a vector instruction, to the vector instruction continuous execution detecting unit 109a. Output to.

The vector instruction execution detection unit 109 further includes a vector instruction continuous execution detection unit 109a.
Based on the continuous execution status signal input from the decoding unit 102, the vector instruction continuous execution detection unit 109a determines whether the subsequent instruction is a vector instruction.
When the vector instruction continuous execution detection unit 109a determines that the subsequent instruction is a vector instruction, the vector instruction execution detection unit 109 processes the subsequent instruction when the currently executed instruction code is a vector instruction. An instruction signal indicating that external interrupt processing is not to be executed (hereinafter referred to as “continuous interrupt prohibition signal”) is output to the program control unit 110 until the process ends.

  When the continuous interrupt inhibition signal is input from the vector instruction execution detection unit 109, the program control unit 110 suspends execution of external interrupt processing until the processing of the currently executing vector instruction and the processing of the subsequent instruction are completed. Then, when the instruction subsequent to the subsequent instruction is a vector instruction, the program control unit 110 continues to hold the execution of the external interrupt process as it is by performing the above-described processing in the same manner, and the instruction subsequent to the subsequent instruction is not a vector instruction. In this case, external interrupt processing is executed.

Next, the operation will be described.
The state transition diagram showing the operation of the processor 2 is different from the state transition diagram of the processor 1 shown in FIG.
That is, in FIG. 2, the state S2 (Normal) is a normal operation state in which no interrupt has occurred. In the state S2, when an external interrupt occurs, a transition is made to the state S3 except when the vector instruction is being processed and the subsequent instruction is a vector instruction (during continuous execution of the vector instruction), When an interrupt other than an external interrupt occurs, the flow goes to the state S5. Further, when reset is performed in the state S2, the state transitions to the state S1. Here, in the state S2, when an external interrupt occurs, if the vector instruction is being continuously executed, the state S2 is continued until the vector instruction is being processed and the subsequent instruction is no longer a vector instruction. To do.

As a result of such state transition, the processor 2 specifically performs the following operation regarding the interrupt processing.
FIG. 9 is a timing chart showing an operation example when an interrupt process occurs during the processing of successive vector instructions.
In FIG. 9, instruction codes (Inst 1 to 12) are sequentially input every cycle defined by the clock signal (CLK). Each instruction code is composed of stages of fetch address calculation (Fadr), fetch (F), decode (D), and execution (E). The instruction code Inst2 is a vector instruction for reading data of two words, and the execution stage extends over two cycles (E1 to E2). Further, the instruction code Inst3 is a vector instruction for adding data of 4 words, and the execution stage extends over 4 cycles (E1 to E4).

In FIG. 9, in cycle “1”, the instruction code Inst1 is input to the processor 2 to perform normal operation.
Then, in cycle “2”, an instruction code Inst2 that is a vector instruction is input, and subsequently, in cycle “3”, an instruction code Inst3 that is also a vector instruction is input.

Then, the processing is continued until the cycle “6” for the instruction code Inst2, and the processing is continued until the cycle “9” for the instruction code Inst3.
Here, in the cycle “4”, when external interrupt processing occurs, the instruction code Inst2 that is a vector instruction is being processed, and the subsequent instruction is also the instruction code Inst3 that is a vector instruction. The normal operation is continued until the cycle “9” when the last execution stage of the instruction code Inst3 is started.

In cycle “9”, the processor 2 starts the external interrupt process Inst9 and calculates the fetch address of the external interrupt process. Further, the operation state including the value of the program counter (PC) in the cycle “8” is temporarily saved.
Then, the processor 2 processes the instruction codes Inst9 to 11 related to the external interrupt processing in cycles “9” to “11”, and returns to the normal operation state from the cycle “12”.

As described above, when an external interrupt occurs during the processing of a vector instruction, the processor 2 according to the present embodiment performs external interrupt processing until the state where the vector instruction is not being continuously executed as shown in FIG. Hold on. When the vector instruction is not being continuously executed, external interrupt processing is executed.
Therefore, even when consecutive vector instructions share a register, it is possible to more reliably prevent a situation in which the operation result of the vector instruction is an invalid value, and safely execute interrupt processing. It becomes possible.

Even when the processor 2 processes a multi-cycle instruction, it is possible to perform the same interrupt processing control as in the case of a vector instruction as described above.
That is, as shown in FIG. 11, in the processor 2, the multi-cycle instruction execution detection unit 113 and the multi-cycle instruction continuous execution detection unit 113a corresponding to the vector instruction execution detection unit 109 and the vector instruction continuous execution detection unit 109a of FIG. And a continuous execution status signal indicating whether the instruction code subsequent to the instruction code currently being executed is a multi-cycle instruction is input from the decoding unit 102.

When an execution status signal indicating that the instruction code subsequent to the instruction code currently being executed is a multi-cycle instruction is input from the decoding unit 102, when the instruction code currently being executed is a multi-cycle instruction, The multicycle instruction execution detection unit 113 outputs a continuous interrupt inhibition signal to the program control unit 110.
By adopting such a configuration, similarly to the case of the vector instruction described above, it is possible to eliminate a problem caused by external interrupt processing being performed during continuous execution of multicycle instructions.

Here, in the first and second embodiments, it has been described that external interrupt processing is always suspended when a vector instruction or multi-cycle instruction is executed or continuously executed. However, in this case, there is a possibility that the holding time until the external interrupt processing is executed becomes longer.
Therefore, in order to reduce the occurrence of such a situation, after checking the dependency relationship of the data involved in the executed vector instruction or multi-cycle instruction and the subsequent instruction, if there is no dependency, External interrupt processing can be started during execution of a vector instruction or a multi-cycle instruction. Such dependency confirmation can be performed by the vector instruction execution detection unit 109 or the multicycle instruction execution detection unit 113 to which the decoding result of each instruction code to be processed is input.

The condition for determining whether or not there is a dependency relationship between the data related to the vector instruction being executed and the succeeding instruction is as follows: "The destination register of the preceding instruction is a scalar register, and the succeeding instruction Whether or not the destination register is used as a source register. For example,
ADD [8]% SR0,% VR0, VR1;
ST [8]% SR0, {% SR6,% SR7};
(However, the first line is an instruction for adding the value of the vector register VR1 to the value of the vector register VR0 and sequentially storing the value in the scalar register SR0. The second line stores the value of the scalar register SR0 in the scalar registers SR6 and SR7. This is an instruction to store in the memory address indicated by
In the case of the instruction sequence, when interrupt processing is performed between the first row and the second row, the value of the scalar register SR0, which is the destination register, sequentially changes during the interrupt processing, and the processing result of the second row Is illegal.

When the vector register VR2 is used instead of the scalar register SR0 in the first row and the second row, the value of the vector register VR2 used in the second row is maintained at a correct value, and the processing result in the second row is invalid. It will not be a thing.
In addition, the condition for determining whether or not there is a dependency relationship between the data related to the executed multi-cycle instruction and the succeeding instruction is “the destination register of the preceding multi-cycle instruction is a scalar register, and Whether the subsequent instruction uses the destination register as a source register before the result of the preceding multi-cycle instruction is written to the destination register. That is, this is the case when multiple allocation of scalar registers is performed in a multi-cycle instruction. For example,
LD% SR0, {% SR6,% SR7};
ADD% SR2,% SR0, SR1;
ADD% SR3,% SR0, SR1;
(However, the first line is an instruction for storing data read from the address {% SR0,% SR7} of the external memory in the scalar register SR0, and the second line is the value of the scalar register SR1 in addition to the value of the scalar register SR0. The third line is an instruction for adding the value of the scalar register SR1 to the value of the scalar register SR0 and storing it in the scalar register SR3.)
In the case of the instruction sequence, the first row is a multi-cycle instruction for reading data from the external memory, and the result is reflected in the processing cycle of the third row. That is, the scalar register SR0 in the second row and the scalar register SR0 in the third row are handled as different “variables”. Therefore, if interrupt processing is performed between the first row and the second row, the scalar register SR0 in the second row and the scalar register SR0 in the third row become the same “variable”, and the second row The processing result is incorrect.

  More specifically, if a, b, c, d, x, and y are variables, the first line substitutes the memory address value of c = d ({% SR6,% SR7} into the scalar register SR0). ), And the second line is x = a + b (the value of the scalar register SR0 and the value of the scalar register SR1 before the processing result of the first line is reflected is added and substituted into the scalar register SR2) This is the process. The third line is a process of y = c + b (the value of the scalar register SR0 and the value of the scalar register SR1 after the processing result of the first line is reflected is added and substituted into the scalar register SR2). . Therefore, if interrupt processing is performed between the first row and the second row, the variables a and c that should be different from each other become equal, and the values (x, y) stored in SR2 and SR3 are also originally different. The place where it becomes a value becomes equal.

  Therefore, after confirming the dependency relationship as described above, if there is no dependency relationship with the data related to the instruction, external interrupt processing can be executed even during execution of a vector instruction or multicycle instruction. is there.

2 is a diagram illustrating a configuration of a processor 1. FIG. FIG. 4 is a state transition diagram showing an operation of the processor 1. It is a timing chart showing an operation example when an external interrupt occurs during processing of a vector instruction. It is a schematic diagram which shows operation | movement of the processor 1 when an external interrupt generate | occur | produces during the process of a vector instruction. It is a figure which shows the structure of the processor 1 in the case of respond | corresponding to a multi cycle instruction. It is a timing chart which shows the operation example of this invention when interruption processing generate | occur | produces during the process of a multi-cycle instruction | indication. It is a timing chart which shows the example of the conventional operation | movement when an interruption process generate | occur | produces during the process of a multi-cycle instruction. 2 is a diagram showing a configuration of a processor 2. FIG. It is a timing chart which shows the operation example of this invention when interruption processing generate | occur | produces during the process of a continuous vector instruction. It is a schematic diagram which shows operation | movement of the processor 2 when an interruption process generate | occur | produces during the process of a continuous vector instruction. It is a figure which shows the structure of the processor 2 in the case of respond | corresponding to a multi cycle instruction. It is a figure which shows the structure of the conventional processor 200 which can perform an interrupt process. FIG. 11 is a schematic diagram illustrating an operation of the processor 200 when an interrupt occurs during processing of a vector instruction.

Explanation of symbols

1,2,200 processor, 101,201 fetch unit, 102,202 decoding unit, 103,203 ALU unit, 104,204 multiplication unit, 105,205 addition / subtraction unit, 106,206 load unit, 107,207 store unit, 108 , 208 register file section, 109 vector instruction execution detection section, 109a vector instruction continuous execution detection section, 110, 209 program control section, 111, 210 exception management section, 112, 211 external interrupt control section, 113 multi-cycle instruction execution detection section 113a multi-cycle instruction continuous execution detection unit, 209a program counter, 209b status register, 209c interrupt processing program counter, 209d interrupt vector

Claims (8)

A processor capable of processing vector instructions or multi-cycle instructions and capable of executing interrupt processing during the processing,
Execution detection means for detecting whether the vector instruction or the multi-cycle instruction is being processed;
When the execution detection means detects that the vector instruction or multicycle instruction is being processed, the execution of the interrupt process can be suspended until the processing of the vector instruction or multicycle instruction is completed. Interrupt control means;
A processor comprising: Further comprising continuous execution detecting means for detecting whether an instruction subsequent to the vector instruction or multi-cycle instruction being processed is a vector instruction or a multi-cycle instruction;
The interrupt control means is processed when the continuous execution detecting means detects that the instruction following the vector instruction or multicycle instruction being processed is a vector instruction or multicycle instruction. 2. The processor according to claim 1, wherein execution of interrupt processing can be suspended until processing of vector instructions or multi-cycle instructions and processing of subsequent instructions are completed. A determination means for determining a dependency relationship between data relating to the vector instruction or multi-cycle instruction being processed and data relating to a subsequent instruction;
The interrupt control means suspends execution of interrupt processing when the determination means determines that the dependency relationship exists, and executes interrupt processing when it is determined that the dependency relationship does not exist. The processor according to claim 1 or 2.   4. The determination unit according to claim 3, wherein the determination unit determines the dependency relationship based on a relationship between a destination register of a vector instruction or multicycle instruction being processed and a source register of a subsequent instruction. Processor. An interrupt control method in a processor capable of processing vector instructions or multi-cycle instructions and capable of executing interrupt processing during the processing,
An execution detection step for detecting whether the vector instruction or the multi-cycle instruction is being processed;
An interrupt control step for suspending execution of interrupt processing until the processing of the vector instruction or multicycle instruction is completed when it is detected that the vector instruction or multicycle instruction is being processed in the execution detection step; ,
An interrupt control method comprising: A continuous execution detecting step for detecting whether an instruction subsequent to the vector instruction or multi-cycle instruction being processed is a vector instruction or a multi-cycle instruction;
In the interrupt control step, when it is detected that the instruction subsequent to the vector instruction or multicycle instruction being processed is a vector instruction or multicycle instruction, the vector instruction or multicycle instruction being processed is detected. An interrupt control method characterized in that execution of interrupt processing is suspended until the processing of the above and the subsequent instruction processing are completed. A determination step of determining a dependency relationship between the data related to the vector instruction or the multi-cycle instruction being processed and the data related to the subsequent instruction;
6. The interrupt control step of suspending execution of interrupt processing when it is determined that the dependency relationship is present, and executing interrupt processing when it is determined that the dependency relationship is not present. Or the interruption control method of 6.   8. The determination step according to claim 7, wherein the dependency relationship is determined based on a relationship between a destination register of a vector instruction or multicycle instruction being processed and a source register of a subsequent instruction. Interrupt control method.

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