JP2005079306A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device that can suppress the shift of a threshold voltage. <P>SOLUTION: The method for manufacturing a semiconductor device comprises a process for forming a first SiO<SB>2</SB>film on a silicon substrate 1, a process for forming a high-permittivity insulating film containing a transition metal on the first SiO<SB>2</SB>film, a process for forming a second SiO<SB>2</SB>film on the high-permittivity insulating film, and a process for forming a gate electrode on the second SiO<SB>2</SB>film. Then, by heat-treating at least the first SiO<SB>2</SB>film, high-permittivity insulating film, and the second SiO<SB>2</SB>film; a gate insulating film 6 is formed where silicon concentration is high near the interface between the silicon substrate 1 and the gate electrode 7, and the silicon concentration becomes gradually lower toward the center. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a gate insulating film formed on a silicon substrate and a gate electrode formed on the gate insulating film.

  In recent years, high integration in semiconductor integrated circuit devices has greatly advanced, and in MOS (Metal Oxide Semiconductor) type semiconductor devices, elements such as transistors are miniaturized and high performance is achieved. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor.

Conventionally, a SiO ₂ (silicon oxide) film has been used as a material constituting the gate insulating film. On the other hand, when the gate insulating film becomes thinner with the miniaturization of the gate electrode, the tunnel current generated by the carriers (electrons and holes) directly tunneling through the gate insulating film, that is, the gate leakage current increases. . For example, according to ITRS (International Technology Roadmap for Semiconductors) 2001, in 2007, which is considered to be the 65 nm generation, the equivalent oxide thickness (EOT, equivalent oxide thickness) is 1 in 2007. A gate insulating film of 2 nm to 1.6 nm is required. However, when the SiO ₂ film is used, the gate leakage current due to the tunnel current exceeds the allowable value, and therefore, it is urgent to adopt a new material in place of the SiO ₂ film.

In view of this, research has been conducted to use a material having a higher relative dielectric constant as the gate insulating film instead of the SiO ₂ film. As a high dielectric constant insulating film (hereinafter referred to as a High-k film), a mixture of HfO ₂ (hafnium oxide) or ZrO ₂ (zirconium oxide) and SiO ₂ or Al ₂ O ₃ (aluminum oxide) is currently used. (See Patent Documents 1-2 and Non-Patent Documents 1-4). Since these films have a relative dielectric constant higher than that of the SiO ₂ film (relative dielectric constant 3.9), if the electrical film thickness (silicon oxide film equivalent film thickness) is constant, the film is more physically than the SiO ₂ film. The film thickness can be reduced. Therefore, it is possible to suppress the leakage current.

US Pat. No. 6,291,867 B1 US Pat. No. 6,020,243 ALP Rotandaro et al., Technology Digest of 2002 Symposium on VLSI Technology, 2002, p. 148-149 S. Inumiya, et al., Technology Digest of 2003 Symposium on VLSI Technology, 2003, p. 17-18 T. Watanabe et al., Technology Digest of 2003 Symposium on VLSI Technology, 2003, p. 19-20 A. Morikawa et al., Technology Digest of 2003 Symposium on VLSI Technology, 2003, p. 165-166

However, when the High-k film is used, there is a problem that the absolute value of the voltage V _th (threshold voltage) at which the transistor switches is shifted in a direction larger than that when the SiO ₂ film is used. It was. This tendency is more noticeable in PMOS (P-channel Metal Oxide Semiconductor) than in NMOS (N-Channel Metal Oxide Semiconductor). When such a threshold voltage shift occurs, the performance of the transistor is significantly degraded.

  The present invention has been made in view of the above-described problems. That is, an object of the present invention is to provide a method of manufacturing a semiconductor device that can suppress a shift in threshold voltage.

  Other objects and advantages of the present invention will become apparent from the following description.

The method for manufacturing a semiconductor device of the present invention includes a step of forming a first SiO ₂ film on a semiconductor substrate and a step of forming a high dielectric constant insulating film containing a transition metal on the first SiO ₂ film. If, forming a second SiO ₂ film on the high dielectric constant insulating film, and forming a gate electrode on the second SiO ₂ film, at least a first SiO ₂ By performing heat treatment on the film, the high dielectric constant insulating film, and the second SiO ₂ film, the silicon concentration is high near the interface between the semiconductor substrate and the gate electrode, and gradually decreases toward the center. An insulating film is formed.

In the present invention, the gate insulating film can be a film composed of a single layer whose composition continuously changes in the film thickness direction. Further, the gate insulating film, and the SiO ₂ film, the composition to have a film thickness direction on the SiO ₂ film may be made from a continuously varying film.

In the present invention, the thickness of the second SiO ₂ film is preferably 0.2 nm or more and 0.5 nm or less.

In the present invention, the high dielectric constant insulating film may be a film made of at least one material selected from the group consisting of transition metal oxides, transition metal aluminates, and transition metal silicates. The transition metal can be any one metal selected from the group consisting of Hf, Zr, Ti, Ta, and La. For example, the high dielectric constant insulating film can be an HfSiO ₄ film.

  In the present invention, the gate electrode can be made of polysilicon.

As described above, according to the present invention, the first SiO ₂ film, the High-k film, and the second SiO ₂ film are sequentially stacked on the semiconductor substrate, and then the heat treatment is performed. A gate insulating film is formed in which the silicon concentration in the vicinity of the interface is high, and the silicon concentration is gradually decreased toward the center. As a result, the transition metal concentration in the gate insulating film in the vicinity of these interfaces can be lowered, so that the reaction between the dopant in the semiconductor substrate and the gate electrode and the transition metal in the gate insulating film is suppressed. , _Vth shift amount can be reduced.

As a result of diligent research, the present inventor has found that the reason why the threshold voltage shifts is that the transition metal in the high-k film (high dielectric constant insulating film) is bonded to the dopant in the semiconductor substrate or the gate electrode. It was. For example, Hf (hafnium) in an HfSiO ₄ (hafnium silicate) film is combined with dopants B (boron) and P (phosphorus) to cause a large threshold voltage shift.

  Therefore, the present inventor has proposed that the threshold voltage is reduced by reducing the concentration of the transition metal in the high-k film in the vicinity of the interfaces between the high-k film and the semiconductor substrate and the high-k film and the gate electrode. Therefore, the present invention has been achieved. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is an example of a cross-sectional view of the semiconductor device according to this embodiment.

  As shown in FIG. 1, a diffusion layer 2, an element isolation region 3, a source / drain region 4 and an extension region 5 are formed on a silicon substrate 1 as a semiconductor substrate. A gate insulating film 6 and a gate electrode 7 are formed on the silicon substrate 1, and sidewalls 8 are formed on the side walls thereof. In FIG. 1, 9 is an interlayer insulating film, 10 is a contact, and 11 is a wiring layer.

  In the present embodiment, the gate insulating film 6 includes at least a transition metal, silicon, and oxygen, and the silicon concentration in the film is high in the vicinity of the interface between the silicon substrate 1 and the gate electrode 7, and is separated from these interfaces. The distribution is characterized by gradually decreasing toward the vicinity. The gate insulating film 6 is characterized in that the concentration of transition metal is low in the vicinity of the interface between the silicon substrate 1 and the gate insulating film 6 and in the vicinity of the interface between the gate electrode 7 and the gate insulating film 6.

  A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, the same reference numerals as those in FIG. 1 indicate the same parts.

  First, as shown in FIG. 2, a silicon oxide film is buried in a predetermined region of the silicon substrate 1 to form an element isolation region 3 having an STI (Shallow Trench Isolation) structure.

  Next, a diffusion layer 2 is formed on the silicon substrate 1 using a photolithography method (FIG. 2). For example, a resist pattern (not shown) is formed in a predetermined region, and N-type or P-type impurities are implanted into the silicon substrate 1 using this resist pattern as a mask. Thereafter, an N-type diffusion layer or a P-type diffusion layer can be formed by diffusing impurities by heat treatment.

  Next, the process proceeds to the step of forming the gate insulating film 6.

First, as shown in FIG. 3, a first SiO ₂ film 12 is formed on the surface of the silicon substrate 1. The first SiO ₂ film 12 can be formed by a thermal oxidation method or the like. For example, the surface of the silicon substrate 1 is oxidized at a temperature of about 800 ° C. in a mixed gas atmosphere composed of 1 vol% oxygen and 99 vol% nitrogen. Thereby, the first SiO ₂ film 12 can be formed.

Next, a high-k film 13 is formed on the first SiO ₂ film 12. As the High-k film 13, a film containing a transition metal and having a higher relative dielectric constant than the SiO ₂ film is used. For example, a film made of at least one material selected from the group consisting of oxides of transition metals, aluminates of transition metals, and silicates of transition metals can be used. Moreover, as a transition metal, Hf (hafnium), Zr (zirconium), Ti (titanium), Ta (tantalum), La (lanthanum), etc. can be used, for example.

  The High-k film 13 can be formed by, for example, a low pressure CVD (Chemical Vapor Deposition, hereinafter referred to as CVD) method or an atomic layer deposition (hereinafter referred to as ALD) method.

For example, an HfSiO ₄ (hafnium silicate) film is formed by a low pressure CVD method using (t—C ₄ H ₉ O) ₄ Hf (hafnium (IV) t-butoxide) and Si ₂ H ₆ (disilane). Can do. In this case, for example, the film formation temperature can be 300 ° C., and the film formation pressure can be 0.2 Torr (about 26.7 Pa).

After the high-k film 13 is formed, a second SiO ₂ film 14 is further formed on the high-k film 13 to finish the step of forming the gate insulating film 6. Here, the second SiO ₂ film 14 can be formed by a low pressure CVD method or an ALD method. For example, after the HfSiO ₄ film is formed by the low pressure CVD method using (t-C ₄ H ₉ O) ₄ Hf and Si ₂ H ₆ , the film forming gas is switched to only Si ₂ H ₆ . Thereby, a SiO ₂ film can be deposited on the HfSiO ₄ film.

As described above, the gate insulating film 6 in the present embodiment is the first SiO ₂ film 12, the High-k film 13 formed on the first SiO ₂ film 12, and the High- The second SiO ₂ film 14 is formed on the k film 13. However, in an actual semiconductor device, diffusion of atoms constituting each layer occurs by heat treatment applied in the process. For this reason, the structure of the gate insulating film 6 in the completed semiconductor device is not a three-layer structure composed of the three films described above, but a single-layer film showing a continuous composition change in the film thickness direction. Here, in the present embodiment, the gate insulating film 6 is formed by laminating the first SiO ₂ film 12, the High-k film 13, and the second SiO ₂ film 14 in this order. Therefore, even when the gate insulating film 6 is formed as a single layer as a whole, the composition of the film in the vicinity of the interface between the silicon substrate 1 and the gate electrode 7 has a high silicon concentration and a low transition metal concentration. can do.

In the present embodiment, in order to reduce the equivalent silicon oxide film thickness of the entire gate insulating film 6, the film thicknesses of the first SiO ₂ film 12, the high-k film 13, and the second SiO ₂ film 14 are as follows. It is preferable to make each as thin as possible. In particular, the thickness of the second SiO ₂ film 14 is preferably in the range of 0.2 nm to 0.5 nm. If the thickness is less than 0.2 nm, it is difficult to form a uniform film. On the other hand, if it is thicker than 0.5 nm, the equivalent silicon oxide film thickness is increased, which is not preferable.

On the other hand, the first SiO ₂ film 12 has a thickness that can suppress a reaction between the silicon substrate 1 and the high-k film 13. For example, the thickness of the first SiO ₂ film 12 can be about 1 nm.

By the way, depending on the film thickness of the first SiO ₂ film 12, the gate insulating film 6 after the diffusion of the constituent atoms by the heat treatment does not become a film consisting of a single layer, but consists of a SiO ₂ film and a mixed film 2. It can be considered that the film has a layer structure. Here, the mixed film is a layer on the SiO ₂ film whose composition continuously changes in the film thickness direction. In the present embodiment, the gate insulating film 6 may have such a structure. In other words, the gate insulating film in the completed semiconductor device is composed of the SiO ₂ film formed on the semiconductor substrate and the High-k film formed on the SiO ₂ film, and this High-k film. Contains at least a transition metal, silicon, and oxygen, and the concentration of silicon in the film is high near the interface between the SiO ₂ film and the gate electrode, and gradually decreases as it moves away from these interfaces toward the center. It may be a film. When the gate insulating film has such a structure, the concentration of the transition metal in the vicinity of the interface between the semiconductor substrate and the gate insulating film can be set to a value close to substantially zero.

In this embodiment, a film made of a material other than the SiO ₂ film may be provided between the high-k film and the gate electrode. For example, a gate insulating film having a high silicon concentration and a low transition metal concentration in the vicinity of the interface with the gate electrode can also be formed by providing a SiN film between the high-k film and the gate electrode. However, in the present embodiment, it is most preferable to provide a SiO ₂ film from the viewpoint of suppressing the formation of an interface state between the gate insulating film and the gate electrode and forming a stable interface.

  After the gate insulating film 6 is formed by the above steps, it is preferable to perform PDA (Post Deposition Annealing). Thereby, the amount of hydrogen caused by impurities contained in the High-k film 13 can be reduced to about 1/10.

  Next, the formation process of the gate electrode 7 is performed.

  First, a polysilicon film 15 as a gate electrode material is formed on the gate insulating film 6 (FIG. 4). The polysilicon film 15 can be formed by, for example, a CVD method.

  After the polysilicon film 15 is formed, a dopant such as P (phosphorus) is ion-implanted into the polysilicon film 15. Thereafter, the implanted dopant is activated by heat treatment. The conditions for the heat treatment can be, for example, about 1,000 ° C. for about 10 seconds.

Next, an SiO ₂ film 16 as a hard mask material is formed on the polysilicon film 15 (FIG. 4).

After forming the SiO ₂ film 16, an antireflection film (not shown) may be formed thereon. The antireflection film plays a role of eliminating exposure light reflection at the interface between the resist film and the antireflection film by absorbing exposure light transmitted through the resist film when patterning a resist film to be formed next. As the antireflection film, a film containing an organic substance as a main component can be used. For example, the antireflection film can be formed by a spin coating method or the like.

Next, a resist film (not shown) is formed on the SiO ₂ film 16, and a resist pattern 17 having a desired line width is formed by photolithography to obtain the structure shown in FIG.

Next, the SiO ₂ film 16 is dry etched using the resist pattern 17 as a mask. Thereafter, by removing the resist pattern 17 that is no longer needed, an SiO ₂ film pattern 18 as a hard mask can be formed as shown in FIG.

Next, dry etching of the polysilicon film 15 is performed using the SiO ₂ film pattern 18 as a mask. As the etching gas, for example, at least one gas selected from the group consisting of BCl ₃ , Cl ₂ , HBr, CF ₄ , O ₂ , Ar, N ₂ and He can be used.

  FIG. 7 shows a state after the polysilicon film 15 is dry-etched. As shown in the figure, the gate electrode 7 is formed by dry etching of the polysilicon film 15.

Next, the gate insulating film 6 is etched by etching using the SiO ₂ film pattern 18 as a mask. Thereby, the structure shown in FIG. 8 is obtained. 4 to 7, the gate insulating film 6 has a structure composed of the first SiO ₂ film 12, the High-k film 13, and the second SiO ₂ film 14. However, the structure of the gate insulating film 6 in the stage before FIG. 8 may be a single layer or a film made of a layer in the middle of changing to a single layer.

  Next, after ion-implanting impurities into the diffusion layer 2 in the silicon substrate 1 using the gate electrode 7 as a mask, the extension region 5 is formed by activation by heat treatment.

  Next, the sidewall 8 is formed in accordance with a known method to obtain the structure shown in FIG. At this time, the side walls 8 are formed on the side walls of the gate electrode 7 and the gate insulating film 6.

  Next, impurities are ion-implanted into the diffusion layer 2 in the silicon substrate 1. Subsequently, activation by heat treatment can be performed to form the source / drain regions 4 (FIG. 10). Thereafter, the structure shown in FIG. 1 can be obtained by forming the interlayer insulating film 9, the contact 10 and the wiring 11.

Then, through the above-described PDA treatment, dopant activation treatment, and heat treatment applied in each film formation step, the first SiO ₂ film, the High-k film, and the second SiO ₂ film are subjected to heat treatment. Diffusion of silicon atoms and transition metal atoms occurs. As a result, the gate insulating film 6 changes to a film having a high silicon concentration in the vicinity of the interface between the silicon substrate 1 and the gate electrode 7 and a gradually decreasing silicon concentration toward the vicinity of the center.

FIG. 11 shows an example of a change in the threshold voltage _Vth with respect to the gate length for the semiconductor device manufactured according to the present embodiment. In FIG. 11, as the gate insulating film of a semiconductor device according to this embodiment, after forming the HfSiO ₄ film and the SiO ₂ film in this order in a thickness 1nm about SiO ₂ film, the manufacturing process of the conventional semiconductor device What was obtained through the heat processing in was used. In addition, as a comparative example, a result of measurement of a semiconductor device using an HfSiO ₄ film formed by a conventional method as a gate insulating film is also shown. Here, the HfSiO ₄ film of the comparative example is a film having a uniform composition in the film thickness direction. Furthermore, the measurement results of the semiconductor device using only the SiO ₂ film as the gate insulating film are also shown.

As can be seen from FIG. 11, in the comparative example, the value of _Vth is greatly shifted in the direction in which the absolute value becomes larger than when only the SiO ₂ film is used. On the other hand, according to the present embodiment, the shift amount of _Vth can be made smaller than that of the comparative example. This is the same for both NMOS and PMOS.

As described above, in this embodiment, the semiconductor substrate and the gate electrode are formed by performing the heat treatment after sequentially laminating the first SiO ₂ film, the High-k film, and the second SiO ₂ film on the semiconductor substrate. A gate insulating film is formed in which the silicon concentration in the vicinity of the interface is high, and the silicon concentration gradually decreases toward the center. As a result, the concentration of the transition metal in the gate insulating film can be made low in the vicinity of these interfaces, or a value close to substantially zero. Therefore, according to the present embodiment, reaction between the dopant in the semiconductor substrate and the gate electrode and the transition metal in the gate insulating film can be suppressed, and the shift amount of _Vth can be reduced.

  In the present embodiment, an example in which a polysilicon film is used as the gate electrode material has been described. However, the present invention is not limited to this. Any film containing silicon such as an amorphous silicon film or a silicon germanium film can be used as the gate electrode material. The gate electrode may have a multilayer structure, and a polysilicon film, an amorphous silicon film, a silicon germanium film, or the like may be included in a part of the gate electrode.

It is sectional drawing of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning this Embodiment. An example of a diagram showing a change in threshold voltage depending on a gate length in this embodiment

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Diffusion layer 3 Element isolation region 4 Source / drain region 5 Extension region 6 Gate insulating film 7 Gate electrode 8 Side wall 9 Interlayer insulating film 10 Contact 11 Wiring layer 12 First SiO ₂ film 13 High-k film 14 Second SiO ₂ film 15 Polysilicon film 16 SiO ₂ film 14 Polysilicon film 17 Resist pattern 18 SiO ₂ film pattern

Claims (8)

Forming a first SiO ₂ film on a semiconductor substrate;
Forming a high dielectric constant insulating film containing a transition metal on the first SiO ₂ film;
Forming a _second SiO ₂ film on the high dielectric constant insulating film;
Forming a gate electrode on the second SiO ₂ film,
By performing a heat treatment on at least the first SiO ₂ film, the high dielectric constant insulating film, and the second SiO ₂ film, the silicon concentration in the vicinity of the interface between the semiconductor substrate and the gate electrode is high, and the vicinity of the center A method of manufacturing a semiconductor device, comprising: forming a gate insulating film in which the silicon concentration gradually decreases as it goes to.   The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film is formed of a single layer whose composition continuously changes in the film thickness direction. The gate insulating film, and the SiO ₂ film, a manufacturing method of a semiconductor device according to claim 1 which composition has a film thickness direction on the said SiO ₂ film is formed of a continuously varying film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the second SiO ₂ film is not less than 0.2 nm and not more than 0.5 nm.   5. The film according to claim 1, wherein the high dielectric constant insulating film is a film made of at least one material selected from the group consisting of transition metal oxides, transition metal aluminates, and transition metal silicates. Semiconductor device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the transition metal is any one metal selected from the group consisting of Hf, Zr, Ti, Ta, and La. The method of manufacturing a semiconductor device according to claim 6, wherein the high dielectric constant insulating film is an HfSiO ₄ film.   The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode is made of polysilicon.

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