JP2007080913A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce damage on a gate insulation film or a semiconductor substrate when a metal gate electrode is formed. <P>SOLUTION: When gate electrodes 12 and 22 are formed, a first metal layer 31 of low etching rate is formed thin in one of two regions for forming first and second MOSFETs 10 and 20 under predetermined etching conditions and a second metal layer 32 of high etching rate is formed thick in the other region under those predetermined etching conditions, and then the first and second metal layers 31 and 32 are etched simultaneously. Consequently, difference in etching rate is offset by difference in thickness and etching of the first and second metal layers 31 and 32 can be ended simultaneously or substantially simultaneously. Etching damage on the gate insulation films 11 and 21 or the Si substrate 2 can thereby be minimized. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a metal gate electrode and a manufacturing method thereof.

  In forming an LSI (Large Scale Integrated circuit) having a high-performance CMOSFET (Complementally Metal Oxide Semiconductor Field Effect Transistor) structure, it is important to suppress depletion of the gate electrode. Replacing a poly-Si gate electrode generally used in recent years with a metal gate electrode is considered to be an effective means for suppressing the depletion of such a gate electrode.

  In a CMOSFET using a Poly-Si gate electrode, for the purpose of reducing a threshold voltage, p-type Poly-Si in which majority carriers are holes is usually used as a p-channel MOSFET (pMOSFET) and an n-channel MOSFET (nMOSFET). And n-type Poly-Si in which majority carriers are electrons. On the other hand, in the case of a CMOSFET using a metal gate electrode, it is necessary to use metals having different work functions for the pMOSFET and the nMOSFET in order to control the threshold voltage.

  Several methods for forming such a metal gate electrode have been proposed. For example, a titanium nitride (TiN) layer is first formed on a gate insulating film formed on a wafer, and after removing the TiN layer in the nMOSFET region, tantalum nitride silicide (TaSiN) is formed in both the nMOSFET region and the pMOSFET region. ) Layer and a Poly-Si layer. Then, the metal gate electrode portions of the pMOSFET region and the nMOSFET region are left, and the other portions of the Poly-Si layer, TaSiN layer, and TiN layer are etched. Thereby, three metal gate electrodes of Poly-Si layer / TaSiN layer / TiN layer are formed in the pMOSFET region, and two metal gate electrodes of Poly-Si layer / TaSiN layer are formed in the nMOSFET region. Metal gate electrodes having different work functions and thicknesses are formed in the regions (see Non-Patent Document 1).

In addition, a method has also been proposed in which nitrogen (N) is ion-implanted only into the nMOSFET region of the TiN layer formed on the gate insulating film so that the work functions of the metal layers in the pMOSFET region and the nMOSFET region are different (non-native). Patent Document 2). In this case, metal gate electrodes having the same thickness are formed in the pMOSFET region and the nMOSFET region.
“International Electron Devices Meeting (IEDM) Technical Digest”, 2002, p. 433 “International Electron Devices Meeting (IEDM) Technical Digest”, 1999, p. 253

However, when forming the metal gate electrode, the following problems may occur.
For example, as described above, a three-layer gate electrode material is formed on the gate insulating film in the pMOSFET region, and a two-layer gate electrode material of the same material as the upper two layers in the pMOSFET region is formed on the gate insulating film in the nMOSFET region. When the metal gate electrode is formed by etching it into a predetermined pattern, there is a difference in the time required to complete the etching in each region. For this reason, the gate insulating film on the nMOSFET region side where the gate electrode material is formed thinly is exposed to etching for a longer time, and etching damage is caused to the gate insulating film and the semiconductor substrate therebelow. was there.

  Such a problem is not limited to the case where the thicknesses of the gate electrode materials before the etching process formed in the pMOSFET region and the nMOSFET region are different from each other.

  19 to 22 are diagrams showing an example of a conventional method for forming a metal gate electrode. FIG. 19 is a schematic cross-sectional view of an essential part of a gate electrode material forming process, and FIG. 20 is an essential cross-sectional view of a first etching process. FIG. 21 and FIG. 22 are schematic cross-sectional views of the relevant part in the second etching step.

  For example, as shown in FIG. 19, an STI (Shallow Trench Isolation) 101 that defines a pMOSFET region 100a and an nMOSFET region 100b is formed on a Si substrate 100, and the pMOSFET region 100a is interposed via a gate insulating film 102. Assume that the first metal layer 103 is formed and the second metal layer 104 is formed in the nMOSFET region 100b. Here, the etching rate of the first metal layer 103 is lower than that of the second metal layer 104.

  In the case where the pMOSFET region 100a and the nMOSFET region 100b are simultaneously etched to form the respective metal gate electrodes, a mask film 105 is first formed on the entire surface as shown in FIG. Thereafter, patterning is performed to form mask patterns 105a in the pMOSFET region 100a and the nMOSFET region 100b as shown in FIG. Then, using the mask as a mask, the first and second metal layers 103 and 104 are etched.

  However, when the first and second metal layers 103 and 104 are simultaneously etched under the same conditions, the first metal layer 103 has a lower etching rate, and as shown in FIG. The etching of the metal layer 104 is completed earlier. If the etching is continued as it is to finish the etching of the first metal layer 103 in the remaining pMOSFET region 100a at this time, the etching damage 106 enters the gate insulating film 102 and the Si substrate 100 in the nMOSFET region 100b as described above. This will cause a problem (FIG. 22).

  Such etching damage to the gate insulating film and the semiconductor substrate causes misalignment of these regions when ion implantation for forming the source / drain / extension region and the source / drain region is performed thereafter. In some cases, the on / off characteristics of the MOSFET may be adversely affected and the performance of the CMOSFET may be degraded.

  In addition to the above problems, the following problems may occur when the characteristics of the metal gate electrode itself are considered. For example, when one metal gate electrode of the CMOSFET is formed with a thick metal layer having a high specific resistance and the other metal gate electrode is formed with a thin metal layer having a low specific resistance, the ON / OFF of the circuit of the CMOSFET is thereby performed. High performance such as off characteristics will be hindered. As described above, when forming the metal gate electrode, in addition to the thickness of the metal layer having a different work function constituting the metal gate electrode, it is necessary to consider its resistance.

  The present invention has been made in view of these points, and an object thereof is to provide a high-performance and high-quality semiconductor device including a metal gate electrode and a method for manufacturing the same.

  In order to solve the above problems, the present invention provides a semiconductor device including a metal gate electrode, the semiconductor device including a plurality of transistors including metal gate electrodes having metal layers having different work functions, and the metal gates of the plurality of transistors. Of the metal layers having different work functions, the metal layer having a low etching rate under a predetermined etching condition is formed thinner than the metal layer having a high etching rate under the predetermined etching condition. An apparatus is provided.

  According to such a semiconductor device, the metal layer having a low etching rate under a predetermined etching condition is formed thinner than the metal layer having a high etching rate under the etching condition. When the gate electrodes are formed, for example, even when they are etched at the same time, the etching rate difference is canceled by the difference in thickness, and the etching can be completed simultaneously or almost simultaneously. As a result, it is possible to obtain a semiconductor device in which etching damage to the gate insulating film formed under the metal layer and the semiconductor substrate therebelow is minimized.

  Furthermore, in the present invention, in a semiconductor device including a metal gate electrode, the semiconductor device includes a plurality of transistors each including a metal gate electrode having a metal layer having a different work function, and the metal gate electrode of the plurality of transistors includes the metal. A semiconductor device is provided in which a metal layer having a high specific resistance is formed thinner than a metal layer having a low specific resistance.

  According to such a semiconductor device, since the metal layer having a high specific resistance is formed thinner than the metal layer having a low specific resistance, it is possible to suppress deterioration in performance such as on / off characteristics of the semiconductor device. become.

  Further, according to the present invention, in a method of manufacturing a semiconductor device having a metal gate electrode, a step of forming metal layers having different work functions and thicknesses through gate insulating films in different transistor formation regions on a semiconductor substrate, And a step of simultaneously etching the metal layers having different work functions and thicknesses under the condition that etching is completed simultaneously or substantially simultaneously.

  According to such a method of manufacturing a semiconductor device, metal layers having different work functions and thicknesses are formed in the formation regions of different transistors on the semiconductor substrate via the gate insulating films, respectively, and these metal layers are formed simultaneously or substantially. At the same time, etching is performed under the condition that the etching is completed, so that it is possible to minimize etching damage to the gate insulating film formed under the metal layer and the semiconductor substrate therebelow.

  In the present invention, metal layers having different work functions used for the metal gate electrode are formed with different thicknesses and etched under predetermined conditions. As a result, etching damage to the gate insulating film formed under the metal layer and the semiconductor substrate therebelow can be minimized, and a high-performance and high-quality semiconductor device can be realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings taking CMOSFETs as an example.
First, the first embodiment will be described.
FIG. 1 is a schematic cross-sectional view of an essential part of an example of a CMOSFET.

  In the CMOSFET 1 shown in FIG. 1, an STI 3 is formed on a silicon (Si) substrate 2, and element regions of the first MOSFET 10 and the second MOSFET 20 are defined by the STI 3. Here, one of the first and second MOSFETs 10 and 20 is a p-channel type and the other is an n-channel type.

  The first MOSFET 10 has a metal gate electrode 12 formed on a Si substrate 2 via a gate insulating film 11, and a sidewall insulating film 13 is formed on the outside thereof. Further, in the Si substrate 2 on both sides of the metal gate electrode 12, a source / drain / extension region 14 of a predetermined conductivity type is formed immediately below the sidewall insulating film 13, and in the Si substrate 2 on both sides of the sidewall insulating film 13, A source / drain region 15 of a predetermined conductivity type is formed.

  The second MOSFET 20 has the same structure as this, and has a laminated structure of a gate insulating film 21 and a metal gate electrode 22 on the Si substrate 2, and a sidewall insulating film 23 is formed outside thereof. In the Si substrate 2, a source / drain / extension region 24 and a source / drain region 25 of a predetermined conductivity type are formed in a predetermined region.

  Here, the first and second metal gate electrodes 12 and 22 of the first and second MOSFETs 10 and 20 have first and second metal layers 31 and 32 formed on the gate insulating films 11 and 21, respectively. The third metal layer 33 has a stacked structure. It is assumed that the first and second metal layers 31 and 32 have different work functions. The first metal layer 31 and the second metal layer 32 are formed such that the second metal layer 32 is thicker than the first metal layer 31.

  If the thicknesses of the first and second metal layers 31 and 32 are different in this way, the materials of the first and second metal layers 31 and 32 are assumed to be the same, and are etched simultaneously under the same conditions. In this case, the etching of the first thin metal layer 31 is completed earlier. Therefore, when forming the metal gate electrodes 12, 22, a metal layer having a low etching rate is formed thin as the first metal layer 31, and a metal layer having a high etching rate is formed thick as the second metal layer 32. If etching is performed in this manner, the etching rate difference is offset by the difference in thickness, and the etching of the first and second metal layers 31 and 32 can be completed simultaneously or almost simultaneously. Thereby, damage to the gate insulating films 11 and 21 and the Si substrate 2 can be minimized.

  Alternatively, etching is performed by setting the etching conditions so that the etching rate is lower in the first metal layer 31 formed thinner and the etching rate is higher in the second metal layer 32 formed thicker. However, the same effect can be obtained.

  Next, a method for forming the CMOSFET 1 having the above configuration will be described. Here, a case where the first MOSFET 10 is a pMOSFET and the second MOSFET 20 is an nMOSFET will be described as an example.

2 to 9 are diagrams for explaining an example of the method of forming the CMOSFET according to the first embodiment. Hereinafter, an example of the forming method will be described in order with reference to FIGS.
FIG. 2 is a schematic cross-sectional view of an essential part of a gate insulating film forming process according to the first embodiment.

First, according to a conventional method, the Si substrate 2 in which the STI 3 is formed to form the pMOSFET region (pMOSFET region) 10a and the nMOSFET region (nMOSFET region) 20a is thermally oxidized to a thickness of about 0.5 nm. A silicon oxide (SiO ₂ ) film is grown.

Next, metalorganic chemical vapor deposition (Metal) using tetra-tertiary-butoxy-hafnium (HTB) and disilane (Si ₂ H ₆ ) as raw materials in an atmosphere at a temperature of about 280 ° C. and a pressure of about 0.3 Torr (about 40 Pa). A hafnium silicate (HfSiO) film having a thickness of about 2.5 nm is formed in the pMOSFET region 10a and the nMOSFET region 20a by an organic chemical vapor deposition (MOCVD) method.

Next, heat treatment is performed in an ammonia (NH ₃ ) / nitrogen (N ₂ ) atmosphere at a temperature of about 700 ° C. and a pressure of about 0.76 Torr (about 101 Pa) to introduce N into the HfSiO film. Thereby, as shown in FIG. 2, a gate insulating film 40 of hafnium nitride silicate (HfSiON) is formed in the pMOSFET region 10a and the nMOSFET region 20a.

FIG. 3 is a schematic cross-sectional view of an essential part of the first metal layer forming step according to the first embodiment.
After the formation of the gate insulating film 40, the pMOSFET region 10a and the nMOSFET region 20a are formed by chemical vapor deposition (CVD) using titanium tetrachloride (TiCl ₄ ) and NH ₃ as raw materials as shown in FIG. Then, a TiN layer having a thickness of about 10 nm is formed as the first metal layer 31.

FIG. 4 is a schematic cross-sectional view of an essential part of the first metal layer removing step of the first embodiment.
After the formation of the first metal layer 31, a mask film 41 is formed in the pMOSFET region 10a using a photolithography technique as shown in FIG. Then, it is immersed in hydrogen peroxide water (H ₂ O ₂ / H ₂ O) at a temperature of 60 ° C., and the first metal layer 31 in the nMOSFET region 20a is removed to obtain the state shown in FIG. Thereafter, the mask film 41 is removed.

FIG. 5 is a schematic cross-sectional view of an essential part of the second metal layer forming step according to the first embodiment.
After removal of the mask film 41, a tantalum silicide (TaSi) layer having a thickness of about 25 nm is formed as the second metal layer 32 in the pMOSFET region 10a and the nMOSFET region 20a by sputtering, as shown in FIG. As described above, the second metal layer 32 is formed thicker than the first metal layer 31 in consideration of an etching rate described later.

FIG. 6 is a schematic cross-sectional view of an essential part of the second metal layer removing step of the first embodiment.
After the formation of the second metal layer 32, a mask film 42 is formed in the nMOSFET region 20a using a photolithography technique as shown in FIG. Thereafter, chlorine (Cl ₂ ) / nitrogen trifluoride (NF ₃ ) / argon (Ar) / oxygen (O ₂ ) = 40/40/140/16 (sccm (= mL / min, 0 ° C., 101.3 kPa) ), The second metal layer 32 on the first metal layer 31 is dry-etched to obtain the state shown in FIG. After the dry etching, the mask film 42 is removed.

FIG. 7 is a schematic cross-sectional view of the relevant part showing a third metal layer forming step according to the first embodiment.
After the removal of the mask film 42, a tungsten (W) layer having a thickness of about 50 nm is formed as a third metal layer 33 in the pMOSFET region 10a and the nMOSFET region 20a as shown in FIG. Form.

FIG. 8 is a schematic cross-sectional view of the relevant part in the third metal layer etching step of the first embodiment.
After the formation of the third metal layer 33, as shown in FIG. 8, first, a mask film 43 is formed in the formation region of the metal gate electrode using a photolithography technique. Then, the third metal layer 33 is dry-etched under the condition of Cl ₂ / NF ₃ / Ar / O ₂ = 40/40/140/16 (sccm). For example, in the generation where the half pitch (hp) is 65 nm, the dimension (gate length) of the third metal layer 33 after processing is set to about 50 nm.

FIG. 9 is a schematic cross-sectional view of the relevant part in the etching process of the first and second metal layers of the first embodiment.
After the etching of the third metal layer 33, the first and second metal layers 31 and 32 are subjected to the conditions of Cl ₂ / carbon tetrafluoride (CF ₄ ) / N ₂ = 40/40/20 (sccm). At the same time, dry etching is performed.

  Under this etching condition, the etching rate of the TiN layer as the first metal layer 31 is about 30 nm / min, and the etching rate of the TaSi layer as the second metal layer 32 is about 75 nm / min. Here, in consideration of such an etching rate, the thickness of the first metal layer 31 is about 10 nm, and the thickness of the second metal layer 32 is about 25 nm. Therefore, under the above etching conditions, even if the pMOSFET region 10a and the nMOSFET region 20a are etched simultaneously, the etching of the first and second metal layers 31 and 32 having different thicknesses is completed at the same time or almost simultaneously. To come.

  After the dry etching, as shown in FIG. 9, the metal gate electrode 12 in which the first metal layer 31 of the thin TiN layer and the third metal layer 33 of the W layer are stacked is formed in the pMOSFET region 10a, and the nMOSFET is formed. A metal gate electrode 22 in which a second metal layer 32 of a thick TaSi layer and a third metal layer 33 of a W layer are stacked is formed in the region 20a.

After the formation of the metal gate electrodes 12 and 22, the CMOSFET 1 having the structure shown in FIG. 1 is formed by the following procedure.
First, the gate insulating film 40 is dry-etched to form the gate insulating films 11 and 21 in the pMOSFET region 10a and the nMOSFET region 20a, respectively, and then the mask film 43 is removed. Then, ion implantation is performed on the pMOSFET region 10a using the metal gate electrode 12 as a mask to form a source / drain extension region 14, and ion implantation is performed on the nMOSFET region 20a using the metal gate electrode 22 as a mask. -The extension region 24 is formed.

  Thereafter, sidewall insulating films 13 and 23 are formed in the pMOSFET region 10a and the nMOSFET region 20a, respectively. Then, ions are implanted into the pMOSFET region 10a using the metal gate electrode 12 and the sidewall insulating film 13 as a mask to form source / drain regions 15, and the metal gate electrode 22 and the sidewall insulating film 23 are used as a mask in the nMOSFET region 20a. Ion implantation is performed to form source / drain regions 25.

As impurities used for ion implantation at the time of forming the impurity diffusion layer, for example, boron fluoride (BF ₂ ) can be used for the pMOSFET region 10a, and arsenic (As) can be used for the nMOSFET region 20a. .

  As described above, in the first embodiment, the first and second metal layers 31 and 32 are formed in the pMOSFET region 10a and the nMOSFET region 20a with thicknesses corresponding to the etching rates of the metal layers used. I tried to do it. Then, by etching them simultaneously under the same conditions, the etching rate difference between the first and second metal layers 31 and 32 is offset by the difference in thickness. Thereby, it is possible to minimize etching damage to the gate insulating film 40 and the Si substrate 2 when the metal gate electrodes 12 and 22 are formed by etching.

  As a result, the first metal layer 31 having a low etching rate is thin, the second metal layer 32 having a high etching rate is formed thick, and has metal gate electrodes 12 and 22 having different work functions and thicknesses in the pMOSFET and the nMOSFET. A high-performance and high-quality CMOSFET 1 is formed.

  Here, the first metal layer 31 having a low etching rate under a predetermined etching condition is formed thin and the second metal layer 32 having a high etching rate is formed thick. However, the first metal layer 31 formed thin is formed. Etching may be performed by adjusting conditions so that the second metal layer 32 formed thicker than the metal layer 31 has a higher etching rate. Also by such a method, the CMOSFET 1 having the above configuration can be formed, and a high-performance and high-quality CMOSFET 1 can be formed.

Next, a second embodiment will be described.
In a CMOSFET provided with a metal gate electrode, the resistance of the metal gate electrode is one of the factors that determine circuit performance such as on / off characteristics, and when a metal gate electrode having a thick metal layer with a high specific resistance is used, Circuit performance is degraded. When forming the metal gate electrode, it is desirable to set the thickness of the pMOSFET side and the nMOSFET side in consideration of the resistance of the metal layer. Hereinafter, an example of a method of forming the CMOSFET in consideration of the resistance of the metal layer used for the metal gate electrode will be described with reference to FIGS.

FIG. 10 is a schematic cross-sectional view of the relevant part in the step of forming the gate insulating film according to the second embodiment.
First, an STI 50 is formed according to a conventional method, and the Si substrate 51 in which the pMOSFET region 10b and the nMOSFET region 20b are defined is thermally oxidized to grow a SiO ₂ film having a thickness of about 0.5 nm.

Next, atomic layer deposition (Atomic Layer Deposition, ALD) using tetrakis-ethyl-methyl-amino-hafnium (TEMAHf) and water vapor (H ₂ O) as raw materials in an atmosphere at a temperature of about 300 ° C. and a pressure of about 125 mTorr (about 17 Pa). ) Method, a hafnia (HfO ₂ ) film having a thickness of about 3 nm is formed as the gate insulating film 52 in the pMOSFET region 10b and the nMOSFET region 20b.

FIG. 11 is a schematic cross-sectional view of an essential part of the first metal layer forming step according to the second embodiment.
After the formation of the gate insulating film 52, a CVD method using tungsten hexafluoride (WF ₆ ) as a raw material is used to form a first metal layer 53 in the pMOSFET region 10b and the nMOSFET region 20b as shown in FIG. A 20 nm W layer is formed.

FIG. 12 is a schematic cross-sectional view of the relevant part in the first metal layer removing step of the second embodiment.
After the formation of the first metal layer 53, a mask film 54 is formed in the pMOSFET region 10b using a photolithography technique as shown in FIG. Then, dry etching is performed under the condition of CF ₄ = 100 (sccm), the first metal layer 53 in the nMOSFET region 20b is removed, and the state shown in FIG. 12 is obtained. Thereafter, the mask film 54 is removed.

FIG. 13 is a schematic cross-sectional view of the relevant part in the second metal layer forming step of the second embodiment.
After the removal of the mask film 54, a TaSi layer having a thickness of about 10 nm is formed as the second metal layer 55 in the pMOSFET region 10b and the nMOSFET region 20b by sputtering as shown in FIG. In this way, the second metal layer 55 is formed thinner than the first metal layer 53 in consideration of the specific resistance of the W layer and the TaSi layer and the etching rate described later.

FIG. 14 is a schematic cross-sectional view of an essential part of the second metal layer removing step according to the second embodiment.
After the formation of the second metal layer 55, a mask film 56 is formed in the nMOSFET region 20b using a photolithography technique as shown in FIG. Thereafter, the second metal layer 55 on the first metal layer 53 is dry-etched under the condition of Cl ₂ / CF ₄ / N ₂ = 40/40/20 (sccm), and the state shown in FIG. obtain. After the dry etching, the mask film 56 is removed.

FIG. 15 is a schematic cross-sectional view of an essential part of a third metal layer forming step according to the second embodiment.
After the removal of the mask film 56, tungsten silicide (WSi) having a thickness of about 50 nm is formed as a third metal layer 57 in the pMOSFET region 10b and the nMOSFET region 20b as shown in FIG. Form a layer.

FIG. 16 is a schematic cross-sectional view of the relevant part in the third metal layer etching step of the second embodiment.
After the formation of the third metal layer 57, as shown in FIG. 16, first, a mask film 58 is formed in the formation region of the metal gate electrode by using a photolithography technique. Then, the third metal layer 57 is dry-etched under the condition of Cl ₂ / NF ₃ / Ar / O ₂ = 40/40/140/16 (sccm). For example, in the generation of hp 65 nm, the dimension (gate length) of the third metal layer 57 after processing is set to about 50 nm.

FIG. 17 is a schematic cross-sectional view of the relevant part in the etching process of the first and second metal layers of the second embodiment.
After the etching of the third metal layer 57, the first and second metal layers 53 and 55 are simultaneously formed under the conditions of Cl ₂ / NF ₃ / Ar / O ₂ = 40/40/140/16 (sccm). Perform dry etching.

  Under this etching condition, the etching rate of the W layer as the first metal layer 53 is about 150 nm / min, and the etching rate of the TaSi layer as the second metal layer 55 is about 75 nm / min. Here, the TaSi layer of the second metal layer 55 is made thinner than the W layer of the first metal layer 53 having a lower specific resistance, and the etching rate of both metal layers is taken into consideration. The thickness of the first metal layer 53 is about 20 nm, and the thickness of the second metal layer 55 is about 10 nm. Therefore, under the above etching conditions, even if the pMOSFET region 10b and the nMOSFET region 20b are simultaneously etched, the etching of the first and second metal layers 53 and 55 having different thicknesses is completed simultaneously or almost simultaneously. To come.

  After the dry etching, as shown in FIG. 17, a metal gate electrode 59 is formed in which the first metal layer 53 having a thick W layer and the third metal layer 57 having a WSi layer are stacked in the pMOSFET region 10b. In the region 20b, a metal gate electrode 60 in which a second metal layer 55 of a thin TaSi layer and a third metal layer 57 of a WSi layer are stacked is formed.

  The etching of the first and second metal layers 53 and 55 shown in FIG. 17 can be performed under the same conditions as the etching of the third metal layer 57 shown in FIG. Therefore, the first and second metal layers 53 and 55 may be etched following the etching of the third metal layer 57.

FIG. 18 is a schematic cross-sectional view of an essential part in the step of forming the impurity diffusion layer and the sidewall insulating film according to the second embodiment.
After the formation of the metal gate electrodes 59 and 60, first, the gate insulating film 52 is dry etched to form gate insulating films 61 and 62 in the pMOSFET region 10b and the nMOSFET region 20b, respectively. Thereafter, the mask film 58 shown in FIG. 17 is removed.

  Then, ion implantation is performed on the pMOSFET region 10b using the metal gate electrode 59 as a mask to form a source / drain extension region 63, and ion implantation is performed on the nMOSFET region 20b using the metal gate electrode 60 as a mask. -An extension region 64 is formed.

  Thereafter, sidewall insulating films 65 and 66 are formed in the pMOSFET region 10b and the nMOSFET region 20b, respectively. Then, ions are implanted into the pMOSFET region 10b using the metal gate electrode 59 and the sidewall insulating film 65 as a mask to form source / drain regions 67, and the metal gate electrode 60 and the sidewall insulating film 66 are used as a mask in the nMOSFET region 20b. Ion implantation is performed to form source / drain regions 68.

For example, BF ₂ can be used for the pMOSFET region 10b and As can be used for the nMOSFET region 20b as impurities used for ion implantation when forming the impurity diffusion layer.

  As described above, in the second embodiment, the pMOSFET region 10b and the nMOSFET region 20b have the first metal layer 53, the second metal layer 53, and the thickness corresponding to the etching rate and specific resistance of the metal layer used. 55 was formed. Then, by etching them simultaneously under the same conditions, the etching rate difference between the first and second metal layers 53 and 55 is offset by the difference in their thickness, and the thickness according to the specific resistance of the metal layer The metal gate electrodes 59 and 60 are formed. Accordingly, it is possible to minimize etching damage to the gate insulating film 52 and the Si substrate 51 when the metal gate electrodes 59 and 60 are formed by etching.

  As a result, the first metal layer 53 having a low specific resistance and a high etching rate is thick, and the second metal layer 55 having a high specific resistance and a low etching rate is formed thin. The pMOSFET and the nMOSFET have different work functions and thicknesses. A high-performance and high-quality CMOSFET having the metal gate electrodes 59 and 60 is formed.

  Here, the first metal layer 53 having a high etching rate and a low specific resistance is formed thickly under a predetermined etching condition, and the second metal layer 55 having a low etching rate and a high specific resistance is formed thinly. However, the etching is performed by adjusting the conditions so that the etching rate of the second metal layer 55 having a high specific resistance is thinner than that of the first metal layer 53 having a low specific resistance, which is formed thick. May be. Also by such a method, the CMOSFET having the configuration as shown in FIG. 18 can be formed, and a high-performance and high-quality CMOSFET can be formed.

  Although the first and second embodiments have been described above, the CMOSFET described in the first and second embodiments is an example, and materials, formation conditions, and the like are appropriately changed as necessary. Is possible.

  For example, the etching conditions of the first metal layers 31 and 53 and the second metal layers 32 and 55 can be set according to the combination of the materials and the film thickness, and according to the etching conditions. It is also possible to set the combination of these materials and the film thickness.

In addition, the gate insulating films 11, 21, 61, 62 (gate insulating films 40, 52) are not only Hf oxide-based materials containing Hf and oxygen (O) such as HfSiON and HfO ₂ , but also zirconium ( Zr oxide materials containing Zr) and O, La oxide materials containing lanthanum (La) and O, Ta oxide materials containing Ta and O, and the like can also be used. Furthermore, materials such as SiO ₂ , silicon oxynitride (SiON), silicon nitride (SiN) can be used.

  In the first and second embodiments, the third metal layers 33 and 57 are formed on the first metal layers 31 and 53 and the second metal layers 32 and 55 for the purpose of reducing the resistance. Although formed, the third metal layers 33 and 57 are not necessarily formed. For example, when the resistances of the first metal layers 31 and 53 and the second metal layers 32 and 55 are sufficiently low by themselves, it is not necessary to form the third metal layers 33 and 57 thereon. is there.

  In the first and second embodiments, in addition to forming the first metal layers 31 and 53 and the second metal layers 32 and 55 from different materials, the first metal layers 31 and 53 The third metal layers 33, 57, the second metal layers 32, 55, and the third metal layers 33, 57 are also formed of different materials. However, the first metal layers 31, 53 and the third metal layers 33, 57 are formed of different materials. The metal layers 33 and 57, the second metal layers 32 and 55, and the third metal layers 33 and 57 may be made of the same material. For example, in the second embodiment, a W layer and a TaSi layer may be used as the first and second metal layers 53 and 55, and a W layer may be used as the third metal layer 57 instead of the WSi layer. It is.

  As mentioned in the second embodiment (see FIGS. 16 and 17), the first metal layers 31, 53, the second metal layers 32, 55, and the third metal layers 33, 57 Depending on the combination of materials and the stacking order, the etching of the third metal layers 33 and 57 and the etching of the first metal layers 31 and 53 and the second metal layers 32 and 55 can be performed in one step. . However, in that case, attention is paid to the shape of the metal gate electrodes 12, 22, 59, 60 obtained when the process is performed in one process and the process performed in two processes, and uniformity in the wafer surface.

(Additional remark 1) In the semiconductor device provided with the metal gate electrode,
Having a plurality of transistors with metal gate electrodes having metal layers with different work functions;
Of the metal layers having different work functions of the metal gate electrodes of the plurality of transistors, a metal layer having a low etching rate under a predetermined etching condition is formed thinner than a metal layer having a high etching rate under the predetermined etching condition. A semiconductor device characterized by that.

  (Appendix 2) The metal layer having a low etching rate and the metal layer having a high etching rate are formed in such a thickness that the etching is completed at the same time or almost simultaneously when the etching is simultaneously performed under the predetermined etching conditions. 2. The semiconductor device according to appendix 1, wherein:

(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein the plurality of transistors are a p-channel MOSFET and an n-channel MOSFET.
(Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the gate insulating films of the p-channel MOSFET and the n-channel MOSFET contain at least hafnium and oxygen in composition.

(Additional remark 5) In the semiconductor device provided with the metal gate electrode,
Having a plurality of transistors with metal gate electrodes having metal layers with different work functions;
A semiconductor device, wherein a metal layer having a high specific resistance among the metal layers of the metal gate electrodes of the plurality of transistors is formed thinner than a metal layer having a low specific resistance.

  (Appendix 6) The metal layer having a high specific resistance and the metal layer having a low specific resistance are each of such thicknesses that the etching is completed simultaneously or substantially simultaneously when etching is performed simultaneously under predetermined etching conditions. The semiconductor device according to appendix 5, wherein the semiconductor device is formed.

(Supplementary note 7) The semiconductor device according to supplementary note 5, wherein the plurality of transistors are a p-channel MOSFET and an n-channel MOSFET.
(Supplementary note 8) The semiconductor device according to supplementary note 7, wherein the gate insulating films of the p-channel MOSFET and the n-channel MOSFET contain at least hafnium and oxygen in composition.

(Additional remark 9) In the manufacturing method of the semiconductor device provided with the metal gate electrode,
Forming a metal layer having a different work function and thickness through a gate insulating film in a formation region of different transistors on a semiconductor substrate;
Etching the metal layers having different work functions and thicknesses at the same time under the condition that the etching is completed simultaneously or substantially simultaneously; and
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 10) In the step of forming the metal layer having a different work function and thickness through the gate insulating film in each of the different transistor formation regions on the semiconductor substrate,
The metal layer having a low etching rate under the etching conditions used in the step of simultaneously etching the metal layers having different work functions and thicknesses at the same time or almost simultaneously with the etching is more than the metal layer having a high etching rate under the etching conditions. The method of manufacturing a semiconductor device according to appendix 9, wherein the semiconductor device is formed thin.

(Supplementary Note 11) In the step of simultaneously etching the metal layers having different work functions and thicknesses at the same time or almost simultaneously under the condition that the etching is finished,
10. The method of manufacturing a semiconductor device according to appendix 9, wherein etching is performed under a condition that an etching rate of a thin metal layer among metal layers having different work functions and thicknesses is lower than an etching rate of a thicker metal layer.

(Supplementary Note 12) In the step of forming the work layers and the metal layers having different thicknesses through the gate insulating films in the formation regions of the different transistors on the semiconductor substrate,
Among the metal layers having different work functions and thicknesses, a metal layer having a high specific resistance is formed thinner than a metal layer having a low specific resistance,
In the step of etching the metal layers having different work functions and thicknesses at the same time under the condition that the etching is completed simultaneously or almost simultaneously,
10. The method of manufacturing a semiconductor device according to appendix 9, wherein etching is performed under a condition that an etching rate of the metal layer having a high specific resistance is lower than an etching rate of the metal layer having a low specific resistance.

It is a principal part cross-section schematic diagram of an example of CMOSFET. It is a principal part cross-sectional schematic diagram of the formation process of the gate insulating film of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the 1st metal layer of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the removal process of the 1st metal layer of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the 2nd metal layer of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the removal process of the 2nd metal layer of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the 3rd metal layer of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the etching process of the 3rd metal layer of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the etching process of the 1st, 2nd metal layer of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the gate insulating film of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the 1st metal layer of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the removal process of the 1st metal layer of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the 2nd metal layer of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the removal process of the 2nd metal layer of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the 3rd metal layer of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the etching process of the 3rd metal layer of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the etching process of the 1st, 2nd metal layer of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of the impurity diffusion layer and side wall insulating film of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the formation process of gate electrode material. It is a principal part cross-sectional schematic diagram of a 1st etching process. It is a principal part cross-sectional schematic diagram of the 2nd etching process (the 1). It is a principal part cross-sectional schematic diagram of the 2nd etching process (the 2).

Explanation of symbols

1 CMOSFET
2,51 Si substrate 3,50 STI
10 First MOSFET
10a, 10b pMOSFET region 11, 21, 40, 52, 61, 62 Gate insulating film 12, 22, 59, 60 Metal gate electrode 13, 23, 65, 66 Side wall insulating film 14, 24, 63, 64 Source, drain, Extension region 15, 25, 67, 68 Source / drain region 20 Second MOSFET
20a, 20b nMOSFET region 31, 53 First metal layer 32, 55 Second metal layer 33, 57 Third metal layer 41, 42, 43, 54, 56, 58 Mask film

Claims (5)

In a semiconductor device provided with a metal gate electrode,
Having a plurality of transistors with metal gate electrodes having metal layers with different work functions;
Of the metal layers having different work functions of the metal gate electrodes of the plurality of transistors, a metal layer having a low etching rate under a predetermined etching condition is formed thinner than a metal layer having a high etching rate under the predetermined etching condition. A semiconductor device characterized by that. In a semiconductor device provided with a metal gate electrode,
Having a plurality of transistors with metal gate electrodes having metal layers with different work functions;
A semiconductor device, wherein a metal layer having a high specific resistance among the metal layers of the metal gate electrodes of the plurality of transistors is formed thinner than a metal layer having a low specific resistance. In a method for manufacturing a semiconductor device provided with a metal gate electrode,
Forming a metal layer having a different work function and thickness through a gate insulating film in a formation region of different transistors on a semiconductor substrate;
Etching the metal layers having different work functions and thicknesses at the same time under the condition that the etching is completed simultaneously or substantially simultaneously; and
A method for manufacturing a semiconductor device, comprising: In the step of forming the work layers and the metal layers having different thicknesses through the gate insulating films in the formation regions of the different transistors on the semiconductor substrate,
The metal layer having a low etching rate under the etching conditions used in the step of simultaneously etching the metal layers having different work functions and thicknesses at the same time or almost simultaneously with the etching is more than the metal layer having a high etching rate under the etching conditions. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is formed thin. In the step of forming the work layers and the metal layers having different thicknesses through the gate insulating films in the formation regions of the different transistors on the semiconductor substrate,
Among the metal layers having different work functions and thicknesses, a metal layer having a high specific resistance is formed thinner than a metal layer having a low specific resistance,
In the step of etching the metal layers having different work functions and thicknesses at the same time under the condition that the etching is completed simultaneously or almost simultaneously,
4. The method of manufacturing a semiconductor device according to claim 3, wherein etching is performed under a condition that an etching rate of the metal layer having a high specific resistance is lower than an etching rate of the metal layer having a low specific resistance.

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