JP2005078467A - Reset method and circuit for digital signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reset method and reset circuit for carrying out digital signal processing by receiving the operation voltage from a plurality of power sources with different voltages (for example, +3.3V and +5V) and for reliably initializing a plurality of circuits connected to each other by signal lines regardless of power-on time difference. <P>SOLUTION: This circuit consists of a first circuit (3.3V circuit) 11 power-supplied from, for example a +3.3V power source, a second circuit (5.0V circuit) 12 power-supplied from, for example a +5.0V power source, power-on reset circuits 13, 14 for these circuits, a DC-DC converter 16 supplying reset circuit power to the power-on reset circuit 13, and a determination circuit 15 being connected to the +3.3V and +5.0V power sources and supplying control signal to the power-on reset circuit 13. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a reset method and a reset circuit, and more particularly to a power-on reset technique for resetting (initializing) each circuit when a digital signal processing circuit is powered on.

  In various circuits including computers, digital circuits are widely used instead of analog circuits because of various advantages such as operational stability and reliability (noise resistance characteristics). The digital signal processing circuit is generally configured to operate under the control of a clock. After each circuit part constituting the digital signal processing circuit is reset (initialized) at the start of operation (or power-on), a reset circuit, that is, a power-on reset circuit is provided to operate each circuit part in a stable operation state. Provided.

For example, in a data bus expansion device that transmits and receives signals between data processing devices that are computers, in order to avoid a risk that another data processing device malfunctions due to a signal before resetting from one data processing device, the data processing device A technique is disclosed in which a signal output from the data processing device to another data processing device is cut off while the power-on reset signal is significant (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 4-336361 (page 2, FIG. 1 and FIG. 2)

  Each circuit constituting the data signal processing apparatus is not necessarily designed to operate with a single power source. It is common to operate with a plurality of power sources according to the characteristics of the circuit device used. A general operating power supply voltage is, for example, + 5.0V. However, a circuit that operates at a lower voltage, for example, + 3.3V is also designed in response to a demand for lower power consumption. Therefore, the data signal processing apparatus generally operates at a plurality of different operating voltages. Thus, the power-on reset circuit of the data signal processing device that operates at different operating voltages needs to be performed in consideration of the power-on state of each operating power source.

  FIG. 3 shows a block diagram of a conventional reset circuit used for this purpose. The reset circuit (or power-on reset circuit) 30 in FIG. 3 includes circuits (hereinafter referred to as 3.3V circuit and 5.0V circuit) 31 and 32 that operate with power supplies of +3.3 volts and +5.0 volts, respectively. 3.3V power-on reset circuit 33 and 5.0V power-on reset circuit 34 for resetting the corresponding 3.3V circuit 31 and 5.0V circuit 32 respectively for a certain period after the power is turned on (power-on). The 3.3V circuit 31 and the 5.0V circuits 32, 31 are interconnected by a signal line 38, and are configured to exchange signals when the power is turned on. The plurality of power supply voltages are generally obtained from a commercial power supply or a built-in battery using a DC-DC converter or the like.

  Next, the operation of the reset circuit 30 shown in FIG. 3 will be described with reference to the timing chart of FIG. 4, (a) is a + 5.0V power input, (b) is a 5V power on reset signal input from the 5.0V power on reset circuit 34 to the 5.0V circuit 32, and (c) is + 3.3V power. A 3.3V power-on reset signal input from the on-reset circuit 33 to the 3.3V circuit 31 and (d) indicate a + 3.3V power supply input.

  When a plurality of different power sources such as +5.0 V and +3.3 V are mixed in the apparatus as shown in FIG. 3, if the load capacity applied to each power source changes, each power source will rise to a predetermined voltage. A time difference occurs. At this time, until the power is turned on to the circuit that is turned on late, a voltage is generated from the signal line to the circuit that is turned on first, and the power is turned off. Despite not being turned on, a voltage about half the power supply voltage is generated.

  FIG. 4 shows a case where the + 3.3V power supply is turned on later than the + 5.0V power supply. When the + 5.0V power supply is turned on at time t0 as shown in FIG. 2A, a time t1 when the power supply exceeds a predetermined voltage (+ 5.0V threshold) is detected, and from this time t1 A power-on reset signal for initializing the 5.0V circuit 32 is output from the 5.0V power-on reset circuit 34 during Trst2 time until time t2. Then, the 5.0V circuit 32 starts to operate after this time t2. Similarly, the 3.3V power-on reset circuit 33 originally detects the time when the + 3.3V power supply is turned on at time t3 and exceeds the 3.3V threshold, and from that time to Trst1, 3.3V The 3.3V power-on reset circuit 33 generates a 3.3V power-on reset signal that initializes the circuit 31.

  However, between the time t2 and the time t3 until the 5.0V circuit 32 starts operating and the + 3.3V power supply is turned on, the + 3.3V power supply is connected between the 5.0V circuit 32 and the 3.3V circuit 31. A wraparound occurs from the signal line 38. Therefore, since a voltage near the 3.3V threshold is generated, the 3.3V power-on reset circuit 33 starts operating before the + 3.3V power is turned on. Further, since the 3.3V power-on reset circuit 33 itself is also operated by the + 3.3V power supply, the circuit operation is also uncertain and unstable during the time t2 to t3 when the + 3.3V power supply is in the uncertain region. Therefore, the output of the power-on reset signal is also uncertain. On the other hand, since the 3.3V circuit 31 also operates with a + 3.3V power supply, the operation may start between time t2 and time t3 without a reliable circuit initialization by a power-on reset signal.

  In the conventional reset circuit as described above, when there are a plurality of power supplies, the operation of the power-on reset circuit of each power supply becomes unstable due to the difference in the rise time of the voltage due to the difference in load capacity. As a result, there is a possibility that proper initialization of a circuit operating with each power supply is not performed. Accordingly, an object of the present invention is to provide a digital signal processing circuit reset method and a reset circuit that overcome the problems of the prior art.

  In order to solve the above-described problems, the digital signal processing circuit reset method and reset circuit according to the present invention employ the following special configuration.

(1) A digital signal processing circuit that performs digital signal processing by receiving voltage supply from power sources having different voltages and initializes the first circuit and the second circuit connected to each other through signal lines when the power is turned on. In the reset method of
A reset method of a digital signal processing circuit, wherein a power-on reset circuit is operated by a power supply that rises first among the plurality of power supplies, and uncertainty of circuit operation due to a difference in turn-on time of the plurality of power supplies is removed.

  (2) The digital signal processing circuit resetting method according to (1), wherein the power source that rises first is a power source having a higher voltage among the plurality of power sources.

(3) The first circuit and the second circuit, which are connected to each other by the signal lines while performing the digital signal processing operation by receiving different voltages from the power sources, respectively, and are initialized when the first circuit and the second circuit are turned on, respectively. In a reset circuit of a digital signal processing circuit including a power-on reset circuit
A reset circuit for a digital signal processing circuit, comprising: a determination circuit that monitors a power source of the first circuit and the second circuit and outputs a control signal for controlling validity / invalidity of an output of a power-on reset circuit to the first circuit.

  (4) The reset circuit for the digital signal processing circuit according to (3), wherein the control signal output from the determination circuit is switched from invalid to valid when a power supply voltage to the first circuit exceeds a determination circuit threshold value.

  (5) A DC-DC converter that is supplied with a voltage from the power supply of the second circuit, and the reset circuit power is supplied from the DC-DC converter to the power-on reset circuit of the first circuit. Or (4) a reset circuit of the digital signal processing circuit.

  (6) The reset circuit of the digital signal processing circuit according to (2), (4) or (5), wherein the determination circuit threshold value is set higher than a normal threshold value of the power-on reset circuit of the first circuit. .

  (7) The digital signal processing circuit according to (3), (4), (5) or (6), wherein the power supply voltages of the first circuit and the second circuit are substantially +3.3 V and +5.0 V, respectively. Reset circuit.

  According to the digital signal processing circuit reset method and reset circuit of the present invention, even if there is a time difference in power-on to a digital signal processing circuit that operates with a plurality of power supplies having different voltages, the operation is uncertain and the circuit is initialized. Can be reliably performed.

  Hereinafter, the configuration and operation of a preferred embodiment of a digital signal processing circuit reset method and reset circuit according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the configuration of a preferred embodiment of a reset circuit of a digital signal processing circuit according to the present invention. The reset circuit 10 is a reset circuit for a data signal processing apparatus that operates with a plurality of power supplies of + 3.3V power supply and + 5.0V power supply. The reset circuit 10 includes a 3.3V circuit (first circuit) 11, a 5.0V circuit (second circuit) 12, a 3.3V power-on reset circuit (first power-on reset circuit) 13, 5.0V. A power-on reset circuit (power-on reset circuit) 14, a 3.3 V determination circuit 15, and a DC-DC converter 16 are included. The 3.3V circuit 11 and the 5.0V circuit 12 are connected to each other by a signal line 18 and exchange signals between these circuits 11 and 12.

  Here, the 3.3V circuit 11 is supplied with an operating voltage from a + 3.3V power supply. On the other hand, the 5.0V circuit 12, the 5.0V power-on reset circuit 14, and the DC-DC converter circuit 16 are supplied with operating voltages from a + 5.0V power source. The 3.3V determination circuit 15 is connected to a + 3.3V power supply and a 5.0V power supply, and then outputs a control signal to the 3.3V power-on reset circuit 13. Further, the DC-DC converter 16 supplies reset circuit power to the 3.3V power-on reset circuit 13.

  Here, as is clear from comparison with the conventional reset circuit 30 shown in FIG. 3 described above, instead of providing independent power-on reset circuits for a plurality of power supplies to be used, the reset circuit 10 of the present invention shown in FIG. In order to operate the power reset circuit by providing a 3.3V determination circuit, a rough power-on reset signal is generated using a power supply whose voltage rises quickly. That is, the 3.3V determination circuit 15 monitors the voltage of the + 3.3V power supply, and outputs a control signal that enables the reset signal of the 3.3V power-on reset circuit 13 when the voltage exceeds the + 3.3V threshold. Occur. The DC-DC converter 16 generates a + 3.3V voltage from a + 5.0V power supply. The 3.3V power-on reset circuit 13 operates with the output of the DC-DC converter 16 and resets the 3.3V circuit 11 to an initial state for a time (Trst1) required for circuit initialization. The 5.0V power-on reset circuit 14 resets the 5.0V circuit 12 operating with a + 5.0V power supply for a certain period of time to bring the circuit into an initial state.

  Next, the operation of the reset circuit 10 of the present invention shown in FIG. 1 will be described with reference to the timing chart of FIG. 2, (a) is a + 5.0V power input, (b) is a 5.0V power-on reset signal from the 5.0V power-on reset circuit 14, and (c) is generated by the DC-DC converter 16 +3. 3D power input, (d) is a control signal output from the 3.3V determination circuit 15 to the 3.3V power-on reset circuit 13, and (e) is a 3.3V power-on reset circuit 13 from the DC-DC converter 16. (F) indicates a 3.3V power-on reset signal output from the 3.3V power-on reset circuit 13 to the 3.3V circuit 11.

  FIG. 2 shows an example in which the + 3.3V power supply is turned on later than the + 5.0V power supply. In FIG. 2, the + 5.0V power supply is turned on at time t0 (see FIG. 2 (a)). A time t1 when the voltage of the + 5.0V power supply becomes a voltage exceeding the + 5.0V threshold value of the 5.0V circuit 12 from 0V is detected. During the reset period (Trst2) from time t1 to time t2, a power-on reset signal that initializes the 5.0V circuit 12 is output from the 5.0V power-on reset circuit 14 (see FIG. 2B). Thereafter, the 5.0V circuit 12 starts to operate.

  On the other hand, the DC-DC converter 16 creates a reset circuit power supply (see FIG. 2E) that rises in response to the input from the + 5.0V power supply and supplies the reset circuit power supply to the 3.3V power-on reset circuit 13. As a result, the 3.3V power-on reset circuit 13 becomes operable from time t1 when the + 5.0V power supply exceeds the threshold value.

  The 3.3V determination circuit 15 operates with the + 5.0V power supply that is input first, and monitors the voltage of the + 3.3V power supply. Then, the voltage t higher than the 3.3V threshold is set as the determination circuit threshold (see FIG. 2C), and the time t4 when the voltage rises without the influence of the above-described wraparound is detected. When the determination circuit threshold value is exceeded at this time t4, a control signal (see FIG. 2D) for enabling the output of the 3.3V power-on reset circuit 13 is output to the 3.3V power-on reset circuit 13. To do.

  In FIG. 2, since the + 3.3V power supply is not turned on from time t1 to time t2, the control signal shown in FIG. 2 (d) invalidates the output of the 3.3V power-on reset circuit 13, that is, 3.3V. The circuit 11 is reset. From the time t2 when the + 5.0V circuit 12 starts to operate until the time t3 when the + 3.3V power supply is turned on, a voltage near the threshold is generated in the + 3.3V power supply due to the wraparound. The value does not reach the decision circuit threshold. Therefore, the 3.3V circuit 11 is maintained in the reset state by the control signal of the 3.3V determination circuit 15.

  Thereafter, when the + 3.3V power supply is turned on at time t3 (see FIG. 2C), the control signal becomes effective from time t4 exceeding the determination threshold value of the 3.3V determination circuit 15. Therefore, the 3.3V power-on reset circuit 13 outputs a power-on reset signal during a period (Trst1) from time t4 to time t5 (see FIG. 2 (f)).

  As described above, by operating the power-on reset circuit 13 of the 3.3V circuit 11 that operates with the + 3.3V power supply that is input later (after the + 5.0V power supply) with the + 5.0V power supply that is input first. The operation uncertainty of the 3.3V power-on reset circuit 13 caused by the sneaking from the + 5.0V power supply is eliminated, and the circuit can be initialized reliably.

  The configuration and operation of the preferred embodiment of the reset circuit according to the present invention have been described in detail above. However, it should be noted that such examples are merely illustrative of the invention and do not limit the invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made without departing from the spirit of the present invention.

1 is a block diagram showing the configuration of a preferred embodiment of a reset circuit according to the present invention. 2 is a timing chart for explaining the operation of each part of the reset circuit shown in FIG. 1. It is a block diagram which shows the structure of the conventional reset circuit. 4 is a timing chart for explaining the operation of the conventional reset circuit shown in FIG. 3.

Explanation of symbols

10 Reset circuit 11 3.3V circuit (first circuit)
12 5.0V circuit (second circuit)
13 3.3V power-on reset circuit 14 5.0V power-on reset circuit 15 judgment circuit (3.3V judgment circuit)
16 DC-DC converter 18 Signal line

Claims (7)

Method of resetting digital signal processing circuit for performing digital signal processing by receiving voltage supply from power sources having different voltages and performing circuit initialization at the time of power-on of the first circuit and the second circuit connected to each other by signal lines In
A method for resetting a digital signal processing circuit, wherein a power-on reset circuit is operated by a power supply that rises first among the plurality of power supplies, and uncertainties in circuit operation due to a difference in turn-on time of the plurality of power supplies are removed.   The digital signal processing circuit resetting method according to claim 1, wherein the power source that rises first is a power source having a higher voltage among the plurality of power sources. The first circuit and the second circuit, which perform digital signal processing operations by receiving different voltages from the power supply and are interconnected by signal lines, and the power to be initialized when the first circuit and the second circuit are turned on, respectively. In a reset circuit of a digital signal processing circuit comprising an on-reset circuit,
A digital signal processing comprising: a determination circuit that monitors a power source of the first circuit and the second circuit and outputs a control signal for controlling validity / invalidity of an output of a power-on reset circuit to the first circuit Circuit reset circuit.   4. The digital signal processing circuit according to claim 3, wherein the control signal output from the determination circuit is switched from invalid to effective when a power supply voltage to the first circuit exceeds a determination circuit threshold value. Reset circuit.   A DC-DC converter to which a voltage is supplied from a power source of the second circuit is provided, and reset circuit power is supplied from the DC-DC converter to a power-on reset circuit of the first circuit. 5. A reset circuit for a digital signal processing circuit according to 3 or 4.   6. The reset circuit for a digital signal processing circuit according to claim 2, wherein the determination circuit threshold value is set higher than a normal threshold value of a power-on reset circuit of the first circuit.   7. The reset circuit of a digital signal processing circuit according to claim 3, wherein the power supply voltages of the first circuit and the second circuit are substantially + 3.3V and + 5.0V, respectively. .

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