JP2005077644A - Wiring board having optical waveguide - Google Patents

Wiring board having optical waveguide Download PDF

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JP2005077644A
JP2005077644A JP2003306994A JP2003306994A JP2005077644A JP 2005077644 A JP2005077644 A JP 2005077644A JP 2003306994 A JP2003306994 A JP 2003306994A JP 2003306994 A JP2003306994 A JP 2003306994A JP 2005077644 A JP2005077644 A JP 2005077644A
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optical waveguide
wiring
relaxation layer
optical
insulating substrate
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JP4267982B2 (en
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Takeshi Ono
猛 大野
Masaki Ono
正樹 大野
Toshifumi Kojima
敏文 小嶋
Toshikazu Horio
俊和 堀尾
Ayako Kawamura
彩子 川村
Toshikatsu Takada
俊克 高田
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/43Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability wiring substrate with an optical waveguide by further improving relaxation of stresses between an insulating substrate and an optical waveguide, located upward on the surface thereof. <P>SOLUTION: The wiring board K1 with an optical waveguide, comprising an insulating substrate 1 having a flat surface 2, an optical waveguide C which is located upward on the surface 2 of this insulating board 1 and has a higher coefficient of thermal expansion than that of the insulating board 1, and a lower relaxation layer 11 and an upper relaxation layer 26, which are formed between the surface of the insulating board and the optical waveguide and upward on the optical waveguide C, and whose thermal expansion coefficients lie between those of the insulating substrate 1 and of the optical waveguide C. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、表面付近に光導波路を有する光導波路付き配線基板に関する。   The present invention relates to a wiring board with an optical waveguide having an optical waveguide near the surface.

信号伝送速度や信号処理速度を高めるため、配線基板の電気配線に例えば高周波信号を流す試みが行われている。しかし、電気配線に高周波信号を流した場合、その付近にノイズや電磁波が発生するため、周囲で誤動作などを招くおそれがある。かかる問題を解決するため、電気配線またはその一部を光配線に置き換えた光導波路付き配線基板が検討されている。
例えば、基板上に十分な密着強度でシロキサンポリマからなる光導波路を形成するため、基板と光導波路との間に同様のポリマからなるバッファ層を配置した光導波路基板が提案されている(例えば、特許文献1参照)。
また、長期間使用した際でもクラックの発生を防ぐため、基板上に応力緩和層を介して、下部クラッド層、コア、および上部クラッド層を形成した高分子光導波路も提案されている(例えば、特許文献2参照)。
In order to increase the signal transmission speed and the signal processing speed, for example, an attempt is made to flow a high-frequency signal through the electrical wiring of the wiring board. However, when a high-frequency signal is passed through the electrical wiring, noise and electromagnetic waves are generated in the vicinity thereof, which may cause malfunctions in the surroundings. In order to solve such a problem, a wiring board with an optical waveguide in which electric wiring or a part thereof is replaced with optical wiring has been studied.
For example, in order to form an optical waveguide made of siloxane polymer with sufficient adhesion strength on the substrate, an optical waveguide substrate in which a buffer layer made of a similar polymer is disposed between the substrate and the optical waveguide has been proposed (for example, (See Patent Document 1).
In addition, in order to prevent the occurrence of cracks even when used for a long time, a polymer optical waveguide in which a lower cladding layer, a core, and an upper cladding layer are formed on a substrate via a stress relaxation layer has also been proposed (for example, (See Patent Document 2).

特開2002−341162号公報 (第1〜7頁、図1)JP 2002-341162 A (pages 1-7, FIG. 1) 特開2001−264562号公報 (第1〜6頁、図1)JP 2001-264562 A (pages 1 to 6, FIG. 1)

前記光導波路基板や高分子光導波路によれば、基板上に光導波路を形成する際、かかる光導波路に応力が残りにくい点において、信頼性を有する。
しかしながら、例えば基板の表面上に形成した光導波路の上に光素子や動作素子を搭載する場合、かかる光導波路を形成する上部クラッド層と上記素子との間における応力が残留する。このため、上部クラッド層にクラックが生じたり、上記光素子の搭載すべき位置がずれて、光導波路との間における光信号の授受が不安定になり得る、という問題があった。
According to the optical waveguide substrate or the polymer optical waveguide, when the optical waveguide is formed on the substrate, the optical waveguide substrate or the polymer optical waveguide is reliable in that stress hardly remains in the optical waveguide.
However, for example, when an optical element or an operating element is mounted on an optical waveguide formed on the surface of the substrate, stress remains between the upper clad layer forming the optical waveguide and the element. For this reason, there has been a problem that cracks may be generated in the upper clad layer, or the position where the optical element is to be mounted may be shifted, resulting in unstable transmission and reception of optical signals with the optical waveguide.

本発明は、以上において説明した背景技術の問題点を解決し、絶縁性基板とその表面上方に配置する光導波路との間における応力の緩和を一層向上し、信頼性の高い光導波路付き配線基板を提供する、ことを課題とする。   The present invention solves the problems of the background art described above, further improves stress relaxation between the insulating substrate and the optical waveguide disposed above the surface thereof, and has a highly reliable wiring substrate with an optical waveguide. It is an issue to provide.

本発明は、上記課題を解決するため、絶縁性基板とその表面上方に配置する光導波路との間における応力を、かかる光導波路の上下においてそれぞれ緩和する、ことに着想して成されたものである。
即ち、本発明の光導波路付き配線基板(請求項1)は、表面を有する絶縁性基板と、かかる絶縁性基板の表面上方に配置され且つ熱膨張率が上記絶縁性基板の熱膨張率よりも高い光導波路と、上記絶縁性基板の表面と光導波路との間およびかかる光導波路の上方に形成され、且つ熱膨張率が上記絶縁性基板と上記光導波路との中間である下緩和層および上緩和層と、を含む、ことを特徴とする。
尚、上記絶縁性基板は、例えば熱膨張率が約15ppm/K以下のセラミックまたは樹脂からなる。また、上記光導波路は、例えばクラッドおよびこれに内蔵されるコアの2重構造体で、熱膨張率が約60〜120ppm/Kのアクリル系、エポキシ系、またはポリシラン系樹脂からなる。更に、上・下緩和層は、例えばワニスをスピンコートし更に硬化したもの、具体的にはドライフィルムを貼り付けてプレス硬化したもので、熱膨張率が約20〜65ppm/Kである。
In order to solve the above-mentioned problems, the present invention was conceived in order to relieve stress between an insulating substrate and an optical waveguide disposed above the surface above and below the optical waveguide. is there.
That is, a wiring board with an optical waveguide according to the present invention (Claim 1) is provided with an insulating substrate having a surface, and is disposed above the surface of the insulating substrate and has a thermal expansion coefficient higher than that of the insulating substrate. A high optical waveguide, a lower relaxation layer formed between the surface of the insulating substrate and the optical waveguide and above the optical waveguide, and having a thermal expansion coefficient intermediate between the insulating substrate and the optical waveguide; And a relaxation layer.
The insulating substrate is made of, for example, ceramic or resin having a coefficient of thermal expansion of about 15 ppm / K or less. The optical waveguide is, for example, a double structure of a clad and a core built in the clad, and is made of an acrylic, epoxy, or polysilane resin having a thermal expansion coefficient of about 60 to 120 ppm / K. Further, the upper and lower relaxation layers are, for example, those obtained by spin-coating varnish and further curing, specifically, those obtained by applying a dry film and press-curing, and have a coefficient of thermal expansion of about 20 to 65 ppm / K.

また、本発明には、前記上緩和層は、前記光導波路の両端に位置する反射ミラー面の上方の位置に一対の透孔を形成しており、かかる一対の透孔の上方で且つ上緩和層の表面上に光素子がそれぞれ実装されている、光導波路付き配線基板(請求項2)も含まれる。上記光素子は、光電変換素子の発光素子および受光素子であって、例えばSiやGaAsなどからなり、その熱膨張率は、約6ppm/K以下である。
付言すれば、前記上緩和層は、前記光導波路の両端に位置する反射ミラー面の上方の位置に一対の透孔を形成しており、かかる一対の透孔の上方で且つ上緩和層の表面上に、前記絶縁性基板の熱膨張率よりも低い熱膨張率である光素子がそれぞれ実装されている、光導波路付き配線基板も含まれ得る。
In the present invention, the upper relaxation layer has a pair of through holes formed at positions above the reflecting mirror surfaces located at both ends of the optical waveguide, and the upper relaxation layer is located above the pair of through holes and the upper relaxation layer. A wiring board with an optical waveguide (claim 2) in which optical elements are respectively mounted on the surface of the layer is also included. The optical element is a light emitting element and a light receiving element of a photoelectric conversion element, and is made of, for example, Si or GaAs, and has a coefficient of thermal expansion of about 6 ppm / K or less.
In other words, the upper relaxation layer has a pair of through holes formed at positions above the reflecting mirror surfaces located at both ends of the optical waveguide, and above the pair of through holes and on the surface of the upper relaxation layer. In addition, a wiring board with an optical waveguide on which optical elements having a thermal expansion coefficient lower than that of the insulating substrate are mounted may be included.

更に、本発明には、前記光素子に隣接し且つ前記光導波路と反対側の前記上緩和層の表面上に当該光素子と導通する動作素子が実装されている、光導波路付き配線基板(請求項3)も含まれる。
尚、上記動作素子は、これと導通する光素子に対し、電気信号から所定の光信号への変換指令、あるいは、光信号から所定の電気信号への変換指令を出して動作せしめるもので、例えば上記指令を形成する動作回路などを内蔵するICチップなどの電子部品が用いられる。また、互いに導通する動作素子と光素子とは、両者同数の形態に限らす、複数の光素子に対して個別に異なる指令を出し得る1つの動作素子を用いる形態としても良い。
Furthermore, the present invention provides a wiring board with an optical waveguide, wherein an operating element that is electrically connected to the optical element is mounted on the surface of the upper relaxation layer adjacent to the optical element and opposite to the optical waveguide. Item 3) is also included.
The operating element is a device that operates an optical element that is electrically connected to the optical element by issuing a conversion command from an electrical signal to a predetermined optical signal or a conversion command from an optical signal to a predetermined electrical signal. An electronic component such as an IC chip that incorporates an operation circuit for forming the command is used. Further, the operating elements and the optical elements that are electrically connected to each other are not limited to the same number of forms, and may be configured to use one operating element that can individually give different commands to a plurality of optical elements.

前記光導波路付き配線基板(請求項1)によれば、光導波路と絶縁性基板との間および当該光導波路の上方に両者の熱膨張率の中間の熱膨張率を有する下緩和層および上緩和層が個別に配置される。このため、熱膨張しにくい絶縁性基板と熱膨張し易い光導波路の間は基より、かかる光導波路と上緩和層との間における応力を低減して緩和することができる。従って、温度変化を伴う環境下で長期間にわたり使用する場合や、光導波路の上方に熱膨張率の低い光素子など実装する場合でも、光導波路の変形やクラックなどを防止できるため、安定した光信号の授受が可能となり、信頼性の高い光導波路付き配線基板とすることが可能となる。   According to the wiring substrate with an optical waveguide (Claim 1), the lower relaxation layer and the upper relaxation layer having a thermal expansion coefficient intermediate between the thermal expansion coefficients between the optical waveguide and the insulating substrate and above the optical waveguide. The layers are arranged individually. For this reason, the stress between the optical waveguide and the upper relaxation layer can be reduced and relaxed between the insulating substrate that is unlikely to thermally expand and the optical waveguide that is likely to be thermally expanded. Therefore, even when used for a long period of time in an environment with temperature changes, or when mounting an optical element with a low coefficient of thermal expansion above the optical waveguide, it is possible to prevent deformation and cracking of the optical waveguide, so stable light Signals can be exchanged, and a highly reliable wiring board with an optical waveguide can be obtained.

また、前記光導波路付き配線基板(請求項2)によれば、絶縁性基板と光導波路との間に両者の熱膨張率の中間の熱膨張率である下緩和層が位置し、且つ光導波路と光素子との間に両者の熱膨張率の中間の熱膨張率である上緩和層が位置しているため、厚み方向において段階的な熱膨張構造となる。従って、温度変化を伴う環境下において長期間使用しても、光導波路に応力が加わりにくなるため、変形やクラックなどを防止でき、安定した光信号の授受が可能となる。   According to the wiring substrate with an optical waveguide (claim 2), the lower relaxation layer having a thermal expansion coefficient intermediate between the thermal expansion coefficients of the insulating substrate and the optical waveguide is located, and the optical waveguide Since the upper relaxation layer, which has a thermal expansion coefficient intermediate between the thermal expansion coefficients of both, is positioned between the optical element and the optical element, a stepwise thermal expansion structure is formed in the thickness direction. Therefore, even if the optical waveguide is used for a long time in an environment with temperature changes, stress is not applied to the optical waveguide, so that deformation and cracks can be prevented, and stable transmission and reception of optical signals becomes possible.

更に、前記光導波路付き配線基板(請求項3)によれば、光導波路の上方に光素子と共にこれを動作せしめる動作素子が実装されるため、光素子および光導波路を介して光信号の伝送を確実に行える。また、動作素子の熱膨張率が前記絶縁性基板のそれと同等であっても、光導波路に対して応力を加えにくくできる。   Furthermore, according to the wiring board with an optical waveguide (claim 3), since the operating element for operating the optical element is mounted above the optical waveguide, an optical signal can be transmitted through the optical element and the optical waveguide. It can be done reliably. Further, even if the thermal expansion coefficient of the operating element is equal to that of the insulating substrate, it is difficult to apply stress to the optical waveguide.

以下において、本発明を実施するための形態について説明する。
図1は、本発明における1形態の光導波路付き配線基板K1の断面を示す。
かかる光導波路付き配線基板K1は、図1に示すように、平坦な表面2を有する絶縁性基板1、かかる表面2の上方に配置され且つ熱膨張率が絶縁性基板1よりも高い光導波路C、かかる光導波路Cと上記絶縁性基板1と間に形成される下緩和層11、および上記光導波路Cの上方に形成される上緩和層26を備える。かかる下緩和層11および上緩和層26の熱膨張率は、上記絶縁性基板1と光導波路Cとの中間である。
Hereinafter, modes for carrying out the present invention will be described.
FIG. 1 shows a cross section of a wiring board K1 with an optical waveguide according to one embodiment of the present invention.
As shown in FIG. 1, the wiring substrate K1 with an optical waveguide includes an insulating substrate 1 having a flat surface 2 and an optical waveguide C disposed above the surface 2 and having a higher thermal expansion coefficient than the insulating substrate 1. The lower relaxation layer 11 formed between the optical waveguide C and the insulating substrate 1 and the upper relaxation layer 26 formed above the optical waveguide C are provided. The thermal expansion coefficients of the lower relaxation layer 11 and the upper relaxation layer 26 are intermediate between the insulating substrate 1 and the optical waveguide C.

図1に示すように、絶縁性基板1は、熱膨張率が約6ppm/Kのガラス−セラミック、熱膨張率が約7ppm/Kのアルミナ、または熱膨張率が約4.5ppm/Kの窒化アルミニウム(AlN)からなるセラミック層S1〜S4を積層したものである。かかる絶縁性基板1の表面2、裏面3、およびセラミック層S1〜S4の間には、Agなどからなる所定パターンの配線層6〜8などが形成されている。尚、裏面3の配線層10は、接続端子(表面電極)である。
また、配線層6〜10は、セラミック層S1〜S4を貫通するAgなどからなるビア導体vを介して接続されている。尚、セラミック層S1〜S4の厚みは、約0.2mm、配線層6などの厚みは、約15μmである。また、絶縁性基板1は、4枚のグリーンシートやその表面に印刷などにより所定パターンで形成した導電性ペーストなどを用いて、公知の製造方法で形成したものである。
As shown in FIG. 1, the insulating substrate 1 is made of glass-ceramic having a thermal expansion coefficient of about 6 ppm / K, alumina having a thermal expansion coefficient of about 7 ppm / K, or nitriding having a thermal expansion coefficient of about 4.5 ppm / K. Ceramic layers S1 to S4 made of aluminum (AlN) are laminated. Between the front surface 2, the back surface 3, and the ceramic layers S1 to S4 of the insulating substrate 1, wiring layers 6 to 8 having a predetermined pattern made of Ag or the like are formed. The wiring layer 10 on the back surface 3 is a connection terminal (surface electrode).
The wiring layers 6 to 10 are connected via via conductors v made of Ag or the like penetrating the ceramic layers S1 to S4. The ceramic layers S1 to S4 have a thickness of about 0.2 mm, and the wiring layer 6 has a thickness of about 15 μm. Further, the insulating substrate 1 is formed by a known manufacturing method using four green sheets or a conductive paste formed on the surface thereof in a predetermined pattern by printing or the like.

図1に示すように、光導波路Cは、断面矩形のクラッド20と、かかるクラッド20に内蔵された断面正方形を呈する複数のコア22との2重構造体であり、左右の両端には45度の反射ミラー面24が対称に形成されている。かかるクラッド20およびコア22は、熱膨張率が約70〜90ppm/Kのアクリル系樹脂(例えばPMMA)、熱膨張率が約60〜70ppm/Kのエポキシ系樹脂、または熱膨張率が約100〜120ppm/Kのポリシラン系樹脂からなり、光の屈折率においてクラッド20は、コア22よりも約0.3〜5%低い。
尚、コア22の一辺は、約50μmである。また、反射ミラー面24は、光の反射が可能な範囲で、30〜60度の傾斜角が適宜選定される。
As shown in FIG. 1, the optical waveguide C is a double structure of a clad 20 having a rectangular cross section and a plurality of cores 22 having a square cross section built in the clad 20. The reflecting mirror surfaces 24 are formed symmetrically. The clad 20 and the core 22 have an acrylic resin (for example, PMMA) having a thermal expansion coefficient of about 70 to 90 ppm / K, an epoxy resin having a thermal expansion coefficient of about 60 to 70 ppm / K, or a thermal expansion coefficient of about 100 to 100 ppm. It consists of 120 ppm / K polysilane resin, and the clad 20 is about 0.3-5% lower than the core 22 in the refractive index of light.
Note that one side of the core 22 is about 50 μm. In addition, the reflection mirror surface 24 is appropriately selected with an inclination angle of 30 to 60 degrees within a range where light can be reflected.

図1に示すように、絶縁性基板1の表面2上には、厚みが約40μmの下緩和層11が形成され、かかる下緩和層11の表面12に上記光導波路Cが形成されている。かかる光導波路Cを除いた表面12上には、接続端子の配線4と、接続配線5とが形成され、配線4と前記絶縁性基板1の配線層6との間は、かかる下緩和層11を貫通するビア導体vを介して接続されている。光導波路Cは、下緩和層11の表面12に直に接着するか、かかる表面12に立設する図示しない複数の金属ピンを貫通させることで位置固定されている。
図1に示すように、両端の反射ミラー面24付近を除く光導波路Cの上方には、厚みが約40μmの上緩和層26が形成されている。下緩和層11および上緩和層26は、例えばエポキシ系またはエポキシアクリレート系樹脂やワニスをスピンコートして硬化したものであり、それらの熱膨張率は、絶縁性基板1と光導波路Cとの中間(約20〜65ppm/K)である。
As shown in FIG. 1, a lower relaxation layer 11 having a thickness of about 40 μm is formed on the surface 2 of the insulating substrate 1, and the optical waveguide C is formed on the surface 12 of the lower relaxation layer 11. On the surface 12 excluding the optical waveguide C, the connection terminal wiring 4 and the connection wiring 5 are formed, and the lower relaxation layer 11 is provided between the wiring 4 and the wiring layer 6 of the insulating substrate 1. Are connected via via conductors v penetrating through. The optical waveguide C is fixed in position by directly adhering to the surface 12 of the lower relaxation layer 11 or by penetrating a plurality of metal pins (not shown) standing on the surface 12.
As shown in FIG. 1, an upper relaxation layer 26 having a thickness of about 40 μm is formed above the optical waveguide C excluding the vicinity of the reflection mirror surfaces 24 at both ends. The lower relaxation layer 11 and the upper relaxation layer 26 are, for example, those obtained by spin-coating an epoxy or epoxy acrylate resin or varnish, and their thermal expansion coefficient is intermediate between the insulating substrate 1 and the optical waveguide C. (About 20 to 65 ppm / K).

図1に示すように、左側の配線4と接続配線5の一端とに、ハンダhを介してICチップ(動作素子)14aの接続端子13,15を接続することで、かかるICチップ14aを上緩和層11の表面12上に実装している。また、接続配線5の他端にハンダhを介して発光素子(光素子)16の接続端子17を接続することで、かかる発光素子16を表面12上に実装している。尚、発光素子16の図示しない発光部は、光導波路Cの左端の反射ミラー面24の真上に位置している。
図1に示すように、右側の配線4と接続配線5の一端とに、ハンダhを介してICチップ(動作素子)14bの接続端子13,15を接続することで、かかるICチップ14bを上緩和層11の表面12上に実装している。また、接続配線5の他端にハンダhを介して受光素子(光素子)18の接続端子19を接続することで、かかる受光素子18を表面12上に実装している。尚、受光素子18の図示しない受光部は、光導波路Cの右端の反射ミラー面24の真上に位置している。
As shown in FIG. 1, the connection terminals 13 and 15 of the IC chip (operation element) 14a are connected to the left wiring 4 and one end of the connection wiring 5 via the solder h, so that the IC chip 14a is It is mounted on the surface 12 of the relaxation layer 11. Further, the light emitting element 16 is mounted on the surface 12 by connecting the connection terminal 17 of the light emitting element (optical element) 16 to the other end of the connection wiring 5 via the solder h. Note that a light emitting portion (not shown) of the light emitting element 16 is located immediately above the reflection mirror surface 24 at the left end of the optical waveguide C.
As shown in FIG. 1, the connection terminals 13 and 15 of the IC chip (operation element) 14b are connected to the right wiring 4 and one end of the connection wiring 5 through the solder h, so that the IC chip 14b is It is mounted on the surface 12 of the relaxation layer 11. Further, the light receiving element 18 is mounted on the surface 12 by connecting the connection terminal 19 of the light receiving element (optical element) 18 to the other end of the connection wiring 5 via the solder h. A light receiving portion (not shown) of the light receiving element 18 is located right above the reflection mirror surface 24 at the right end of the optical waveguide C.

ICチップ14a,14bは、配線4やビア導体vなどを介して、絶縁性基板1内から所要の電力を予め供給されている。図1で左側のICチップ14aは、所定の動作を指示する電気信号を、接続配線5、ハンダh、および接続端子17を介して、発光素子16に伝送する。そして、図1中の矢印で示すように、発光素子16から発光された光信号は、左側の反射ミラー面24に反射して光導波路Cのコア22中をその周面に多重反射しつつ右方向に伝送される。かかる光信号は、コア22中から右側の反射ミラー面24に反射して、受光素子18に伝送され、電気信号に変換された後、接続配線5などを経て右側のICチップ14bに伝送される。この結果、ICチップ14a,14b間の信号伝送を、上記経路で且つ光信号を介して高速度で行うことができる。   The IC chips 14a and 14b are supplied with necessary power in advance from the insulating substrate 1 through the wiring 4, via conductors v, and the like. The left IC chip 14 a in FIG. 1 transmits an electrical signal instructing a predetermined operation to the light emitting element 16 through the connection wiring 5, the solder h, and the connection terminal 17. Then, as indicated by the arrows in FIG. 1, the optical signal emitted from the light emitting element 16 is reflected by the left reflecting mirror surface 24, and the right inside the core 22 of the optical waveguide C is subjected to multiple reflections on its peripheral surface. Transmitted in the direction. Such an optical signal is reflected from the core 22 to the right reflecting mirror surface 24, transmitted to the light receiving element 18, converted into an electrical signal, and then transmitted to the right IC chip 14b through the connection wiring 5 and the like. . As a result, signal transmission between the IC chips 14a and 14b can be performed at a high speed through the above path and through the optical signal.

尚、図1において、ICチップ14a,14bおよび発光素子16と受光素子18とを、それぞれ左右反対に配置(実装)することで、上記と反対の経路で光信号を介したICチップ14a,14b間の信号伝送を高速度行うこともできる。
また、図1において、ICチップ14a,14bの奥行き方向に隣接して新たなICチップ14b,14aを前記同様に配置(実装)し、且つ発光素子16および受光素子18の奥行き方向に隣接して新たな受光素子18および発光素子16を前記同様に配置しても良い。かかる複数組のICチップ14a,14b、発光素子16、および受光素子18と、光導波路Cの複数のコア22とにより、図1で左右の双方から電気信号を光信号を介して反対側に高速度で伝送可能となる。
In FIG. 1, the IC chips 14a and 14b and the light-emitting elements 16 and the light-receiving elements 18 are arranged (mounted) opposite to each other on the left and right sides, so that the IC chips 14a and 14b via the optical signal through the opposite path. The signal transmission between them can be performed at a high speed.
Further, in FIG. 1, new IC chips 14b and 14a are arranged (mounted) in the same manner as described above adjacent to the depth direction of the IC chips 14a and 14b, and adjacent to the light emitting element 16 and the light receiving element 18 in the depth direction. New light receiving elements 18 and light emitting elements 16 may be arranged in the same manner as described above. With the plurality of sets of IC chips 14a and 14b, the light emitting element 16, the light receiving element 18, and the plurality of cores 22 of the optical waveguide C, an electric signal is transmitted from both the left and right sides in FIG. Transmission at speed is possible.

以上のような光信号を伝送する光導波路Cを用いる高速度の信号伝送を、温度変化を伴う環境下で長期間にわたり行っても、かかる光導波路Cと絶縁性基板1との間に下緩和層11が位置し、且つ当該光導波路Cの上方に上緩和層26が位置しているため、光導波路Cに加わる応力が確実に緩和される。即ち、熱膨張し易い光導波路Cは、熱膨張しにくい絶縁性基板1との間の下緩和層11により受ける応力を低減されるだけでなく、それらと反対側の上緩和層26によっても受ける応力が相殺されて低減される。このため、光導波路Cのクラッド20やコア22に変形や割れが生じにくくなり、安定した光信号の伝送が可能となるため、信頼性の高い光導波路付き配線基板K1となる。
尚、光導波路付き配線基板K1は、その絶縁性基板1の裏面3に設けた配線層10を介して、図示しないマザーボードなどのプリント基板上に実装される。
Even if high-speed signal transmission using the optical waveguide C for transmitting an optical signal as described above is performed over a long period of time in an environment with a temperature change, the lower relaxation occurs between the optical waveguide C and the insulating substrate 1. Since the layer 11 is located and the upper relaxation layer 26 is located above the optical waveguide C, the stress applied to the optical waveguide C is reliably relaxed. That is, the optical waveguide C that is easily thermally expanded is not only reduced in stress received by the lower relaxation layer 11 between the insulating substrate 1 that is less likely to thermally expand, but is also received by the upper relaxation layer 26 on the opposite side thereof. Stress is offset and reduced. For this reason, the clad 20 and the core 22 of the optical waveguide C are less likely to be deformed and cracked, and stable optical signal transmission is possible, so that the wiring substrate K1 with an optical waveguide having high reliability is obtained.
The wiring board K1 with an optical waveguide is mounted on a printed board such as a mother board (not shown) through a wiring layer 10 provided on the back surface 3 of the insulating substrate 1.

図2は、前記配線基板K1の変形形態である光導波路付き配線基板K2の断面を示す。かかる配線基板K2は、図2に示すように、絶縁性基板30と、その表面(第1主面)42aに形成された下緩和層46と、その表面46aの中央付近に形成された光導波路Cと、かかる光導波路Cの両端部を除く上方に形成された上緩和層26と、を備えている。
図2に示すように、絶縁性基板30は、熱膨張率が約15ppm/Kの例えばエポキシ系樹脂とガラスクロスの複合材料とからなるコア基板31、その表面32上方に形成した絶縁層38,42、およびコア基板31の裏面33に形成したソルダーレジスト層(絶縁層)39を含んでいる。コア基板31は、厚みが約0.8mmで、その表面32と裏面33との間を貫通する複数のスルーホール34には、ほぼ円筒形で銅メッキ膜からなるスルーホール導体35が個別に形成され、かかるスルーホール導体35の内側に充填樹脂36が形成されている。
FIG. 2 shows a cross section of a wiring board K2 with an optical waveguide, which is a modification of the wiring board K1. As shown in FIG. 2, the wiring substrate K2 includes an insulating substrate 30, a lower relaxation layer 46 formed on the surface (first main surface) 42a, and an optical waveguide formed near the center of the surface 46a. C and an upper relaxation layer 26 formed above except for both ends of the optical waveguide C.
As shown in FIG. 2, the insulating substrate 30 includes a core substrate 31 made of, for example, a composite material of epoxy resin and glass cloth having a thermal expansion coefficient of about 15 ppm / K, an insulating layer 38 formed above the surface 32, 42 and a solder resist layer (insulating layer) 39 formed on the back surface 33 of the core substrate 31. The core substrate 31 has a thickness of about 0.8 mm, and a plurality of through holes 34 penetrating between the front surface 32 and the back surface 33 are individually formed with through-hole conductors 35 made of a copper plating film in a substantially cylindrical shape. A filling resin 36 is formed inside the through-hole conductor 35.

図2に示すように、コア基板31の表面32には、銅メッキ膜からなり且つ所定パターンを有する配線層40が形成され、前記スルーホール導体35の上端と導通している。また、絶縁層38,42間には、上記同様の配線層44が、絶縁層42と上緩和層46との間には、上記同様の配線層48が形成されている。更に、配線層40,44,48間は、絶縁層38,42に形成したフィルドビア導体v(以下、ビア導体vとする)を介して導通されている。尚、絶縁層38,42の厚みは約40μmであり、配線層40などの厚みは約15μmである。
一方、図2に示すように、コア基板31の裏面33には、銅メッキ膜からなる所定パターンの配線層41が形成され、かかる配線層41は、前記スルーホール導体35の下端と接続されている。かかる配線層41と裏面33の下方には、厚みが約30μmのソルダーレジスト層39が形成され、その表面(第2主面)49に開口する開口部43の底面には、上記配線層41から延びた配線45が位置する。かかる配線(接続端子)45は、その表面にNiメッキおよびAuメッキが被覆され、図示しないマザーボードなどのプリント基板との接続に活用される。
As shown in FIG. 2, a wiring layer 40 made of a copper plating film and having a predetermined pattern is formed on the surface 32 of the core substrate 31 and is electrically connected to the upper end of the through-hole conductor 35. A wiring layer 44 similar to the above is formed between the insulating layers 38 and 42, and a wiring layer 48 similar to the above is formed between the insulating layer 42 and the upper relaxation layer 46. Further, the wiring layers 40, 44 and 48 are electrically connected via a filled via conductor v (hereinafter referred to as a via conductor v) formed in the insulating layers 38 and 42. The insulating layers 38 and 42 have a thickness of about 40 μm, and the wiring layer 40 has a thickness of about 15 μm.
On the other hand, as shown in FIG. 2, a wiring layer 41 having a predetermined pattern made of a copper plating film is formed on the back surface 33 of the core substrate 31, and the wiring layer 41 is connected to the lower end of the through-hole conductor 35. Yes. A solder resist layer 39 having a thickness of about 30 μm is formed below the wiring layer 41 and the back surface 33, and the bottom surface of the opening 43 opening on the surface (second main surface) 49 is formed from the wiring layer 41. The extended wiring 45 is located. The wiring (connection terminal) 45 is coated with Ni plating and Au plating on its surface, and is used for connection to a printed board such as a mother board (not shown).

下緩和層46は、厚みが約40μmで、エポキシ系の樹脂フィルムを貼り付けるか、ワニスをスピンコートした後で硬化させたもので、図2に示すように、かかる下緩和層46の表面46a上の左右の両端部には、銅メッキ膜からなる接続端子の配線47が形成され、上記配線層48とフィルドビア導体vを介して導通されている。左右の各配線47に隣接する表面46a上には、銅メッキ膜からなる前記同様の接続配線5がそれぞれ形成されている。
また、図2に示すように、下緩和層46の表面46aの中央付近には、前記同様の光導波路Cが配置されている。かかる光導波路Cの反射ミラー面24を含む両端部を除いた上方には、前記同様の上緩和層26が形成されている。尚、下緩和層46、配線47、接続配線5、および前記絶縁性基板30は、公知のセミアデティブ法、サブトラクティブ法、フォトリソグラフィ技術などで形成される。
The lower relaxation layer 46 has a thickness of about 40 μm and is cured after an epoxy resin film is attached or varnish is spin-coated, and as shown in FIG. 2, the surface 46a of the lower relaxation layer 46 is formed. On both the left and right upper ends, connection terminal wiring 47 made of a copper plating film is formed, and is electrically connected to the wiring layer 48 via the filled via conductor v. On the surface 46a adjacent to the left and right wirings 47, the same connection wirings 5 made of a copper plating film are formed.
Further, as shown in FIG. 2, an optical waveguide C similar to the above is disposed near the center of the surface 46 a of the lower relaxation layer 46. An upper relaxation layer 26 similar to the above is formed above the optical waveguide C except for both ends including the reflection mirror surface 24. The lower relaxation layer 46, the wiring 47, the connection wiring 5, and the insulating substrate 30 are formed by a known semi-additive method, subtractive method, photolithography technique, or the like.

図2に示すように、左側の配線47と接続配線5の一端とに、ハンダhを介してICチップ(動作素子)14aの接続端子13,15を接続することで、かかるICチップ14aを上緩和層46の表面46a上に実装している。また、接続配線5の他端にハンダhを介して発光素子(光素子)16の接続端子17を接続することで、かかる発光素子16を表面46a上に実装している。尚、発光素子16の発光部は、光導波路Cの左端の反射ミラー面24の真上に位置している。
図2に示すように、右側の配線47と接続配線5の一端とに、ハンダhを介してICチップ(動作素子)14bの接続端子13,15を接続することで、かかるICチップ14bを上緩和層46の表面上46aに実装している。また、接続配線5の他端にハンダhを介して受光素子(光素子)18の接続端子19を接続することで、かかる受光素子18を表面46a上に実装している。尚、受光素子18の受光部は、光導波路Cの右端の反射ミラー面24の真上に位置している。
上記ICチップ14aおよび発光素子16とICチップ14bおよび受光素子18とは、互いに隣接し且つ光導波路Cを含めて平面視で直線状に配列される。
As shown in FIG. 2, the connection terminals 13 and 15 of the IC chip (operation element) 14a are connected to the left wiring 47 and one end of the connection wiring 5 via the solder h, so that the IC chip 14a is It is mounted on the surface 46 a of the relaxation layer 46. Further, the light emitting element 16 is mounted on the surface 46a by connecting the connection terminal 17 of the light emitting element (optical element) 16 to the other end of the connection wiring 5 via the solder h. Note that the light emitting portion of the light emitting element 16 is positioned directly above the reflection mirror surface 24 at the left end of the optical waveguide C.
As shown in FIG. 2, the connection terminals 13 and 15 of the IC chip (operation element) 14b are connected to the right wiring 47 and one end of the connection wiring 5 through the solder h, so that the IC chip 14b is It is mounted on the surface 46 a of the relaxation layer 46. Further, the light receiving element 18 is mounted on the surface 46a by connecting the connection terminal 19 of the light receiving element (optical element) 18 to the other end of the connection wiring 5 via the solder h. The light receiving portion of the light receiving element 18 is located immediately above the right reflecting mirror surface 24 of the optical waveguide C.
The IC chip 14 a and the light emitting element 16, the IC chip 14 b and the light receiving element 18 are adjacent to each other and arranged linearly in plan view including the optical waveguide C.

ICチップ14a,14bは、配線47やビア導体vなどを介して、絶縁性基板30内から所要の電力を予め供給されている。図2で左側のICチップ14aは、所定の動作を指示する電気信号を、接続配線5、ハンダh、および接続端子17を介して、発光素子16に伝送する。そして、図2中の矢印で示すように、発光素子16から発光された光信号は、左側の反射ミラー面24に反射して光導波路Cのコア22中をその周面に多重反射しつつ右方向に伝送される。かかる光信号は、コア22中から右側の反射ミラー面24に反射して、受光素子18に伝送され、電気信号に変換された後、接続配線5などを経て右側のICチップ14bに伝送される。この結果、ICチップ14a,14b間の信号伝送を、上記経路で光信号を介して高速度で行うことができる。   The IC chips 14a and 14b are supplied with necessary power in advance from the insulating substrate 30 via the wiring 47, the via conductors v, and the like. The left IC chip 14 a in FIG. 2 transmits an electrical signal instructing a predetermined operation to the light emitting element 16 via the connection wiring 5, the solder h, and the connection terminal 17. Then, as indicated by the arrows in FIG. 2, the optical signal emitted from the light emitting element 16 is reflected by the left reflecting mirror surface 24, and the right side of the optical waveguide C is reflected in the core 22 by multiple reflection on its peripheral surface. Transmitted in the direction. Such an optical signal is reflected from the core 22 to the right reflecting mirror surface 24, transmitted to the light receiving element 18, converted into an electrical signal, and then transmitted to the right IC chip 14b through the connection wiring 5 and the like. . As a result, signal transmission between the IC chips 14a and 14b can be performed at high speed via the optical signal in the above-described path.

尚、図2においても、ICチップ14a,14bおよび発光素子16と受光素子18とを、左右反対に配置(実装)することで、上記と反対の経路で光信号を介たしICチップ14a,14b間の信号伝送を高速度で行うこともできる。
また、図2においても、ICチップ14a,14bの奥行き方向に隣接して新たなICチップ14b,14aを前記同様に配置し、且つ発光素子16および受光素子18の奥行き方向に隣接して新たな受光素子18および発光素子16を前記同様に配置しても良い。かかる複数組のICチップ14a,14b、発光素子16、および受光素子18と、光導波路Cの複数のコア22とにより、図2にても左右の双方から電気信号を光信号を介して反対側に高速度で伝送可能となる。
Also in FIG. 2, the IC chips 14a and 14b and the light emitting element 16 and the light receiving element 18 are disposed (mounted) in the left and right directions so that the IC chip 14a, Signal transmission between 14b can also be performed at high speed.
Also in FIG. 2, new IC chips 14b and 14a are disposed in the same manner as described above adjacent to the depth direction of the IC chips 14a and 14b, and new light is provided adjacent to the light emitting element 16 and the light receiving element 18 in the depth direction. The light receiving element 18 and the light emitting element 16 may be arranged in the same manner as described above. With the plurality of sets of IC chips 14a and 14b, the light emitting element 16, the light receiving element 18, and the plurality of cores 22 of the optical waveguide C, electrical signals are transmitted from both the left and right sides in FIG. Can be transmitted at high speed.

以上のような光信号を伝送する光導波路Cを用いる高速度の信号伝送を、温度変化を伴う環境下で長期間行っても、かかる光導波路Cと絶縁性基板30との間に下緩和層46が位置し、且つ当該光導波路Cの上方に上緩和層26が位置しているため、光導波路Cに加わる応力が確実に緩和される。即ち、熱膨張率の高い光導波路Cは、熱膨張率の低い絶縁性基板30との間の下緩和層46で受ける応力を低減されるだけでなく、それらと反対側の上緩和層26によっも受ける応力を相殺して低減される。従って、光導波路Cのクラッド20やコア22に変形や割れが生じにくくなり、安定した光信号の伝送が可能となるため、信頼性の高い光導波路付き配線基板K2となる。   Even if high-speed signal transmission using the optical waveguide C for transmitting an optical signal as described above is performed for a long time in an environment with temperature change, a lower relaxation layer is provided between the optical waveguide C and the insulating substrate 30. Since the upper relaxation layer 26 is located above the optical waveguide C, the stress applied to the optical waveguide C is reliably relaxed. That is, the optical waveguide C having a high coefficient of thermal expansion not only reduces the stress received by the lower relaxation layer 46 between the insulating substrate 30 having a lower coefficient of thermal expansion but also the upper relaxation layer 26 on the opposite side thereof. However, it is reduced by offsetting the stress received. Therefore, the clad 20 and the core 22 of the optical waveguide C are not easily deformed or cracked, and stable optical signal transmission is possible, so that the wiring substrate K2 with an optical waveguide having high reliability is obtained.

図3は、異なる形態の光導波路付き配線基板K3の断面を示す。かかる配線基板K3は、図3に示すように、前記同様の絶縁性基板1と、その表面2上に形成した下緩和層50と、その表面51上の中央付近に配置した前記同様の光導波路Cと、かかる光導波路Cおよび下緩和層50の左右の表面51の上方に形成した上緩和層52と、を備えている。上緩和層52の表面53上方には、ICチップ(動作素子)56,60と発光素子64および受光素子67とが実装されている。
下緩和層50も前記下緩和層11などと同様の厚みおよび特性を有する。上緩和層52は、下緩和層50よりも厚肉で、図3に示すように、光導波路Cの側面および上面を覆い、光導波路Cの反射ミラー面24の真上付近に一対の透孔54,55を形成している。かかる上緩和層52も前記同様の特性を有する。
FIG. 3 shows a cross section of a wiring board K3 with an optical waveguide having a different form. As shown in FIG. 3, the wiring substrate K3 includes the same insulating substrate 1, the lower relaxation layer 50 formed on the surface 2, and the same optical waveguide disposed near the center on the surface 51. C and an upper relaxation layer 52 formed above the left and right surfaces 51 of the optical waveguide C and the lower relaxation layer 50. Above the surface 53 of the upper relaxing layer 52, IC chips (operation elements) 56 and 60, a light emitting element 64 and a light receiving element 67 are mounted.
The lower relaxation layer 50 has the same thickness and characteristics as the lower relaxation layer 11 and the like. The upper relaxation layer 52 is thicker than the lower relaxation layer 50 and covers the side surface and the upper surface of the optical waveguide C as shown in FIG. 3, and a pair of through-holes near the reflection mirror surface 24 of the optical waveguide C. 54 and 55 are formed. The upper relaxation layer 52 has the same characteristics as described above.

図3に示すように、上緩和層52の表面53上の両端付近には、Cuなどからなる前記同様の配線4がそれぞれ形成され、上・下緩和層52,50を貫通するビア導体vを介して、絶縁性基板1の配線層6と接続されている。上記表面53上における左右の両端付近には、配線4に隣接し且つ透孔54,55との間に前記同様の接続配線5がそれぞれ形成されている。
図3に示すように、左側の配線4と接続配線5の一端とに、図示しないハンダを介してICチップ(動作素子)56の接続端子57,58を接続することで、かかるICチップ56を上緩和層52の表面53上に実装している。また、接続配線5の他端にハンダを介して発光素子(光素子)64の接続端子65を接続し、且つ表面53上に突出する支持片66に先端部を支持することによって、かかる発光素子64を表面53上に実装している。
尚、上記発光素子64は、Si(熱膨張率:約3.6ppm/K)またはGaAs(熱膨張率:約6.0ppm/K)からなり、ICチップ56も同様である。また、発光素子64の図示しない発光部は、光導波路Cの左端の反射ミラー面24および透孔54の真上に位置している。
As shown in FIG. 3, the same wiring 4 made of Cu or the like is formed in the vicinity of both ends on the surface 53 of the upper relaxation layer 52, and the via conductors v penetrating the upper and lower relaxation layers 52 and 50 are provided. Through the wiring layer 6 of the insulating substrate 1. In the vicinity of both left and right ends on the surface 53, the same connection wiring 5 is formed adjacent to the wiring 4 and between the through holes 54 and 55, respectively.
As shown in FIG. 3, the connection terminals 57 and 58 of the IC chip (operation element) 56 are connected to the left wiring 4 and one end of the connection wiring 5 via solder (not shown), whereby the IC chip 56 is connected. It is mounted on the surface 53 of the upper relaxation layer 52. In addition, the connection terminal 65 of the light emitting element (optical element) 64 is connected to the other end of the connection wiring 5 via solder, and the tip portion is supported by the support piece 66 protruding on the surface 53, thereby the light emitting element. 64 is mounted on the surface 53.
The light emitting element 64 is made of Si (thermal expansion coefficient: about 3.6 ppm / K) or GaAs (thermal expansion coefficient: about 6.0 ppm / K), and the IC chip 56 is the same. Further, the light emitting portion (not shown) of the light emitting element 64 is located immediately above the reflection mirror surface 24 and the through hole 54 at the left end of the optical waveguide C.

図3に示すように、右側の配線4と接続配線5の一端とに、図示しないハンダを介してICチップ(動作素子)60の接続端子61,62を接続することで、かかるICチップ60を上緩和層52の表面53上に実装している。また、接続配線5の他端にハンダを介して受光素子(光素子)67の接続端子69を接続し、且つ表面53上に突出する支持片68に先端部を支持することで、かかる受光素子67を表面53上に実装している。尚、受光素子67の図示しない受光部は、光導波路Cの右端の反射ミラー面24および透孔55の真上に位置している。
尚、上記受光素子67も、Si(熱膨張率:約3.6ppm/K)またはGaAs(熱膨張率:約6.0ppm/K)からなり、ICチップ60も同様である。また、光導波路Cのクラッド20が断面長方形で且つその中に複数のコア22が平行に内蔵されている場合、透孔54,55は、かかる複数のコア22と直交する平面視で長方形の形態とするほか、各コア22の反射ミラー面24ごとにほぼ正方形とした複数個の形態としても良い。
As shown in FIG. 3, the connection terminals 61 and 62 of the IC chip (operation element) 60 are connected to the right wiring 4 and one end of the connection wiring 5 via solder (not shown), whereby the IC chip 60 is connected. It is mounted on the surface 53 of the upper relaxation layer 52. Further, a connection terminal 69 of a light receiving element (optical element) 67 is connected to the other end of the connection wiring 5 via solder, and the tip end portion is supported by a support piece 68 protruding on the surface 53, whereby the light receiving element. 67 is mounted on the surface 53. A light receiving portion (not shown) of the light receiving element 67 is located right above the reflection mirror surface 24 and the through hole 55 at the right end of the optical waveguide C.
The light receiving element 67 is also made of Si (thermal expansion coefficient: about 3.6 ppm / K) or GaAs (thermal expansion coefficient: about 6.0 ppm / K), and the IC chip 60 is the same. Further, when the clad 20 of the optical waveguide C has a rectangular cross section and a plurality of cores 22 are incorporated in parallel therein, the through holes 54 and 55 have a rectangular shape in a plan view orthogonal to the plurality of cores 22. In addition, a plurality of forms may be used in which each reflection mirror surface 24 of each core 22 is substantially square.

ICチップ56,60は、配線4やビア導体vなどを介して、絶縁性基板1内から所要の電力を予め供給されている。図3で左側のICチップ56は、所定の動作を指示する電気信号を、接続配線5、ハンダ、および接続端子65を介して、発光素子64に伝送する。
そして、図3中の矢印で示すように、発光素子64から発光された光信号は、透孔54を経て、左側の反射ミラー面24に反射して光導波路Cのコア22中をその周面に多重反射しつつ右方向に伝送される。かかる光信号は、コア22中から右側の反射ミラー面24に反射し、透孔55を経て受光素子67に伝送され、電気信号に変換された後、接続配線5などを経て右側のICチップ60に伝送される。従って、ICチップ56,60間の信号伝送を、上記経路における光信号を介して高速度で行える。
The IC chips 56 and 60 are supplied with required power in advance from the inside of the insulating substrate 1 through the wiring 4 and the via conductors v. The left IC chip 56 in FIG. 3 transmits an electrical signal instructing a predetermined operation to the light emitting element 64 through the connection wiring 5, the solder, and the connection terminal 65.
3, the optical signal emitted from the light emitting element 64 passes through the through hole 54 and is reflected by the left reflecting mirror surface 24 to pass through the core 22 of the optical waveguide C. Are transmitted in the right direction with multiple reflections. The optical signal is reflected from the core 22 to the right reflecting mirror surface 24, transmitted to the light receiving element 67 through the through hole 55, converted into an electric signal, and then connected to the right IC chip 60 through the connection wiring 5 and the like. Is transmitted. Therefore, signal transmission between the IC chips 56 and 60 can be performed at a high speed via the optical signal in the path.

尚、図3において、ICチップ56,60および発光素子64と受光素子67とを、それぞれ左右反対に配置(実装)することで、上記と反対の経路で光信号を介したICチップ56,60間の信号伝送を高速度行うこともできる。
また、図3において、ICチップ56,60の奥行き方向に隣接して新たなICチップ60,56を前記同様に配置(実装)し、且つ発光素子64および受光素子67の奥行き方向に隣接して新たな受光素子67および発光素子64を前記同様に配置しても良い。かかる複数組のICチップ56,60、発光素子64、および受光素子67と、光導波路Cの複数のコア22とにより、図3にて左右の双方から電気信号を光信号を介して反対側に高速度で伝送可能となる。
In FIG. 3, the IC chips 56, 60 and the light emitting elements 64 and the light receiving elements 67 are arranged (mounted) opposite to each other on the left and right sides, so that the IC chips 56, 60 via the optical signal through the opposite path. The signal transmission between them can be performed at a high speed.
In FIG. 3, new IC chips 60 and 56 are disposed (mounted) in the same manner as described above adjacent to the depth direction of the IC chips 56 and 60, and adjacent to the light emitting element 64 and the light receiving element 67 in the depth direction. New light receiving elements 67 and light emitting elements 64 may be arranged in the same manner as described above. With the plurality of sets of IC chips 56 and 60, the light emitting element 64 and the light receiving element 67, and the plurality of cores 22 of the optical waveguide C, electric signals are transmitted from the left and right sides to the opposite side via optical signals in FIG. Transmission at high speed is possible.

以上のような光導波路付き配線基板K3によれば、最も高い熱膨張率の光導波路Cに隣接して中間的な熱膨張率の下緩和層50および上緩和層52が位置し、且つこれらを介して最も熱膨張率が低い絶縁性基板1や発光素子64および受光素子67などが配置された厚み方向において段階的な熱膨張構造となっている。このため、温度変化を伴う環境下で長期間使用しても、光導波路Cには応力が加わりにくくなると共に、発光素子64および受光素子67の実装時およびその後にても実装位置ずれが生じにくなる。また、光導波路Cは、上緩和層52に覆われているため、そのクラッド20やコア22が吸水しにくくなり、その屈折率が安定する。従って、光導波路Cのクラッド20やコア22に変形や割れが生じにくくなり、安定した光信号の伝送が可能となるため、信頼性が一層高まる。   According to the wiring substrate with optical waveguide K3 as described above, the lower relaxation layer 50 and the upper relaxation layer 52 having an intermediate thermal expansion coefficient are located adjacent to the optical waveguide C having the highest thermal expansion coefficient, and these are Thus, a stepwise thermal expansion structure is formed in the thickness direction in which the insulating substrate 1, the light emitting element 64, the light receiving element 67 and the like having the lowest thermal expansion coefficient are disposed. For this reason, even if the optical waveguide C is used for a long time in an environment with a temperature change, it is difficult for stress to be applied to the optical waveguide C, and a mounting position shift occurs even when and after the light emitting element 64 and the light receiving element 67 are mounted. Become. Further, since the optical waveguide C is covered with the upper relaxation layer 52, the clad 20 and the core 22 are difficult to absorb water, and the refractive index is stabilized. Therefore, the cladding 20 and the core 22 of the optical waveguide C are less likely to be deformed or cracked, and stable optical signal transmission is possible, thereby further improving the reliability.

ここで、前記光導波路付き配線基板K3の製造方法について説明する。
予め、複数枚のグリーンシートおよびその表面などに印刷にて導電性ペーストのパターンなどを形成し、これらを積層し且つ焼成することで、図4の部分断面図で示すように、絶縁性基板1を製作しておく。
次に、図5に示すように、絶縁性基板1の表面2上に、エポキシ系樹脂フィルムの貼り付け、またはワニスをスピンコートし且つ硬化することで、熱膨張率が約20〜65ppm/Kで且つ前記厚みの下緩和層50を形成する。
Here, a method for manufacturing the wiring substrate with optical waveguide K3 will be described.
A conductive paste pattern or the like is formed by printing on a plurality of green sheets and the surface thereof in advance, and these are laminated and baked. Make.
Next, as shown in FIG. 5, the thermal expansion coefficient is about 20 to 65 ppm / K by attaching an epoxy resin film on the surface 2 of the insulating substrate 1 or spin-coating and curing a varnish. And the lower relaxation layer 50 of the said thickness is formed.

次いで、図6に示すように、下緩和層50の表面51上に光導波路Cを形成する。即ち、クラッド20およびコア22からなる複合樹脂材を表面51に配置し、その両端を光路変換構造とすることで、両端に反射ミラー面24を対称に有する光導波路C(厚み約150μm)を表面51上に形成できる。
更に、図7に示すように、下緩和層50の表面51上および光導波路Cの上に、エポキシアクリレート系のワニスをスピンコートすることにより、熱膨張率が約40〜50ppm/Kで且つ前記厚みの上緩和層52を形成する。尚、上緩和層52の厚みは、表面51上で約200μm、光導波路C上で約40μmである。
Next, as shown in FIG. 6, the optical waveguide C is formed on the surface 51 of the lower relaxation layer 50. That is, a composite resin material composed of the clad 20 and the core 22 is arranged on the surface 51, and both ends thereof have an optical path conversion structure, so that the optical waveguide C (thickness of about 150 μm) having the reflection mirror surfaces 24 symmetrically at both ends is provided on the surface. 51 can be formed.
Further, as shown in FIG. 7, by spin-coating an epoxy acrylate varnish on the surface 51 of the lower relaxation layer 50 and on the optical waveguide C, the coefficient of thermal expansion is about 40 to 50 ppm / K and An upper relaxation layer 52 having a thickness is formed. The thickness of the upper relaxing layer 52 is about 200 μm on the surface 51 and about 40 μm on the optical waveguide C.

次に、図8に示すように、上緩和層52における光導波路Cの一対の反射ミラー面24の真上付近に、公知のフォトリソグラフィ技術によって透孔54,55を形成する。併せて、上緩和層52および下緩和層50の両端付近に、レーザ加工によりスルーホールを形成し、その内壁に無電解銅メッキおよび電解銅メッキを施して、図8に示すように、前記配線層6に接続するビア導体vを形成する。
次いで、図9に示すように、透孔54,55の開口部に隣接して、公知のフォトリソグラフィ技術などにより、所要本数の接続配線5および所要数の配線4を形成する。また、これらと反対側の透孔54,55の開口部には、上緩和層52と同様な樹脂からなる支持片66,68が上記同様の技術によって突設される。
Next, as shown in FIG. 8, through holes 54 and 55 are formed in the upper relaxing layer 52 in the vicinity of the optical waveguide C just above the pair of reflecting mirror surfaces 24 by a known photolithography technique. In addition, through holes are formed by laser processing in the vicinity of both ends of the upper relaxation layer 52 and the lower relaxation layer 50, and electroless copper plating and electrolytic copper plating are applied to the inner walls thereof, as shown in FIG. A via conductor v connected to the layer 6 is formed.
Next, as shown in FIG. 9, a required number of connection wirings 5 and a required number of wirings 4 are formed adjacent to the openings of the through holes 54 and 55 by a known photolithography technique or the like. Further, support pieces 66 and 68 made of the same resin as that of the upper relaxing layer 52 are projected from the openings of the through holes 54 and 55 on the opposite side by the same technique as described above.

そして、図10に示すように、右側の配線4と接続配線5の一端とに、ハンダ(図示せず)を介してICチップ(動作素子)60の接続端子61,62を接続することで、かかるICチップ60を上緩和層52の表面53上に実装する。
また、接続配線5の他端にハンダを介して受光素子(光素子)67の接続端子69を接続し、且つ支持片68に先端部を支持することで、かかる受光素子67を表面53上に実装する。この際、受光素子67の受光部(図示せず)は、光導波路Cの右端の反射ミラー面24および透孔55の真上に位置している。
更に、図10に示すように、左側の配線4と接続配線5の一端とに、ハンダを介してICチップ(動作素子)56の接続端子57,58を接続することで、かかるICチップ56を上緩和層52の表面53上に実装する。また、接続配線5の他端にハンダを介して発光素子(光素子)64の接続端子65を接続し、且つ支持片66に先端部を支持することで、かかる発光素子64を表面53上に実装する。この際、発光素子64の発光部(図示せず)は、光導波路Cの左端の反射ミラー面24および透孔54の真上に位置している。
Then, as shown in FIG. 10, by connecting the connection terminals 61 and 62 of the IC chip (operation element) 60 to the right wiring 4 and one end of the connection wiring 5 through solder (not shown), Such an IC chip 60 is mounted on the surface 53 of the upper relaxation layer 52.
Further, the connection terminal 69 of the light receiving element (optical element) 67 is connected to the other end of the connection wiring 5 via solder, and the tip end portion is supported by the support piece 68, so that the light receiving element 67 is placed on the surface 53. Implement. At this time, the light receiving portion (not shown) of the light receiving element 67 is located immediately above the reflection mirror surface 24 and the through hole 55 at the right end of the optical waveguide C.
Further, as shown in FIG. 10, the connection terminals 57 and 58 of the IC chip (operation element) 56 are connected to the left wiring 4 and one end of the connection wiring 5 through solder, whereby the IC chip 56 is connected. It is mounted on the surface 53 of the upper relaxation layer 52. Further, the connection terminal 65 of the light emitting element (optical element) 64 is connected to the other end of the connection wiring 5 via solder, and the tip end portion is supported by the support piece 66, so that the light emitting element 64 is placed on the surface 53. Implement. At this time, the light emitting portion (not shown) of the light emitting element 64 is located immediately above the reflection mirror surface 24 and the through hole 54 at the left end of the optical waveguide C.

この結果、前記図3で示した光導波路付き配線基板K3を得ることができる。
尚、絶縁性基板1を前記樹脂からなる絶縁性基板30に置き換えて、以上のような各工程を経ることにより、全体がほぼ樹脂からなる上記配線基板K3と同様の光導波路付き配線基板を得ることも可能である。
As a result, the wiring substrate with optical waveguide K3 shown in FIG. 3 can be obtained.
In addition, by replacing the insulating substrate 1 with the insulating substrate 30 made of the resin and passing through the above-described steps, a wiring substrate with an optical waveguide similar to the wiring substrate K3, which is substantially made entirely of resin, is obtained. It is also possible.

本発明は、以上において説明した各形態に限定されるものではない。
例えば、前記光導波路Cは、断面正方形のクラッド20とその内側に断面正方形の1本のコア22とからなる形態としても良い。
また、光導波路は、マルチモードの前記光導波路Cのほか、シングルモードとしも良い。
更に、前記光導波路Cの素材は、前記アクリル樹脂などのほか、シロキサンポリマやフッ素ポリイミドとしても良い。
また、前記光導波路Cは、両端の前記反射ミラー面24を省略した直角の端面とし、かかる両端面に近接して鏡面の傾斜した反射ミラー面を有する断面三角形の反射材を配置しても良い。
更に、前記配線層6などやビア導体vは、前記AgやCuに限らず、W、Mo、Ag−Cu、Cu−Wなどの金属または合金としても良い。
加えて、前記絶縁性基板30を形成する前記ガラスクロスに替えて、樹脂繊維やその他の材料を適用しても良い。
The present invention is not limited to the embodiments described above.
For example, the optical waveguide C may be configured by a clad 20 having a square cross section and a single core 22 having a square cross section inside thereof.
The optical waveguide may be a single mode in addition to the multimode optical waveguide C.
Further, the material of the optical waveguide C may be siloxane polymer or fluorine polyimide in addition to the acrylic resin.
Further, the optical waveguide C may have a right-angled end surface from which the reflection mirror surfaces 24 at both ends are omitted, and a reflective member having a triangular cross section having a reflection mirror surface having a mirror surface in the vicinity of the both end surfaces. .
Further, the wiring layer 6 and the via conductor v are not limited to Ag and Cu, and may be a metal or alloy such as W, Mo, Ag—Cu, or Cu—W.
In addition, resin fibers and other materials may be applied instead of the glass cloth forming the insulating substrate 30.

本発明の光導波路付き配線基板の1形態を示す断面図。Sectional drawing which shows 1 form of the wiring board with an optical waveguide of this invention. 上記光導波路付き配線基板の変形形態を示す断面図。Sectional drawing which shows the deformation | transformation form of the said wiring board with an optical waveguide. 異なる形態の光導波路付き配線基板を示す断面図。Sectional drawing which shows the wiring board with an optical waveguide of a different form. 上記光導波路付き配線基板の製造工程を示す部分断面図。The fragmentary sectional view which shows the manufacturing process of the said wiring board with an optical waveguide. 図4に続く製造工程を示す部分断面図。The fragmentary sectional view which shows the manufacturing process following FIG. 図5に続く製造工程を示す部分断面図。FIG. 6 is a partial cross-sectional view illustrating a manufacturing process subsequent to FIG. 5. 図6に続く製造工程を示す部分断面図。FIG. 7 is a partial cross-sectional view illustrating a manufacturing process following FIG. 6. 図7に続く製造工程を示す部分断面図。FIG. 8 is a partial cross-sectional view illustrating a manufacturing process following FIG. 7. 図8に続く製造工程を示す部分断面図。FIG. 9 is a partial cross-sectional view illustrating a manufacturing process following FIG. 8. 図9に続く製造工程を示す部分断面図。FIG. 10 is a partial cross-sectional view showing the manufacturing process following FIG. 9.

符号の説明Explanation of symbols

1,30…………………………絶縁性基板
2,42a………………………表面
11,46,50………………下緩和層
14a,14b,56,60…ICチップ(動作素子)
16,64………………………発光素子(光素子)
18,67………………………受光素子(光素子)
24………………………………反射ミラー面
26,52………………………上緩和層
53………………………………上緩和層の表面
54,55………………………透孔
C…………………………………光導波路
K1〜K3………………………光導波路付き配線基板
1, 30 ………………………… Insulating substrate 2, 42a ……………………… Surface 11, 46, 50 ……………… Lower relaxation layer 14a, 14b, 56, 60 ... IC chip (operating element)
16, 64 ………………………… Light emitting element (optical element)
18, 67 ………………………… Light receiving element (optical element)
24 ……………………………… Reflecting mirror surface 26, 52 ……………………… Upper relaxation layer 53 ……………………………… Upper relaxation layer surface 54 55 ……………………… Through hole C …………………………………… Optical waveguide K1 to K3 ……………………… Wiring board with optical waveguide

Claims (3)

表面を有する絶縁性基板と、
上記絶縁性基板の表面上方に配置され且つ熱膨張率が上記絶縁性基板の熱膨張率よりも高い光導波路と、
上記絶縁性基板の表面と光導波路との間およびかかる光導波路の上方に形成され、且つ熱膨張率が上記絶縁性基板と上記光導波路との中間である下緩和層および上緩和層と、を含む、ことを特徴とする光導波路付き配線基板。
An insulating substrate having a surface;
An optical waveguide disposed above the surface of the insulating substrate and having a coefficient of thermal expansion higher than that of the insulating substrate;
A lower relaxation layer and an upper relaxation layer formed between the surface of the insulating substrate and the optical waveguide and above the optical waveguide, and having a thermal expansion coefficient intermediate between the insulating substrate and the optical waveguide; A wiring board with an optical waveguide, comprising:
前記上緩和層は、前記光導波路の両端に位置する反射ミラー面の上方の位置に一対の透孔を形成しており、かかる一対の透孔の上方で且つ上緩和層の表面上に光素子がそれぞれ実装されている、
請求項1に記載の光導波路付き配線基板。
The upper relaxation layer has a pair of through holes formed at positions above the reflecting mirror surfaces located at both ends of the optical waveguide, and the optical element is located above the pair of through holes and on the surface of the upper relaxation layer. Are implemented respectively.
The wiring board with an optical waveguide according to claim 1.
前記光素子に隣接し且つ前記光導波路と反対側の前記上緩和層の表面上に当該光素子と導通する動作素子が実装されている、
請求項1または2に記載の光導波路付き配線基板。
An operating element that is electrically connected to the optical element is mounted on the surface of the upper relaxation layer adjacent to the optical element and opposite to the optical waveguide.
The wiring board with an optical waveguide according to claim 1 or 2.
JP2003306994A 2003-08-29 2003-08-29 Wiring board with optical waveguide Expired - Fee Related JP4267982B2 (en)

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