JP2005073452A - Overcurrent protecting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the protective effect against overcurrent, by shutting down an input signal for a fixed period of time, if overcurrents are detected continuously. <P>SOLUTION: The detection of the overcurrents are counted by a counter circuit 17. It is recognized that the overcurrents are detected, when they are detected four times consecutively. Then, the input signal is shut down, until a counter circuit 24 counts a reference clock 64 times. This constitution makes it possible to reduce the overcurrents that flow in an output MOSFET 4 to 4/64. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an overcurrent protection circuit that protects an output device that performs switching operation.

  As a conventional overcurrent protection circuit, the circuit configuration described in Patent Documents 1 and 2 can be exemplified.

  FIG. 4 is a configuration diagram of a conventional overcurrent protection circuit, and FIG. 5 is a timing chart of a conventional overcurrent protection operation.

  In FIG. 4, 1 is an input signal terminal, 2 is an AND circuit, 3 is a driver circuit, 4 is an output MOSFET, 5 is an overcurrent detection resistor, 6 is a power supply voltage, 7 is a voltage comparator, 8 is a reference voltage, and 9 is a reference voltage. SR-FF circuit, 10 is a delay circuit, 11 is a NAND circuit, 12 is an overcurrent detection terminal, and 13, 14 and 15 are inverter circuits.

  In FIG. 5, 101 is a voltage waveform of the input signal terminal 1, 102 is an output voltage waveform of the AND circuit 2, 103 is a source voltage waveform of the output MOSFET 4, 104 is a drain voltage waveform of the output MOSFET 4, 105 is a reference voltage waveform, and 106 is An overcurrent detection set signal, 107 is an overcurrent detection reset signal, and 108 is a voltage waveform of the overcurrent detection terminal 12.

  The operation of the overcurrent protection circuit configured as described above will be described below.

  First, the input signal 101 applied to the input signal terminal 1 passes through the driver circuit 3 and drives the output MOSFET 4. Next, when the output MOSFET 4 is turned on and a current flows, a voltage drop occurs due to the overcurrent detection resistor 5 and the voltage drop is large. When the drain voltage of the output MOSFET 4 becomes smaller than the reference voltage 8 as shown by waveforms 104 and 105, The voltage comparator 7 outputs an overcurrent detection set signal as the waveform 106 as overcurrent detection.

  Further, by connecting the input signal terminal 1 to the delay circuit 10, a signal having a delay is output. By connecting the inverted signal through the inverter circuit 13 and the input signal terminal 1 to the NAND circuit 11, the waveform 107 Thus, a pulse synchronized with the rising edge of the input signal terminal 1 is generated and used as an overcurrent detection reset signal. However, the magnitude of the delay is shorter than one cycle time.

  Next, when the overcurrent detection set signal and the reset signal are input to the SR-FF circuit 9 and the output is passed through the inverter circuit 15, a voltage waveform such as the waveform 108 is output to the overcurrent detection terminal 12. The overcurrent detection terminal 12 is protected via the AND circuit 2 by shutting down the input signal and turning off the output MOSFET 4 when an overcurrent is detected.

In FIG. 5, the result of passing the voltage waveform 101 of the input signal terminal 1 and the voltage waveform 108 of the overcurrent detection terminal 12 through the AND circuit 2 is the output voltage waveform 102 of the AND circuit 2, and the overcurrent detection terminal 12 is It is always delayed from the input terminal 1 by the circuit delay. Even if the drain voltage of the output MOSFET 4 does not become higher than the reference voltage 8 (FIG. 5 (1)), a current flows through the output MOSFET 4 during the circuit delay time. In the waveform 103, the shaded portion indicates a portion that is turned off due to overcurrent detection.
Japanese Patent Laid-Open No. 6-187055 JP-A-8-32362

  However, in the conventional configuration, since the input signal is shut down by a signal fed back overcurrent detection, a current always flows for at least the circuit delay time. In addition, the earlier the operation cycle, the larger the proportion of overcurrent in one cycle, and the overcurrent protection effect is reduced.

  The present invention solves the above-described conventional problems, and an object of the present invention is to provide an overcurrent protection circuit capable of shutting down an input signal for a certain period when an overcurrent is continuously detected.

  In order to achieve the above object, an overcurrent protection circuit according to the present invention connects an overcurrent detection signal to one input terminal of a NOR circuit via a fourth inverter circuit in addition to the conventional circuit, and connects the other of the NOR circuit. The input signal terminal is connected to the input terminal of the first counter circuit, the output terminal of the NOR circuit is connected to the reset terminal of the first counter circuit that counts the clock having the reset terminal, the clock terminal, and the positive output terminal four times. An overcurrent detection signal is connected to the clock terminal of the counter circuit, the input terminal of the second delay circuit is connected to the positive output terminal of the first counter circuit, and the output terminal of the second delay circuit is connected to the second output terminal. 5 is connected to one input terminal of the second NAND circuit through the inverter circuit, and the positive output terminal of the first counter circuit is connected to the other input terminal of the second NAND circuit. The output terminal of the second NAND circuit is connected to the set terminal of the second SR-FF circuit, and the output terminal of the second SR-FF circuit is connected to one input of the OR circuit via the sixth inverter circuit. And the other output terminal of the OR circuit is connected to a reset terminal of a second counter circuit that counts a clock having a reset terminal, a clock terminal, and a positive output terminal 64 times, and the second counter circuit A reference clock terminal is connected to the clock terminal, and the positive output terminal of the second counter circuit is connected to the other input terminal of the first AND circuit and the clock of the D flip-flop circuit with reset via a seventh inverter circuit. And the input terminal of the D flip-flop circuit is connected to a power supply voltage, and the sixth inverter circuit is connected to the reset terminal of the D flip-flop circuit. Of connecting the output terminals, and the configuration of connecting the positive output terminal of the D flip-flop circuit to the other input terminal of the reset terminal and the OR circuit of said second SR-FF circuit.

  According to the present invention, it is possible to prevent malfunction of the timer due to erroneous detection of overcurrent, and it is possible to increase the function of overcurrent protection by shutting down the input signal for a certain period of time by the timer circuit, and for normal operation. Can self-recover.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of an overcurrent protection circuit according to an embodiment of the present invention, and members corresponding to those described in the conventional example shown in FIG.

  In FIG. 1, 1 is an input signal terminal, 2a and 2b are AND circuits, 3 is a driver circuit, 4 is an output MOSFET, 5 is an overcurrent detection resistor, 6 is a power supply voltage, 7 is a voltage comparator, 8 is a reference voltage, 9 is an SR-FF circuit, 10 is a delay circuit, 11 is a NAND circuit, 12 is an overcurrent detection terminal, 13, 14 and 15 are inverter circuits, 16 is a NOR circuit, 17 is a clock terminal, a reset terminal, and a positive output terminal. 4 count counter circuit, 18 delay circuit, 19 inverter circuit, 20 NAND circuit, 21 SR-FF circuit, 22 inverter circuit, 23 OR circuit, 24 clock terminal, reset terminal, positive output terminal Counter circuit for 64 counts, 25 is a reference clock terminal, 26 is an inverter circuit, 27 is a D-FF circuit with reset, and 28 is a power supply It is.

  FIG. 2 is a timing chart showing the timing until the counter circuit 17 of the overcurrent protection circuit in this embodiment counts four times continuously, 201 is the voltage waveform of the input signal terminal 1, and 202 is the voltage of the overcurrent detection terminal 12. Waveform, 203 is a voltage waveform of the reset terminal of the counter circuit 17, 204 is a voltage waveform of the output terminal of the counter circuit 17, 205 is a pulse waveform synchronized with the rise of the counter circuit 17, and 206 is a reset terminal of the D-FF circuit 27 The waveform of the input signal, 207 is the reset signal of the counter circuit 24, 208 is the waveform of the reference clock, and 209 is the voltage waveform of the output terminal of the counter circuit 24.

  FIG. 3 is a time chart for explaining the circuit operation of the overcurrent protection circuit of the present embodiment, and is a timing chart from when the counter circuit 17 counts continuously four times until the counter circuit 24 counts continuously 64 times. Yes, 211 is a voltage waveform of the output terminal of the counter circuit 17, 212 is a pulse waveform synchronized with the rising of the counter circuit 17, 213 is a waveform of an input signal of the reset terminal of the D-FF circuit 31, and 214 is a reset of the counter circuit 24 Signal 215 is a voltage waveform at the output terminal of the counter circuit 24, and 216 is a voltage waveform at the output terminal of the D-FF circuit 27.

  The circuit operation of the overcurrent protection circuit of the present embodiment configured as described above will be described below.

  In FIG. 1, the overcurrent detection terminal 12 is connected to the clock terminal of the counter circuit 17 from the same circuit as the conventional example, and overcurrent detection is counted. However, if the overcurrent is not detected continuously with respect to the input signal, an inversion of the input signal and the overcurrent detection signal 12 is connected to the reset terminal of the counter circuit 17 via the NOR circuit 16 in order to recognize a malfunction. . This is because the overcurrent detection signal is HIGH during normal operation and a reset signal is issued when the input signal is LOW, and the counter is reset each time.

  When an overcurrent is detected, once detected by the SR-FF circuit 21, the overcurrent detection signal 12 is a LOW signal until the input signal rises. Therefore, even if the input signal becomes LOW, the reset signal remains LOW. When it is counted and continuously counted four times, it is recognized as overcurrent detection, and a HIGH signal is output to the output terminal. In this way, it is determined whether it is erroneous recognition or overcurrent detection. Next, in order to start the operation of the counter circuit 24 by the output of the counter circuit 17, the SR-FF circuit 21 sets the reset signal of the counter circuit 24 to LOW.

  Therefore, the output terminal of the counter circuit 17 is connected to the set terminal of the SR-FF circuit 21, but when the counter circuit 24 is counting, the input signal terminal is shut down, so that the output terminal of the counter circuit 17 is HIGH. May remain. When this happens, when the counter circuit 24 counts 64 times and returns to normal operation, no matter what signal is input to the reset terminal, the output terminal does not become a LOW signal if HIGH is input to the set terminal.

  In order to solve this problem, the delay circuit 18, the inverter circuit 19, and the NAND circuit 20 generate a pulse synchronized with the rising edge of the output signal of the counter circuit 17. The above problem can be solved by connecting the pulse to the set terminal of the SR-FF circuit 21.

  Next, when a HIGH signal is input to the set terminal of the SR-FF circuit 21, the output of the inverter circuit 22 becomes LOW, and the output of the D-FF circuit 27 is LOW. The 24 reset terminals become LOW, the reset is released, and 64 counts of the reference clock 25 are started. When the counting is started, the output terminal of the counter circuit 24 becomes HIGH and is connected to the AND circuit 2a through the inverter circuit 26 to shut down the signal of the input signal terminal.

  When counting 64 times, the output terminal of the counter circuit 24 becomes LOW, the output of the inverter circuit 26 becomes HIGH, the shutdown of the input signal terminal is released, and the clock is input to the D-FF circuit 27 for output. The terminal becomes HIGH and the SR-FF circuit 21 is reset, and the signal passing through the inverter circuit 22 from the output terminal of the SR-FF circuit 21 becomes HIGH, the D-FF circuit 27 is reset, and the output terminal becomes LOW. The reset terminal of the SR-FF circuit 21 becomes LOW and returns to the input waiting state of the counter circuit 17.

  When the output terminal of the D-FF circuit 27 becomes HIGH, the output terminal of the NOR circuit 16 becomes HIGH, and the counter circuit 24 returns to the reset state. That is, when the counter circuit 17 counts overcurrent detection for a certain number of consecutive times, the output circuit 4 is protected from overcurrent by shutting down the input signal for a certain period of time by the counter circuit 24. You can return to the waiting state.

  As described above, according to the present embodiment, the overcurrent detection is counted, and the overcurrent flowing through the output MOSFET can be reduced to 4/64 by shutting down the input signal for 64 clocks when four consecutive detections are made. it can.

  In this embodiment, the circuit for generating the pulse synchronized with the rising edge passes the input signal through the delay circuit, the signal through the inverter circuit and the input signal through the NAND circuit, but the input signal passes through the delay circuit. A pulse may be created by passing a signal and an input signal through an inverter circuit and a NOR circuit.

  In this embodiment, overcurrent detection is continuously counted four times, but may be counted continuously N times.

  In this embodiment, the reference clock is counted 64 times, but may be counted M times.

  The present invention is applied to an overcurrent protection circuit that protects an output device that performs switching operation. In particular, the timer prevents malfunction due to erroneous detection of overcurrent, and the function of overcurrent protection is increased to operate normally. This is useful for an overcurrent protection circuit that enables self-recovery.

1 is a configuration diagram of an overcurrent protection circuit according to an embodiment of the present invention. Timing chart until the counter circuit of the overcurrent protection circuit in this embodiment counts continuously four times Time chart for explaining the circuit operation of the overcurrent protection circuit of this embodiment Configuration diagram of conventional overcurrent protection circuit Timing chart of each part of the conventional overcurrent protection circuit

Explanation of symbols

1 Input signal terminals 2a and 2b AND circuit 3 Driver circuit 4 Output MOSFET
5 Overcurrent detection resistor 6 Power supply voltage 7 Voltage comparator 8 Reference voltage 9 SR-FF circuit 10 Delay circuit 11 NAND circuit 12 Overcurrent detection terminals 13, 14, 15 Inverter circuit 16 NOR circuit 17 4 counter circuit 18 delay circuit 19 Inverter circuit 20 NAND circuit 21 SR-FF circuit 22 Inverter circuit 23 OR circuit 24 64 Counter circuit 25 Reference clock terminal 26 Inverter circuit 27 D-FF circuit 28 with reset Power supply voltage

Claims (6)

  The input signal terminal is connected to one input terminal of the first AND circuit, the output terminal of the first AND circuit is connected to one input terminal of the second AND circuit, and the output of the second AND circuit The terminal is connected to the gate terminal of the MOSFET via the amplifier circuit, the source terminal of the MOSFET is grounded, the drain terminal is connected to the power supply voltage via a resistor, and the drain terminal is connected to the positive input terminal of the voltage comparator. And connecting the reference voltage to the negative input terminal of the voltage comparator and connecting the output terminal to the input terminal of the first inverter circuit, and connecting the output terminal of the first inverter circuit to an SR flip-flop (hereinafter referred to as SR flip-flop). -FF) is connected to the set terminal of the circuit, the output terminal of the SR-FF circuit is connected to the second inverter circuit, and the output terminal of the first AND circuit is connected to the first terminal via the first delay circuit. Connected to the inverter circuit, the output terminal of the third inverter circuit is connected to one input terminal of the first NAND circuit, and the output terminal of the first AND circuit is connected to the other of the first NAND circuit. Connected to the input terminal, the output terminal of the first NAND circuit is connected to the reset terminal of the SR-FF circuit, and the output terminal of the second inverter circuit is connected to the other input terminal of the second AND circuit. Connected to the input terminal of the fourth inverter circuit, connected the output terminal of the fourth inverter circuit to one input terminal of the NOR circuit, and connected to the other input terminal of the NOR circuit as the output terminal of the first AND circuit And the output terminal of the NOR circuit is connected to the reset terminal of a first counter circuit that counts a clock having a reset terminal, a clock terminal, and a positive / negative output terminal four times. The output terminal of the second inverter circuit is connected to the clock terminal of the inverter circuit, the second delay circuit is connected to the positive output terminal of the second inverter circuit, and the second inverter circuit is connected via the fifth inverter circuit. Is connected to one input terminal of the NAND circuit, the positive output terminal of the first counter circuit is connected to the other input terminal of the second NAND circuit, and the output terminal of the second NAND circuit is connected to the second SR. -Connected to the set terminal of the FF circuit, the output terminal of the second SR-FF circuit is connected to one input terminal of the OR circuit via the sixth inverter circuit, and the output terminal of the OR circuit is connected to the reset terminal A clock terminal and a positive / negative output terminal are connected to the reset terminal of the second counter circuit that counts the clock 64 times, the reference clock terminal is connected to the clock terminal of the second counter circuit, and the second The positive output terminal of the counter circuit is connected to the other input terminal of the first AND circuit and the clock terminal of a D flip-flop (hereinafter referred to as D-FF) circuit via a seventh inverter circuit, and the D The input terminal of the FF circuit is connected to the power supply voltage, the output terminal of the sixth inverter circuit is connected to the reset terminal of the D-FF circuit, and the positive output terminal of the D-FF circuit is connected to the second SR. An overcurrent protection circuit, wherein the overcurrent protection circuit is connected to a reset terminal of the FF circuit and the other input terminal of the OR circuit.   A source terminal of the MOSFET is connected to a power source via a resistor, a drain terminal of the MOSFET is connected to a positive input terminal of a voltage comparator, a reference voltage is connected to a negative input terminal of the voltage comparator, and the voltage comparison 2. The overcurrent protection circuit according to claim 1, wherein an output terminal of the capacitor is connected to the first inverter circuit.   2. The overcurrent protection circuit according to claim 1, wherein the current detection method is performed by another method.   2. An OR circuit is connected between a positive output terminal of the D-FF circuit and a reset terminal of the second SR-FF circuit, and the other input terminal is connected to an on-reset terminal. Overcurrent protection circuit.   2. The overcurrent protection circuit according to claim 1, wherein the first counter circuit comprises an N-count counter circuit.   2. The overcurrent protection circuit according to claim 1, wherein the second counter circuit comprises an M-count counter circuit.

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