JP2005072167A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of high reliability in which breakdown voltage is ensured sufficiently between a contact plug and a gate electrode, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device comprises a silicon substrate 1 including a main surface 1a, a gate electrode which is formed on the main surface 1a and includes a crest plane 4a, word lines 5m and 5n which are formed on the crest plane 4a and include a crest plane 5a formed by an area smaller than that of the crest plane 4a, the crest plane 5a, gate protective films 6m and 6n covering the gate electrode and side walls of the word lines 5m and 5n, an inlterlayer insulating film 8 which is formed on the main surface 1a covering the gate protective films 6m, 6n, and includes a contact hole 7 reaching the main surface 1a, and a contact plug 9 which includes a part 9p being in contact with the gate protective films 6m and 6n and fills the contact hole 7. The interlayer insulating film 8 is easier to be etched than the gate protective films 6m and 6n to predetermined etching condition. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention generally relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using a SAC (self align contact) structure and a manufacturing method thereof.

  In recent years, as the degree of integration of semiconductor devices has improved and the miniaturization of memory cells has progressed, the distance between gate electrodes has become shorter. Under such circumstances, it has become difficult to form a contact between gate electrodes using only a photoresist mask without short-circuiting the gate electrodes. Therefore, various methods for forming a contact that does not cause a short circuit have been considered, and one method is to use a SAC (self align contact) structure.

  When this SAC structure is used, a sidewall made of, for example, a silicon nitride film is formed so as to cover the gate electrode and the word line formed on the gate electrode. A contact formed between the gate electrodes is formed so that a part thereof reaches the side wall.

  In addition, a method for manufacturing a semiconductor device for the purpose of obtaining a field effect transistor having a high breakdown voltage gate electrode is disclosed in Japanese Patent Application Laid-Open No. 61-147579 (Patent Document 1).

  According to the method for manufacturing a semiconductor device disclosed in Patent Document 1, anisotropic dry etching is performed to form a gate electrode composed of a polysilicon layer and a tungsten silicide layer. Thereafter, wet etching is further performed using a mixed solution of hydrogen peroxide and ammonia. By this wet etching, only the tungsten silicide layer is etched, and the cross-sectional shape of the gate electrode is formed in a convex shape. During the wet etching process, a resist film is formed on the top surface of the tungsten silicide layer as a mask.

In addition, a method for manufacturing a semiconductor memory device for the purpose of increasing the alignment margin of a photoresist is disclosed in Japanese Patent Laid-Open No. 9-275152 (Patent Document 2). In addition, a field effect semiconductor device and a method of manufacturing the same for the purpose of facilitating the flattening of an interlayer insulating film and the like and setting the interval between pocket layers and the like to a predetermined value with respect to the gate length are disclosed in Japanese Patent Application Laid-Open No. 8-288510. (Patent Document 3).
JP 61-147579 A JP-A-9-275152 JP-A-8-288510

  As already described, in the SAC structure, a part of the contact reaches the sidewall covering the gate electrode and the word line. For this reason, the contact plug filling the contact is formed in contact with the sidewall. However, in this case, since the distance between the contact plug and the word line sandwiching the sidewall is small, there arises a problem that the withstand voltage is lowered at that portion. For this reason, when the semiconductor device is operated, a leak current is generated, which causes a malfunction.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, and to provide a highly reliable semiconductor device in which a withstand voltage between a contact plug and a gate electrode is sufficiently secured, and a method for manufacturing the same. .

  A semiconductor device according to the present invention includes a semiconductor substrate including a main surface, a gate electrode formed on the main surface and including a first top surface, and a first top surface formed on the first top surface. A metal wiring including a second top surface formed in an area smaller than the area, a gate protection film covering the second top surface and the side walls of the gate electrode and the metal wiring, and a gate protection film An interlayer insulating film formed on the main surface and including a hole reaching the main surface, and a conductive layer including a portion in contact with the gate protective film and filling the hole. The interlayer insulating film is more easily etched than the gate protective film under predetermined etching conditions.

  According to the present invention, it is possible to provide a highly reliable semiconductor device in which a withstand voltage between the contact plug and the gate electrode is sufficiently secured and a method for manufacturing the same.

  Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing the semiconductor device in FIG. 1, in which the structure located in the upper layer is omitted. 1 is a cross-sectional view taken along the line II in FIG.

  Referring to FIGS. 1 and 2, a semiconductor device includes a silicon substrate 1 having a main surface 1a, floating gate electrodes 2m and 2n, ONO films 3m and 3n, and control gates stacked on the main surface 1a in order from the bottom. Electrodes 4m and 4n and word lines 5m and 5n, gate protective films 6m and 6n formed on main surface 1a so as to cover these stacked bodies, and an interlayer formed on main surface 1a and having contact hole 7 An insulating film 8 and a contact plug 9 filling the contact hole 7 are provided. A semiconductor device having such a structure constitutes a flash memory of a nonvolatile semiconductor memory device.

  On the main surface 1a of the silicon substrate 1, an active region 31 in which elements are formed extends in one direction. On both sides of the active region 31, separation regions 34 that separate adjacent active regions 31 from each other are formed.

  Tunnel oxide films 41m and 41n made of a silicon oxide film are formed on main surface 1a. Floating gate electrodes 2m and 2n made of polysilicon are formed on tunnel oxide films 41m and 41n at a distance from each other. Floating gate electrodes 2m and 2n are formed so as to cross each other in the direction in which active region 31 extends.

  A drain region 32 is formed on main surface 1a located between floating gate electrodes 2m and 2n. Source regions 33 are formed on the main surface 1a opposite to the drain region 32 with the floating gate electrodes 2m and 2n interposed therebetween. The drain region 32 and the source region 33 are constituted by impurity regions, and are formed by doping an impurity having a conductivity type opposite to that of the impurity doped in the silicon substrate 1.

  On floating gate electrodes 2m and 2n, ONO films 3m and 3n having a three-layer structure of an oxide film, a nitride film, and an oxide film are formed. Further, control gate electrodes 4m and 4n made of polysilicon are formed on the ONO films 3m and 3n. The control gate electrodes 4m and 4n intersect the active region 31, and extend in a direction substantially orthogonal to the direction in which the active region 31 extends. Control gate electrode 4 (4m and 4n) has a top surface 4a on the side opposite to the surface in contact with ONO films 3m and 3n.

  In the channel length direction (direction perpendicular to the direction in which control gate electrodes 4m and 4n extend) from drain region 32 to source region 33, top surface 4a of control gate electrode 4 is formed with a width B1. The width B1 is, for example, about 160 nm to 170 nm. In the same direction, control gate electrodes 4m and 4n, ONO films 3m and 3n, and floating gate electrodes 2m and 2n are formed with substantially the same width or slightly wider than silicon nitride films 11m and 11n in FIG. ing. On the side walls of control gate electrodes 4m and 4n, ONO films 3m and 3n, and floating gate electrodes 2m and 2n, sidewall oxide film 42 is thinly formed.

  On the top surface 4a of the control gate electrode 4, word lines 5m and 5n made of tungsten silicide (WSi) are formed. Further, the word lines 5m and 5n may be made of tungsten (W) instead of tungsten silicide. By using tungsten silicide or tungsten having a low resistivity, the resistance of the word lines 5m and 5n can be reduced. The word lines 5m and 5n extend in the direction in which the control gate electrodes 4m and 4n extend. The word line 5 (5m and 5n) has a top surface 5a on the side opposite to the surface in contact with the top surface 4a. The top surface 5 a is formed with a smaller area than the top surface 4 a of the control gate electrode 4.

  In the channel length direction, the top surface 5a of the word line 5 is formed with a width B2 smaller than the width B1. The width B2 is, for example, about 75 nm to 85 nm. In the same direction, the word lines 5m and 5n are formed with a width B2.

  An exposed portion 4 y exposed from the word line 5 is formed on the top surface 4 a of the control gate electrode 4 located on both sides of the word line 5. The exposed portion 4 y corresponds to a portion from the periphery of the top surface 4 a to the top surface 4 a extending to the side wall of the word line 5. The exposed portion 4y extends in the direction in which the control gate electrodes 4m and 4n extend. All the exposed portions 4y are formed with substantially the same width.

  Gate protective films 6m and 6n made of a silicon nitride film are formed on main surface 1a at a distance. The gate protective film 6m includes the top surface 5a of the word line 5, the exposed portion 4y of the control gate electrode 4m, and the side wall oxide film 42 provided on the side walls of the control gate electrode 4m, the ONO film 3m, and the floating gate electrode 2m. Covering. The gate protection film 6n includes the top surface 5a of the word line 5, the exposed portion 4y of the control gate electrode 4n, and the sidewall oxide film 42 provided on the sidewalls of the control gate electrode 4n, the ONO film 3n, and the floating gate electrode 2n. Covering.

  The surfaces of gate protective films 6m and 6n are linearly formed on the top surface side, and extend in an arc shape from the top surface side toward main surface 1a. Gate protective films 6m and 6n are formed such that the distance from the sidewall of each gate electrode in contact with the surface of gate protective films 6m and 6n decreases as the distance from main surface 1a increases. A part of main surface 1a located between floating gate electrodes 2m and 2n is exposed from gate protective films 6m and 6n. Silicon nitride films 43m and 43n are thinly formed so as to cover part of the surfaces of gate protective films 6m and 6n.

  On main surface 1a, interlayer insulating film 8 made of a silicon oxide film is formed so as to cover silicon nitride films 43m and 43n. The silicon nitride film forming the gate protective films 6m and 6n has a selection ratio of a certain level or more with respect to predetermined etching conditions when the interlayer insulating film 8 is etched.

  In interlayer insulating film 8, contact hole 7 reaching main surface 1a located between floating gate electrodes 2m and 2n is formed. A part of the contact hole 7 is defined by the gate protective films 6m and 6n. A contact plug 9 made of tungsten (W) is formed so as to fill the contact hole 7. Contact plug 9 is in contact with drain region 32 formed in main surface 1a. The portion 9p of the contact plug 9 is in contact with the gate protective films 6m and 6n.

  The distance L between the contact plug 9 formed via the gate protective films 6m and 6n and the word line 5 (the distance between the contact plug 9 and the periphery of the top surface 5a) is 0 <L ≦ 90 nm. Meet.

  A semiconductor device according to the first embodiment of the present invention includes a silicon substrate 1 as a semiconductor substrate including main surface 1a, and a gate electrode formed on main surface 1a and including top surface 4a as a first top surface. And word lines 5m and 5n as metal wirings including a top surface 5a as a second top surface formed on top surface 4a and having an area smaller than the area of top surface 4a, and top surface 5a Gate protective films 6m and 6n covering the gate electrodes and side walls of word lines 5m and 5n, and contact holes formed on main surface 1a so as to cover gate protective films 6m and 6n and as holes reaching main surface 1a 7 and a contact plug 9 as a conductive layer that fills the contact hole 7 including a portion 9p that contacts the gate protective films 6m and 6n. The interlayer insulating film 8 is more easily etched than the gate protective films 6m and 6n under predetermined etching conditions.

  The gate electrode and the word line 5 extend in one direction. Top surface 4a is exposed from word line 5 on both sides of word line 5, and has an exposed portion 4y extending in the direction in which the gate electrode and word line 5 extend. In other words, the gate electrode is formed with a first width in the channel length direction, and the word line 5 is formed with a second width smaller than the first width in the channel length direction.

  The distance L from the contact plug 9 to the word line 5 is more than 0 and 90 nm or less. More preferably, the distance L from the contact plug 9 to the word line 5 is not less than 70 nm and not more than 90 nm. Word lines 5m and 5n include at least one of tungsten silicide and tungsten.

  Gate electrodes are formed on floating gate electrodes 2m and 2n formed on main surface 1a, ONO films 3m and 3n as dielectric films formed on floating gate electrodes 2m and 2n, and ONO films 3m and 3n. The control gate electrodes 4m and 4n are formed and have a top surface 4a.

  3 to 11 are cross-sectional views showing the steps of the method of manufacturing the semiconductor device in FIG. A method for manufacturing the semiconductor device in FIG. 1 will be described below with reference to FIGS. 1 and 3 to 11.

  Referring to FIG. 3, silicon oxide film 41 to be tunnel oxide films 41n and 41m is formed on main surface 1a of silicon substrate 1. Next, on the silicon oxide film 41, a polysilicon film, an ONO film, a poly for forming the floating gate electrode 2 (2m and 2n), the ONO film 3 (3m and 3n), the control gate electrode 4 and the word line 5 are formed. A silicon film and a tungsten silicide film are sequentially deposited. Further, a silicon nitride film 11 is deposited on the polysilicon film for forming the control gate electrode 4.

  Referring to FIG. 4, a resist film 13 having a predetermined opening pattern is formed on silicon nitride film 11. Referring to FIG. 5, silicon nitride film 11 is anisotropically etched using resist film 13 as a mask. Thereby, the portion of the silicon nitride film 11 exposed from the resist film 13 is removed, and the silicon nitride films 11m and 11n remain at positions spaced apart from each other. Thereafter, the resist film 13 is removed.

  Referring to FIG. 6, the tungsten silicide film, the polysilicon film, the ONO film, and the polysilicon film are sequentially anisotropically etched using silicon nitride films 11m and 11n as a mask. Thereby, a part of each film is removed, and word lines 5m and 5n, control gate electrodes 4m and 4n, ONO films 3m and 3n, and floating gate electrodes 2m and 2n are formed by the remaining portions.

  At this time, since the silicon nitride films 11m and 11n are used as the mask instead of the resist film, the resistance of the mask to etching can be improved. Thereby, it is possible to prevent the word lines 5m and 5n located immediately below the mask from being damaged during the anisotropic etching described above.

Referring to FIG. 7, word lines 5m and 5n are wet-etched using an etchant containing acid-based sulfuric acid (H ₂ SO ₄ ) which has an action of dissolving metal. Specifically, first, the word lines 5m and 5n are wet-etched using an etchant of SPM (H ₂ SO ₄ : H ₂ O ₂ = 5: 1, temperature 130 ° C. ± 5 ° C.). Subsequently, the word lines 5m and 5n are wet-etched using an etchant of APM (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5, temperature 45 ° C. ± 5 ° C.). Further, a series of wet etching using these two etchants is repeated five times.

  By this wet etching, the etching of the word lines 5m and 5n proceeds from the peripheral edge toward the center. Then, the word lines 5m and 5n move backward until the width in the channel length direction becomes B2. On the other hand, the floating gate electrodes 2m and 2n made of polysilicon or the like are hardly affected by the two etchants, and the width of the floating gate electrodes 2m and 2n etc. in the channel length direction is B1.

  Referring to FIG. 8, side wall oxidation is performed on control gate electrodes 4m and 4n, ONO films 3m and 3n, and floating gate electrodes 2m and 2n. Thereby, the sidewall oxide film 42 is thinly formed at a predetermined position. A sidewall 15 made of a silicon nitride film is deposited so as to cover the surface of the structure on the main surface 1a. Referring to FIG. 9, sidewall 15 is anisotropically etched until main surface 1a is exposed, and sidewalls 15m and 15n are left on both sides of the gate electrode composed of floating gate electrodes 2m and 2n. On the other hand, the sidewall 15 on the silicon nitride films 11m and 11n is removed by this anisotropic etching, and the top surfaces of the silicon nitride films 11m and 11n are exposed. As a result, a gate protective film 6m made of a silicon nitride film is formed by the sidewalls 15m and the silicon nitride film 11m. Further, a gate protection film 6n made of a silicon nitride film is formed by the sidewalls 15n and the silicon nitride film 11n.

  Referring to FIG. 10, a silicon nitride film 43 is formed with a thickness of 15 nm, for example, so as to cover main surface 1a and gate protective films 6m and 6n. A silicon oxide film for forming the interlayer insulating film 8 is deposited so as to cover the silicon nitride film 43. Referring to FIG. 11, a resist film (not shown) is formed on interlayer insulating film 8. Using the resist film as a mask, the interlayer insulating film 8 is etched under predetermined etching conditions. This etching stops on the silicon nitride film 43, and then the silicon nitride film 43 on the main surface 1a is removed by performing a predetermined etching. Thereby, contact hole 7 reaching main surface 1a is formed. Thereafter, the resist film (not shown) is removed. Referring to FIG. 1, in order to form contact plug 9, contact hole 7 is filled with polysilicon. Through the above steps, the semiconductor device in FIG. 1 is completed.

  In the process shown in FIG. 11, the silicon nitride film has a selection ratio of a certain level or more with respect to predetermined etching conditions when etching the interlayer insulating film 8. For this reason, the contact hole 7 does not penetrate through the gate protective films 6m and 6n made of a silicon nitride film, regardless of the accuracy of photoengraving when the contact hole 7 is formed. As a result, the contact plug 9 filling the contact hole 7 can be prevented from contacting the word lines 5m and 5n. As a result, a contact can be formed between the gate electrodes without fear of occurrence of a short circuit, so that the distance between the gate electrodes can be positively shortened and the memory cell can be miniaturized.

  In the method of manufacturing a semiconductor device according to the first embodiment of the present invention, a polysilicon film as a conductor film containing silicon and a tungsten silicide film as a metal film are sequentially formed on main surface 1a of silicon substrate 1. A step of forming, a step of forming silicon nitride films 11m and 11n as mask films including at least one of silicon nitride and silicon oxide on the tungsten silicide film, and a polysilicon film using silicon nitride films 11m and 11n as a mask. Forming a gate electrode and word lines 5m and 5n extending in one direction by etching a part of the tungsten silicide film and a part of the tungsten silicide film and leaving the other part, and a word line using an etchant containing sulfuric acid Isotropic etching of 5m and 5n edges And sidewalls 15m and 15n as sidewall protective films including at least one of silicon nitride and silicon oxide are formed so as to be in contact with the gate electrodes, the word lines 5m and 5n, and the sidewalls of the silicon nitride films 11m and 11n. A process.

  According to the semiconductor device configured as described above and the manufacturing method thereof, the top surfaces 5a of the word lines 5m and 5n are formed with a smaller area than the top surfaces 4a of the control gate electrodes 4m and 4n located therebelow. Yes. For this reason, compared with the case where the top surface 5a is formed in the same area as the top surface 4a, the distance from the periphery of the top surface 5a to the surface of the gate protective films 6m and 6n can be increased. As a result, the distance between the contact plug 9 formed in contact with the surfaces of the gate protective films 6m and 6n and the word line 5 is increased, so that the breakdown voltage between them is set to a higher value and the reliability is high. A semiconductor device can be realized.

  The top surface 4a has an exposed portion 4y extending in the direction in which the gate electrode and the word line 5 extend. Therefore, even when the contact plug 9 is formed at any position in the direction in which the gate electrode and the word line 5 extend, the above-described effect can be obtained.

  Further, the distance L between the contact plug 9 and the word line 5 is set to be more than 0 and 90 nm or less. When the distance L is 0, since the contact plug 9 and the word line 5 are in contact with each other, both are short-circuited. Further, when the distance L is greater than 90 nm, the thickness of the gate protective films 6m and 6n becomes too large, so that the main surface 1a exposed from the gate protective films 6m and 6n is sufficient between the floating gate electrodes 2m and 2n. Can't get by area. Therefore, such a situation can be avoided by setting the distance L to the above range.

  Further, when wet etching is performed on the word lines 5m and 5n made of tungsten silicide, an etchant containing sulfuric acid is used. For this reason, only the word lines 5m and 5n can be effectively retracted without substantially affecting the floating gate electrodes 2m and 2n made of polysilicon.

  Further, during this wet etching, silicon nitride films 11m and 11n are used as masks on the word lines 5m and 5n instead of the resist film. Silicon nitride films 11m and 11n are hardly dissolved by wet etching using an etchant containing sulfuric acid.

  The SPM and APM etchants used for wet etching are usually used for cleaning processes such as before the film forming process. When a resist film is used as a mask, the resist film is dissolved by an etchant containing sulfuric acid, so that the etchant is contaminated. When the contaminated etchant is used as a cleaning liquid, the contamination spreads on the cleaned silicon substrate. Therefore, in this embodiment, the silicon nitride films 11m and 11n that do not contaminate the etchant are used as a mask.

  In the present embodiment, the gate electrode is composed of a floating gate electrode, a dielectric film, and a control gate electrode, and a flash memory including these has been described as having the above-described effects. However, the semiconductor device of the present invention is not limited to the flash memory, and can be applied to all transistors using the SAC structure.

(Embodiment 2)
12 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. Referring to FIG. 12, the semiconductor device according to the second embodiment of the present invention basically has the same structure as the semiconductor device according to the first embodiment. In the following, description of overlapping structures is omitted.

  On main surface 1a, gate protective films 23m and 23n made of a silicon oxide film are formed at a distance. The gate protection film 23m includes the top surface 5a of the word line 5, the exposed portion 4y of the control gate electrode 4m, and the sidewall oxide film 42 provided on the sidewalls of the control gate electrode 4m, the ONO film 3m, and the floating gate electrode 2m. Covering. The gate protective film 23n includes the top surface 5a of the word line 5, the exposed portion 4y of the control gate electrode 4n, and the sidewall oxide film 42 provided on the sidewalls of the control gate electrode 4n, the ONO film 3n, and the floating gate electrode 2n. Covering. The silicon oxide film that forms the gate protective films 23m and 23n has a selection ratio of a certain level or higher with respect to predetermined etching conditions for etching the interlayer insulating film 8 due to a difference in doped impurity concentration.

  Silicon nitride films 43m and 43n are thinly formed so as to cover part of the surfaces of gate protective films 23m and 23n. Silicon nitride films 43m and 43n also cover other parts of main surface 1a excluding the part where contact hole 7 reaches. The silicon nitride films 43m and 43n are mainly formed to prevent the etching from penetrating into the silicon substrate 1 during the etching for forming the contact hole 7.

  The semiconductor device manufacturing method in FIG. 12 includes basically the same steps as the semiconductor device manufacturing method in the first embodiment. However, in the step shown in FIG. 3 of the first embodiment, a silicon oxide film as a mask film is formed on the tungsten silicide film for forming the word line 5. Further, in the step shown in FIG. 8, a sidewall made of a silicon oxide film is formed.

  According to the semiconductor device configured as described above and the manufacturing method thereof, the same effects as those described in the first embodiment can be obtained. The ion gas released from the nitride film adversely affects the E (erase) / W (write) characteristics of the flash memory. In the present embodiment, since the silicon nitride films 43m and 43n are only formed thin on the gate protective films 23m and 23n made of silicon oxide films, the influence of the above-described ion gas can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which shows the semiconductor device in Embodiment 1 of this invention. FIG. 2 is a plan view showing the semiconductor device in FIG. 1. It is sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in FIG. It is sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in FIG. FIG. 8 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device in FIG. 1. FIG. 8 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device in FIG. 1. FIG. 7 is a cross-sectional view showing a fifth step of the method for manufacturing the semiconductor device in FIG. 1. FIG. 10 is a cross-sectional view showing a sixth step of the method for manufacturing the semiconductor device in FIG. 1. It is sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in FIG. It is sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in FIG. It is sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in FIG. It is sectional drawing which shows the semiconductor device in Embodiment 2 of this invention.

Explanation of symbols

  1 silicon substrate, 1a main surface, 2m, 2n floating gate electrode, 3m, 3n ONO film, 4a, 5a top surface, 4m, 4n control gate electrode, 4y exposed part, 5m, 5n word line, 6m, 6n, 23m, 23n Gate protective film, 7 contact hole, 8 interlayer insulation film, 9 contact plug, 9p portion, 11m, 11n silicon nitride film, 15m, 15n sidewall.

Claims (6)

A semiconductor substrate including a main surface;
A gate electrode formed on the main surface and including a first top surface;
A metal wiring including a second top surface formed on the first top surface and having an area smaller than an area of the first top surface;
A gate protective film covering the second top surface and the gate electrode and the side wall of the metal wiring;
An interlayer insulating film that is formed on the main surface so as to cover the gate protective film, includes a hole reaching the main surface, and is more easily etched than the gate protective film under a predetermined etching condition;
A semiconductor device comprising: a conductive layer including a portion in contact with the gate protective film and filling the hole.   The gate electrode and the metal wiring extend in one direction, the first top surface is exposed from the metal wiring on both sides of the metal wiring, and the gate electrode and the metal wiring extend. The semiconductor device according to claim 1, comprising an exposed portion extending in a direction.   The semiconductor device according to claim 1, wherein a distance from the conductive layer to the metal wiring is greater than 0 and equal to or less than 90 nm.   The gate electrode includes a floating gate electrode formed on the main surface, a dielectric film formed on the floating gate electrode, and a control formed on the dielectric film and having the first top surface. The semiconductor device according to claim 1, comprising a gate electrode.   The semiconductor device according to claim 1, wherein the metal wiring includes at least one of tungsten silicide and tungsten. A step of sequentially forming a conductor film containing silicon and a metal film on a main surface of a semiconductor substrate;
Forming a mask film containing at least one of silicon nitride and silicon oxide on the metal film;
Forming a gate electrode and a metal wiring extending in one direction by etching a part of the conductor film and a part of the metal film and leaving another part using the mask film as a mask;
A step of isotropically etching the periphery of the metal wiring using an etchant containing sulfuric acid;
Forming a sidewall protective film including at least one of silicon nitride and silicon oxide so as to be in contact with the gate electrode, the metal wiring, and the sidewall of the mask film.

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