JP2005072140A - Method of manufacturing semiconductor device and method of processing semiconductor wafer - Google Patents

Method of manufacturing semiconductor device and method of processing semiconductor wafer Download PDF

Info

Publication number
JP2005072140A
JP2005072140A JP2003297617A JP2003297617A JP2005072140A JP 2005072140 A JP2005072140 A JP 2005072140A JP 2003297617 A JP2003297617 A JP 2003297617A JP 2003297617 A JP2003297617 A JP 2003297617A JP 2005072140 A JP2005072140 A JP 2005072140A
Authority
JP
Japan
Prior art keywords
wafer
back surface
grinding
dicing tape
dicing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003297617A
Other languages
Japanese (ja)
Inventor
Katsuhiko Horigome
米 克 彦 堀
Michio Kanai
井 道 生 金
Hiroshi Koike
池 洋 小
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lintec Corp
Original Assignee
Lintec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lintec Corp filed Critical Lintec Corp
Priority to JP2003297617A priority Critical patent/JP2005072140A/en
Publication of JP2005072140A publication Critical patent/JP2005072140A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a defective pickup caused by insufficient formation of an oxide film on a rear face of a wafer, in a semiconductor device manufacturing method which includes an in-line process wherein immediately after finishing grinding the rear face, a dicing tape is pasted to the ground face. <P>SOLUTION: The method of manufacturing the semiconductor device comprises processes of grinding the rear face of the silicon wafer having a circuit formed on the surface, oxidizing the rear face of the silicon wafer to form the oxide film, pasting the dicing tape to the rear face of the silicon wafer, and then dicing the wafer into chips, and picking up the silicon chips. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、シリコンウエハの裏面研削工程、ウエハのダイシング工程およびチップのピックアップ工程からなる半導体装置の製造方法ならびにこの製法に用いられる半導体ウエハ加工装置に関し、特に、いわゆるインライン化プロセスを採用した際に、最終工程であるチップのピックアップ工程におけるピックアップ不良の低減を実現する半導体装置の製造方法および半導体ウエハ加工装置に関する。   The present invention relates to a semiconductor device manufacturing method comprising a silicon wafer back grinding step, a wafer dicing step, and a chip pick-up step, and a semiconductor wafer processing apparatus used in this manufacturing method, particularly when a so-called in-line process is employed. The present invention relates to a method for manufacturing a semiconductor device and a semiconductor wafer processing apparatus that can reduce pickup defects in a chip pickup process as a final process.

近年、ICカードの普及が進み、さらなる薄型化が望まれている。このため、従来は厚さが350μm程度であった半導体チップを、厚さ50〜100μmあるいはそれ以下まで薄くする必要が生じている。また、生産性を向上するためウエハの大口径化が検討されてきた。   In recent years, IC cards have been widely used, and further reduction in thickness has been desired. For this reason, it is necessary to reduce the thickness of a semiconductor chip, which has conventionally been about 350 μm, to a thickness of 50 to 100 μm or less. In addition, increasing the diameter of the wafer has been studied in order to improve productivity.

回路パターン形成後にウエハ裏面を研削することは従来より行われており、その際、回路面に表面保護シートを貼付して、回路面の保護およびウエハの固定を行い、裏面研削を行っている。その後、ダイシング、ダイボンド、樹脂封止等の各種の工程を経て、半導体装置が製造されることになる。   Grinding the back surface of a wafer after forming a circuit pattern has been conventionally performed. At that time, a surface protection sheet is attached to the circuit surface to protect the circuit surface and fix the wafer, and then perform back surface grinding. Thereafter, the semiconductor device is manufactured through various processes such as dicing, die bonding, and resin sealing.

半導体ウエハをダイシングし、チップ化する際には、半導体ウエハの裏面(研削面)にダイシングテープが貼着され、ダイシングテープ上にウエハを保持しつつウエハのダイシングを行っている。ダイシングテープとしては、種々のものが上市されているが、特にUVテープと呼ばれる紫外線硬化型粘着テープが好ましく用いられている。UVテープは、紫外線照射により粘着剤層が硬化し、接着力が消失または激減する性質を有する。したがって、ウエハのダイシング時には、十分な接着力でウエハを固定することができ、ダイシング終了後には粘着剤層を紫外線硬化させることで、チップを容易にピックアップできる。   When dicing a semiconductor wafer into chips, a dicing tape is attached to the back surface (ground surface) of the semiconductor wafer, and the wafer is diced while holding the wafer on the dicing tape. Various dicing tapes are on the market, and in particular, an ultraviolet curable adhesive tape called a UV tape is preferably used. The UV tape has a property that the pressure-sensitive adhesive layer is cured by irradiation with ultraviolet rays, and the adhesive force is lost or drastically reduced. Therefore, at the time of dicing the wafer, the wafer can be fixed with sufficient adhesive force, and the chip can be easily picked up by curing the pressure-sensitive adhesive layer after completion of dicing.

ダイシングテープを貼着するために、裏面研削が終了したウエハは、その後、ダイシングテープ貼着装置(マウンター)に移送されることになる。この際、ウエハはウエハカセットと呼ばれる収容装置に収容され、マウンターへと移送される。   In order to attach the dicing tape, the wafer after the back surface grinding is transferred to a dicing tape attaching device (mounter). At this time, the wafer is stored in a storage device called a wafer cassette and transferred to the mounter.

しかし、ウエハを極薄に研削するとウエハ自身に自己支持性がなくなり、自重でさえ破損する可能性がでてくる。このため、極薄にまで研削されたウエハを、それ自体でウエハカセットに収容することは困難である。   However, if the wafer is ground to an extremely thin thickness, the wafer itself loses its self-supporting property and may be damaged even by its own weight. For this reason, it is difficult to house a wafer ground to an extremely thin thickness in a wafer cassette.

強度が低下した半導体ウエハに支持機能を与えるため、プロセスのインライン化、すなわち、裏面研削終了後、直ちに研削面にダイシングテープを貼着し、その後、ダイシング工程に移送することが提案されている。たとえば、特許文献1には、このようなインライン化プロセスの一例が記載されている。このようなプロセスによれば、極薄にまで研削され強度が低下したウエハであっても、その裏面がダイシングテープにより補強されるため、支持機能が向上し、前記したウエハカセットによる移送が可能になる。   In order to give a supporting function to a semiconductor wafer having a reduced strength, it has been proposed that a dicing tape is immediately attached to the grinding surface after the in-line process, that is, the back surface grinding, and then transferred to the dicing process. For example, Patent Document 1 describes an example of such an inlining process. According to such a process, even if the wafer is ground to a very thin thickness and has a reduced strength, the back surface is reinforced with dicing tape, so that the support function is improved and the wafer cassette can be transferred. Become.

しかし、このようなインライン化の結果、チップのピックアップ不良の増大という予期せぬ問題が発生した。これは、チップ裏面と粘着剤層との接着力が増大し、チップのピックアップが困難になるという問題であり、ダイシングテープとしてUVテープとを使用した場合においてもピックアップ不良は増大した。   However, as a result of such in-line implementation, an unexpected problem of increased chip pickup defects occurred. This is a problem that the adhesive force between the back surface of the chip and the pressure-sensitive adhesive layer increases, and it becomes difficult to pick up the chip. Even when a UV tape is used as the dicing tape, the pick-up failure increases.

この原因について、本発明者らが鋭意検討したところ、次の事実が判明した。
(1)インライン化プロセスでは、裏面研削終了後、直ちに研削面にダイシングテープを貼着しているため、裏面における酸化膜の形成はほとんど無い。
(2)一方、従来のプロセスでは、裏面研削終了後、ウエハカセットに収納し、裏面が露出した状態で移送した後、研削面にダイシングテープを貼着しているため、裏面が空気に曝される時間が長く、裏面における酸化膜の形成は、(1)に比して多い。
(3)酸化膜の形成が多いと、裏面と粘着剤層との間の親和性が弱く、一方、酸化膜の形成が少ないと、裏面と粘着剤層との間の親和性が強く、これがピックアップ不良の原因となる。
特開2002−343756号公報
When the present inventors diligently investigated the cause, the following facts were found.
(1) In the in-line process, since the dicing tape is adhered to the ground surface immediately after the back surface grinding is completed, there is almost no oxide film formation on the back surface.
(2) On the other hand, in the conventional process, after the backside grinding is completed, the wafer is stored in a wafer cassette, transferred with the backside exposed, and then the dicing tape is attached to the grinding surface, so the backside is exposed to air. The formation time of the oxide film on the back surface is longer than that in (1).
(3) When the formation of the oxide film is large, the affinity between the back surface and the pressure-sensitive adhesive layer is weak. On the other hand, when the formation of the oxide film is small, the affinity between the back surface and the pressure-sensitive adhesive layer is strong. It may cause pickup failure.
JP 2002-343756 A

本発明は、上記のような従来技術に鑑みてなされたものであって、裏面研削終了後直ちに研削面にダイシングテープを貼着するインライン化工程を含む半導体装置の製造方法において、ウエハ裏面での酸化膜の形成不足に起因するピックアップ不良を解消することを目的としている。   The present invention has been made in view of the prior art as described above, and in a semiconductor device manufacturing method including an in-line process in which a dicing tape is attached to a grinding surface immediately after completion of back surface grinding, An object of the present invention is to eliminate a pickup failure caused by insufficient formation of an oxide film.

本発明は、上記した(1)〜(3)の知見に基づいて完成されたものであって、裏面研削後、ダイシングテープの貼着前に、ウエハ裏面に意図的に酸化膜を形成することを特徴としている。すなわち、本発明に係る半導体装置の製造方法は、
表面に回路が形成されたシリコンウエハの裏面を研削する工程、
シリコンウエハ裏面を酸化処理し、酸化膜を形成する工程、
シリコンウエハ裏面にダイシングテープを貼着し、該ウエハをダイシングしチップ化する工程、および
シリコンチップをピックアップする工程を含む。
The present invention has been completed based on the above findings (1) to (3), and an oxide film is intentionally formed on the back surface of the wafer after the back surface grinding and before the dicing tape is attached. It is characterized by. That is, a method for manufacturing a semiconductor device according to the present invention includes:
Grinding the back surface of the silicon wafer having a circuit formed on the surface;
A step of oxidizing the back surface of the silicon wafer to form an oxide film;
It includes a step of attaching a dicing tape to the back surface of the silicon wafer, dicing the wafer into chips, and a step of picking up silicon chips.

上記の製造方法においては、シリコンウエハ裏面の酸化処理を、含酸素雰囲気中における短波長紫外線照射により行うことが好ましい。   In the above manufacturing method, it is preferable to perform the oxidation treatment on the back surface of the silicon wafer by short-wavelength ultraviolet irradiation in an oxygen-containing atmosphere.

本発明に係る半導体ウエハ加工装置の一態様では、ウエハの裏面研削装置と、ウエハ裏面への短波長紫外線照射装置とを備える。   One aspect of a semiconductor wafer processing apparatus according to the present invention includes a wafer back grinding apparatus and a short wavelength ultraviolet irradiation apparatus for the wafer back surface.

本発明に係る半導体ウエハ加工装置の他の態様では、ウエハ裏面への短波長紫外線照射装置と、ダイシングテープ貼着装置とを備える。   In another aspect of the semiconductor wafer processing apparatus according to the present invention, the semiconductor wafer processing apparatus includes a short-wavelength ultraviolet irradiation device for the wafer back surface and a dicing tape attaching device.

このような本発明に係る半導体装置の製造方法によれば、裏面研削終了後直ちに研削面にダイシングテープを貼着するインライン化工程を含む半導体装置の製造方法において、ウエハ裏面での酸化膜の形成不足に起因するピックアップ不良を低減することができる。   According to such a method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device including an in-line process in which a dicing tape is attached to the ground surface immediately after the back surface grinding is finished, the formation of the oxide film on the back surface of the wafer is performed. It is possible to reduce pickup defects due to the shortage.

以下、本発明について図面を参照しながらさらに具体的に説明する。   Hereinafter, the present invention will be described more specifically with reference to the drawings.

本発明に係る半導体装置の製造方法においては、図1に示すように、まず表面に回路が形成されたシリコンウエハ1の裏面を研削する。   In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1, first, the back surface of the silicon wafer 1 on which a circuit is formed is ground.

ウエハ表面への回路の形成は、エッチング法、リフトオフ法などの従来より汎用されている方法を含む、様々な方法により行うことができる。半導体ウエハの回路形成工程にお
いて、所定の回路が形成される。このようなウエハ1の研削前の厚みは特に限定はされないが、通常は650〜750μm程度である。
Formation of a circuit on the wafer surface can be performed by various methods including conventionally used methods such as an etching method and a lift-off method. In the semiconductor wafer circuit forming step, a predetermined circuit is formed. The thickness of the wafer 1 before grinding is not particularly limited, but is usually about 650 to 750 μm.

また、裏面研削時には、表面の回路を保護するために、回路面に表面保護シート2に貼付しておくことが好ましい。表面保護シート2としては、この種の用途に用いられている各種の再剥離可能な粘着シートが特に制限されることなく用いられる。   Moreover, it is preferable to affix on the surface protection sheet 2 to a circuit surface in order to protect a surface circuit at the time of back surface grinding. As the surface protective sheet 2, various releasable pressure-sensitive adhesive sheets used for this type of application are used without particular limitation.

裏面の研削は、グラインダー3およびウエハ固定のための吸着テーブル4等を用いた公知の手法により行われる。裏面研削工程の後、酸化膜を形成する工程の前には、研削によって生成した破砕層を除去する処理が行われてもよい。研削面に対し破砕層を除去する処理を行った直後は、処理面は酸化膜が除去されたままの場合が多い。このような処理としてはケミカルエッチング、プラズマエッチング、CMP (Chemical Mechanical Etching)等が挙げられる。   The back surface is ground by a known method using a grinder 3 and a suction table 4 for fixing the wafer. After the back surface grinding step, before the step of forming the oxide film, a process of removing the crushed layer generated by grinding may be performed. Immediately after performing the process of removing the crushed layer on the ground surface, the oxide film is often removed from the treated surface. Examples of such treatment include chemical etching, plasma etching, and CMP (Chemical Mechanical Etching).

本発明の目的によれば、極薄の加工に好適なインライン処理に適合するため、その裏面研削による仕上げ厚は、好ましくは20〜100μm程度である。しかし、通常の工程にも適用可能であるため、100〜400μm程度の通常の仕上げ厚でも適用可能である。   According to the object of the present invention, in order to adapt to in-line processing suitable for ultra-thin processing, the finished thickness by back grinding is preferably about 20 to 100 μm. However, since it can be applied to a normal process, a normal finish thickness of about 100 to 400 μm is also applicable.

このような裏面研削によりウエハが所定の厚みとなり、同時に、回路形成時にウエハ裏面に形成された酸化膜が除去される。   By such back surface grinding, the wafer has a predetermined thickness, and at the same time, the oxide film formed on the back surface of the wafer during circuit formation is removed.

本発明では、このような裏面研削が終了したウエハ1の裏面に、酸化処理を施し、酸化膜を形成することを特徴としている。酸化膜が形成されていないウエハ裏面にダイシングテープを貼付すると、裏面とダイシングテープの粘着剤層との親和性が高すぎるため、後述するピックアップ工程におけるピックアップ不良の原因となる。一方、裏面に酸化膜を形成しておくと、裏面と粘着剤層との間の相互作用が小さく、ピックアップ不良を低減することができる。   The present invention is characterized in that the back surface of the wafer 1 after such back surface grinding is subjected to an oxidation treatment to form an oxide film. If a dicing tape is attached to the back surface of the wafer on which no oxide film is formed, the affinity between the back surface and the pressure-sensitive adhesive layer of the dicing tape is too high, which causes a pickup failure in the pickup process described later. On the other hand, when an oxide film is formed on the back surface, the interaction between the back surface and the pressure-sensitive adhesive layer is small, and pickup defects can be reduced.

裏面の酸化処理は、種々の方法により行われる。たとえば、ウエハ表面に回路を形成するために種々の酸化処理方法が知られているが、本発明ではこのような公知の表面酸化の方法を用いてウエハ裏面の酸化処理を行い、酸化膜を形成することができる。   The back surface oxidation treatment is performed by various methods. For example, various oxidation treatment methods are known for forming circuits on the wafer surface. In the present invention, oxidation treatment is performed on the back surface of the wafer using such a known surface oxidation method to form an oxide film. can do.

より具体的には、以下のような(1)〜(8)の手法を採用することができる。
(1)密閉可能な短波長紫外線照射装置10を用いて、含酸素雰囲気中における短波長紫外線照射により行う。
More specifically, the following methods (1) to (8) can be employed.
(1) Performed by short-wavelength ultraviolet irradiation in an oxygen-containing atmosphere using the sealable short-wavelength ultraviolet irradiation apparatus 10.

短波長紫外線とは、波長が150〜300nm程度の紫外線を意味し、特に低圧水銀ランプ(185nm)、エキシマランプ(172nm)等の短波長光源5が好ましく用いられる。このような短波長紫外線の照射を含酸素雰囲気中で行うと、オゾン、酸素ラジカルが発生し、ウエハ裏面に効率良く酸化膜を形成することができる。   The short wavelength ultraviolet ray means an ultraviolet ray having a wavelength of about 150 to 300 nm, and a short wavelength light source 5 such as a low pressure mercury lamp (185 nm) or an excimer lamp (172 nm) is particularly preferably used. When such short-wavelength ultraviolet irradiation is performed in an oxygen-containing atmosphere, ozone and oxygen radicals are generated, and an oxide film can be efficiently formed on the back surface of the wafer.

紫外線照射量は好ましくは100〜6000mJ/cm2、さらに好ましくは300〜2
000mJ/cm2である。また照射雰囲気における酸素濃度は、通常の空気濃度(20%程度)で使用可能であり、同程度の酸素分圧があれば減圧下での照射であってもよい。また、積極的に高濃度酸素を紫外線照射領域に供給してもよい。
(2)含酸素雰囲気中におけるプラズマ処理により行う。
(3)陽極酸化により行う。
(4)酸素イオンの打ち込みにより行う。
(5)スパッタリングにより行う。
(6)CVD (Chemical Vapor Deposition)により行う。
(7)水または砥粒を含む水を含ませた軟質樹脂製の摺動面を有するポリッシャでウエハ裏面を摩擦摺動させることにより行う(特開平6−192810号公報参照)。
(8)オゾン溶液やアンモニア過水溶液、塩酸過水溶液、硫酸過水溶液等の酸化剤溶液をウエハ裏面に供給することで行う。
The amount of ultraviolet irradiation is preferably 100 to 6000 mJ / cm 2 , more preferably 300 to 2
000 mJ / cm 2 . The oxygen concentration in the irradiation atmosphere can be used at a normal air concentration (about 20%), and irradiation under reduced pressure may be used as long as the oxygen partial pressure is the same. Alternatively, high concentration oxygen may be positively supplied to the ultraviolet irradiation region.
(2) Performed by plasma treatment in an oxygen-containing atmosphere.
(3) Performed by anodization.
(4) Performed by implantation of oxygen ions.
(5) Performed by sputtering.
(6) Performed by CVD (Chemical Vapor Deposition).
(7) It is carried out by rubbing and sliding the back surface of the wafer with a polisher having a sliding surface made of soft resin containing water or water containing abrasive grains (see JP-A-6-192810).
(8) An oxidant solution such as an ozone solution, an ammonia aqueous solution, a hydrochloric acid aqueous solution, or a sulfuric acid aqueous solution is supplied to the back surface of the wafer.

これらの中でも、上記(1)の手法は、装置が簡便でありまたドライプロセスであることから好ましく採用される。   Among these, the method (1) is preferably employed because the apparatus is simple and is a dry process.

ウエハ1裏面の酸化処理は、ウエハ1の裏面研削後、直ちに行われる。具体的には、後述する本発明の半導体ウエハ加工装置を用いることで、工程を連続して行えるようになるので、ウエハ1の裏面研削後0.5〜5分程度で、ウエハ1の裏面の酸化処理を行うことができる。   The oxidation treatment of the back surface of the wafer 1 is performed immediately after the back surface of the wafer 1 is ground. Specifically, by using the semiconductor wafer processing apparatus of the present invention, which will be described later, the process can be continuously performed. Therefore, after the backside grinding of the wafer 1, about 0.5 to 5 minutes, An oxidation treatment can be performed.

このような酸化処理によりウエハ裏面に形成される酸化膜は、SiOx(xは0〜2の
任意の値)であり、酸化処理が充分であれば酸化膜はSiO2となり、ウエハ研削面は不
活性表面となる。酸化が不充分であったり行われなかった場合は、xは0に近い値となり、研削直後のウエハ研削面は活性な状態でダイシングテープの粘着剤と化学反応か、または何らかの相互作用を引き起こす。
Such oxide film formed on the wafer back surface by oxidation treatment is a SiOx (x is an arbitrary value of 0 to 2), oxide film SiO 2 becomes long is sufficient oxidizing treatment, the wafer grinding surface not It becomes the active surface. When the oxidation is insufficient or not performed, x becomes a value close to 0, and the wafer grinding surface immediately after grinding causes a chemical reaction or some kind of interaction with the adhesive of the dicing tape in an active state.

酸化膜におけるシリコン中の酸素濃度は、XPS(X-ray Photoelectron Spectroscopy)によって(O/Si値)として検出される。酸化膜の厚みは直接測定することが困難なため、XPSの測定における検出角度を変化させて(O/Si値)を測定することにより、推測される。検出角度が大きい(90°に近い)と比較的深部の酸素濃度を測定でき、検出角度が小さいと比較的浅部の酸素濃度を測定できる。   The oxygen concentration in silicon in the oxide film is detected as (O / Si value) by XPS (X-ray Photoelectron Spectroscopy). Since it is difficult to directly measure the thickness of the oxide film, it is estimated by measuring (O / Si value) while changing the detection angle in the XPS measurement. When the detection angle is large (close to 90 °), the oxygen concentration in a relatively deep portion can be measured, and when the detection angle is small, the oxygen concentration in a relatively shallow portion can be measured.

次いで、ウエハの裏面にダイシングテープ6を貼付する。ダイシングテープ6の貼付は、図3に示すように、ローラー7を備えたマウンターと呼ばれる装置により行われるのが一般的だが、特に限定はされない。   Next, a dicing tape 6 is attached to the back surface of the wafer. As shown in FIG. 3, the dicing tape 6 is generally attached by a device called a mounter provided with a roller 7, but is not particularly limited.

ダイシングテープ6としては、この種の用途に用いられている各種の粘着テープが特に制限されることなく用いられるが、特にUVテープと呼ばれる紫外線硬化型粘着テープが、小さいピックアップ力を必要とするデバイスに多く使用されるため、その効果が顕著であり、好ましく用いられる。   As the dicing tape 6, various adhesive tapes used for this type of application are used without particular limitation, and in particular, an ultraviolet curable adhesive tape called a UV tape requires a small pickup force. Therefore, the effect is remarkable and it is preferably used.

ウエハ1の裏面の酸化処理が完了していれば、既にウエハ研削面と粘着剤との相互作用が低減しピックアップ力が小さくなっているので、ウエハ研削面にダイシングテープを貼付するまでどれだけ放置する期間があっても問題はない。また、ウエハ研削後酸化処理を施す時間がどの程度であっても、ウエハ研削処理の後酸化処理を施せばウエハ研削面は安定した酸化膜となっているので、問題はない。   If the oxidation treatment on the back surface of the wafer 1 is completed, the interaction between the wafer grinding surface and the adhesive has already been reduced and the pick-up force has been reduced, so how much is left until the dicing tape is applied to the wafer grinding surface. There is no problem even if there is a period to do. Moreover, no matter what time the oxidation treatment is performed after wafer grinding, there is no problem because the wafer grinding surface becomes a stable oxide film if the oxidation treatment after wafer grinding is performed.

しかし、グラインダーとダイシングテープ貼付装置が一体となったインライン処理装置において、本発明の課題が顕著に現れる。したがって、ウエハ研削工程とウエハ裏面の酸化処理との間、およびウエハ裏面の酸化処理とダイシングテープの貼付工程との間は、それぞれ時間をおかずに、たとえば0.5〜3分程度で行うことが好ましい。   However, in the in-line processing apparatus in which the grinder and the dicing tape attaching apparatus are integrated, the problem of the present invention appears remarkably. Therefore, between the wafer grinding process and the oxidation process on the back surface of the wafer, and between the oxidation process on the wafer back surface and the application process of the dicing tape, it takes about 0.5 to 3 minutes, for example, without taking time. preferable.

ウエハ1のダイシング時には、ダイシングテープ6の周辺部を、リングフレーム8により固定した後(図4参照)、ダイサーなどの回転丸刃を用いるなどの公知の手法により、ウエハのチップ化を行う(図5参照)。表面保護シート2は、ダイシングテープ6の貼着後、任意の段階で剥離される。   When dicing the wafer 1, the peripheral portion of the dicing tape 6 is fixed by the ring frame 8 (see FIG. 4), and then the wafer is chipped by a known method such as using a rotating round blade such as a dicer (see FIG. 4). 5). The surface protective sheet 2 is peeled off at any stage after the dicing tape 6 is attached.

次いで、得られたチップ9を、ダイシングテープ6からピックアップする。チップのピックアップは、回路面側から吸引コレットを用いて行うのが一般的であり、またコレットによる吸引と同時に、ダイシングテープ6側から突き上げピンによりチップを押し上げてもよい。また、ダイシングテープ6としてUVテープを用いた場合には、チップのピックアップに先立ち、粘着剤層に紫外線照射し、接着力を低下させておくことが好ましい。   Next, the obtained chip 9 is picked up from the dicing tape 6. The pickup of the chip is generally performed using a suction collet from the circuit surface side, and at the same time as the suction by the collet, the chip may be pushed up from the dicing tape 6 side by a push-up pin. Further, when a UV tape is used as the dicing tape 6, it is preferable to reduce the adhesive force by irradiating the pressure-sensitive adhesive layer with ultraviolet rays prior to chip pickup.

本発明によれば、シリコンウエハの裏面に酸化膜を形成しておくことで、裏面とダイシングテープの粘着剤層との間での相互作用が小さくなるため、ピックアップ不良を低減することができる。   According to the present invention, by forming the oxide film on the back surface of the silicon wafer, the interaction between the back surface and the pressure-sensitive adhesive layer of the dicing tape is reduced, so that pickup defects can be reduced.

本発明に係る第1の半導体ウエハ加工装置は、従来公知のウエハ裏面研削装置(グラインダー)に短波長紫外線照射装置を備えた装置である。短波長紫外線照射装置はウエハの研削面に照射可能なように、ウエハ研削加工のための位置よりも下流側に位置し、さらに下流側にウエハストッカーが位置する。短波長紫外線照射装置としては、短波長光源、好ましくは低圧水銀ランプ(185nm)、エキシマランプ(172nm)を備え、また必要に応じ酸素の供給口を有する密閉可能な容器を備える。また、ウエハ研削加工のための位置と短波長紫外線照射装置の間には、ケミカルエッチング装置、プラズマエッチング装置やCMP装置等の破砕層を除去するための装置が配置されてもよい。   The first semiconductor wafer processing apparatus according to the present invention is an apparatus provided with a short-wavelength ultraviolet irradiation apparatus in a conventionally known wafer back surface grinding apparatus (grinder). The short-wavelength ultraviolet irradiation device is located downstream from the position for wafer grinding so that the grinding surface of the wafer can be irradiated, and a wafer stocker is located further downstream. The short-wavelength ultraviolet irradiation device includes a short-wavelength light source, preferably a low-pressure mercury lamp (185 nm), an excimer lamp (172 nm), and a sealable container having an oxygen supply port as necessary. In addition, an apparatus for removing a crushed layer such as a chemical etching apparatus, a plasma etching apparatus, or a CMP apparatus may be disposed between the position for wafer grinding and the short wavelength ultraviolet irradiation apparatus.

このような構成の半導体ウエハ加工装置を使用すれば、ウエハの裏面研削を行った直後に研削面の酸化処理を行うことができ、研削工程の後任意の放置時間をおいてダイシングテープの貼付作業を行うことができるようになる。   If the semiconductor wafer processing apparatus having such a configuration is used, the grinding surface can be oxidized immediately after the backside grinding of the wafer, and the dicing tape is affixed after an arbitrary standing time after the grinding process. Will be able to do.

本発明に係る第2の半導体ウエハ加工装置は、従来公知のダイシングテープ貼着装置に短波長紫外線照射装置を備えた装置である。短波長紫外線照射装置はダイシングテープの貼付前にウエハ研削面に照射可能なように、テープの貼付位置よりも上流側に位置する。さらに上流側にウエハストッカーが配置されてもよい。また、短波長紫外線照射装置とテープ貼付位置との間には、上述の破砕層を除去するための装置が配置されてもよい。このような構成の半導体ウエハ加工装置を使用すれば、ダイシングテープを貼付するときには、必ずウエハの研削面が十分に酸化され化学的に安定する。このため、研削工程の後任意の放置期間をおいたウエハに対してダイシングテープの貼付を行ってもピックアップ力が増大することはない。   The second semiconductor wafer processing apparatus according to the present invention is an apparatus including a conventionally known dicing tape attaching apparatus and a short wavelength ultraviolet irradiation apparatus. The short wavelength ultraviolet irradiation device is located upstream of the tape application position so that the wafer grinding surface can be irradiated before the dicing tape is applied. Further, a wafer stocker may be arranged on the upstream side. Moreover, the apparatus for removing the above-mentioned crushing layer may be arrange | positioned between a short wavelength ultraviolet irradiation device and a tape sticking position. When the semiconductor wafer processing apparatus having such a configuration is used, the wafer grinding surface is always sufficiently oxidized and chemically stabilized when a dicing tape is applied. For this reason, the pick-up force does not increase even if the dicing tape is applied to the wafer that has been left for an arbitrary period after the grinding step.

さらに、ウエハの裏面研削装置、短波長紫外線照射装置、ダイシングテープ貼着装置が、この順で配置されたインライン対応の加工装置であってもよい。このような装置であれば、ダイシングテープの貼付がウエハの裏面研削の直後であっても、酸化処理を経ることにより、チップのピックアップ力の増大を防ぐことができる。   Further, the wafer back grinding device, the short wavelength ultraviolet irradiation device, and the dicing tape attaching device may be an inline-compatible processing device arranged in this order. With such an apparatus, an increase in chip pick-up force can be prevented by performing an oxidation treatment even if the dicing tape is applied immediately after the back surface grinding of the wafer.

このような本発明に係る半導体ウエハ加工装置によれば、裏面研削終了後、直ちに研削面にダイシングテープを貼着するプロセスのインライン化が可能となり、さらにウエハ裏面の酸化処理工程を工程間に介在させることで、インライン化にともなうピックアップ不良という問題が解消される。   According to such a semiconductor wafer processing apparatus according to the present invention, it is possible to in-line the process of adhering the dicing tape to the ground surface immediately after completion of the back surface grinding, and further, an oxidation treatment process on the back surface of the wafer is interposed between the processes. By doing so, the problem of poor pickup due to inlining is solved.

本発明に係る半導体装置の製造方法によれば、本発明によれば、シリコンウエハの裏面に酸化膜を形成しておくことで、裏面とダイシングテープの粘着剤層との間での相互作用が小さくなるため、ピックアップ不良を低減することができ、生産効率の向上が達成される。
(実施例)
以下、本発明を実施例により説明するが、本発明はこれら実施例に限定されるものでは
ない。
(実施例1)
未処理のシリコンウエハ(200mm径)をウエハ研削装置(ディスコ社製、DFG-840)を用いて仕上げ厚が350μmとなるまで研削を行った。研削したウエハを短波長紫外線照射装
置(オーク製作所製、VUM-3037-F、低圧水銀ランプ使用、紫外線波長185nm、254nm)にセットし、研削後30秒以内に照射を行った。紫外線の照射条件は、照度約10mW/cm2、光量1800mJ/cm2、照射時間3分、照射距離15mmで行った。
According to the method for manufacturing a semiconductor device according to the present invention, according to the present invention, by forming an oxide film on the back surface of the silicon wafer, the interaction between the back surface and the adhesive layer of the dicing tape is achieved. Therefore, pickup defects can be reduced, and improvement in production efficiency is achieved.
(Example)
EXAMPLES Hereinafter, although an Example demonstrates this invention, this invention is not limited to these Examples.
(Example 1)
An untreated silicon wafer (200 mm diameter) was ground using a wafer grinding apparatus (DFG-840, DFG-840) until the finished thickness was 350 μm. The ground wafer was set in a short-wavelength ultraviolet irradiation device (manufactured by Oak Manufacturing Co., Ltd., VUM-3037-F, using a low-pressure mercury lamp, ultraviolet wavelengths 185 nm and 254 nm) and irradiated within 30 seconds after grinding. The ultraviolet irradiation conditions were an illuminance of about 10 mW / cm 2 , a light amount of 1800 mJ / cm 2 , an irradiation time of 3 minutes, and an irradiation distance of 15 mm.

ダイシングテープとして、紫外線硬化型粘着テープ(リンテック社製Adwill D675)を
用いた。
As the dicing tape, an ultraviolet curable adhesive tape (Adwill D675 manufactured by Lintec Corporation) was used.

照射後30秒以内でウエハの研削面にダイシングテープを貼付し、その直後にダイシング装置(東京精密社製、A-WD-4000B)でウエハを10mm×10mmサイズにダイシングを行った。続いて、すぐに紫外線照射装置(リンテック社製、RAD2000m/8、紫外線波長領域365nm
)で紫外線を照射してダイシングテープの粘着剤層を硬化した。先端にニードルを設けた荷重測定器を用いてチップを突き上げ、ピックアップ力を測定した。
Within 30 seconds after irradiation, a dicing tape was affixed to the ground surface of the wafer, and immediately after that, the wafer was diced to a size of 10 mm × 10 mm with a dicing apparatus (A-WD-4000B, manufactured by Tokyo Seimitsu Co., Ltd.). Next, immediately UV irradiation equipment (Rintec, RAD2000m / 8, UV wavelength region 365nm
) Was irradiated with ultraviolet rays to cure the adhesive layer of the dicing tape. The tip was pushed up using a load measuring device provided with a needle at the tip, and the pick-up force was measured.

また、同様の工程でダイシングを行わないだけのサンプルを作成し、ダイシングテープのウエハの研削面に対する粘着力をJIS Z0237に準じて測定した。結果を表1に示す。
(実施例2)
実施例1において、ダイシングテープの貼付からダイシングまでの時間を24時間とした以外は実施例1と同様の工程を行った。ピックアップ力と粘着力の結果を表1に示す。(実施例3、4)
実施例1、2において、ダイシングテープとして非紫外線硬化型粘着テープ(リンテック社製、Adwill G-12)を使用し、ダイシング後の紫外線照射を行わなかった以外は、そ
れぞれ実施例1、2と同様の工程を行った。ピックアップ力と粘着力の結果を表1に示す。
(比較例1〜4)
実施例1〜4において、ウエハ研削直後の短波長紫外線照射を行わず、それに合わせてダイシングテープを貼付するまでの時間を調整して行った以外は、それぞれ実施例1〜4と同様の工程を行った。ピックアップ力と粘着力の結果を表1に示す。
In addition, a sample that was not diced in the same process was prepared, and the adhesive force of the dicing tape to the ground surface of the wafer was measured according to JIS Z0237. The results are shown in Table 1.
(Example 2)
In Example 1, the same process as in Example 1 was performed except that the time from dicing tape application to dicing was set to 24 hours. The results of pick-up force and adhesive strength are shown in Table 1. (Examples 3 and 4)
In Examples 1 and 2, a non-ultraviolet curable adhesive tape (Adwill G-12, manufactured by Lintec Co., Ltd.) was used as the dicing tape, and ultraviolet irradiation after dicing was not performed. The process was performed. The results of pick-up force and adhesive strength are shown in Table 1.
(Comparative Examples 1-4)
In Examples 1 to 4, the same steps as in Examples 1 to 4 were performed except that short-wavelength ultraviolet irradiation immediately after wafer grinding was not performed and the time until the dicing tape was applied was adjusted accordingly. went. The results of pick-up force and adhesive strength are shown in Table 1.

Figure 2005072140
Figure 2005072140

本発明に係る半導体装置の製造方法の1工程を示す。1 shows one step of a method of manufacturing a semiconductor device according to the present invention. 本発明に係る半導体装置の製造方法の1工程を示す。1 shows one step of a method of manufacturing a semiconductor device according to the present invention. 本発明に係る半導体装置の製造方法の1工程を示す。1 shows one step of a method of manufacturing a semiconductor device according to the present invention. 本発明に係る半導体装置の製造方法の1工程を示す。1 shows one step of a method of manufacturing a semiconductor device according to the present invention. 本発明に係る半導体装置の製造方法の1工程を示す。1 shows one step of a method of manufacturing a semiconductor device according to the present invention.

符号の説明Explanation of symbols

1…シリコンウエハ
2…表面保護シート
3…グラインダー
4…吸着テーブル
5…短波長光源
6…ダイシングテープ
7…ローラー
8…リングフレーム
9…チップ
10…短波長紫外線照射装置
DESCRIPTION OF SYMBOLS 1 ... Silicon wafer 2 ... Surface protection sheet 3 ... Grinder 4 ... Suction table 5 ... Short wavelength light source 6 ... Dicing tape 7 ... Roller 8 ... Ring frame 9 ... Chip 10 ... Short wavelength ultraviolet irradiation device

Claims (4)

表面に回路が形成されたシリコンウエハの裏面を研削する工程、
シリコンウエハ裏面を酸化処理し、酸化膜を形成する工程、
シリコンウエハ裏面にダイシングテープを貼着し、該ウエハをダイシングしチップ化する工程、および
シリコンチップをピックアップする工程を含む半導体装置の製造方法。
Grinding the back surface of the silicon wafer having a circuit formed on the surface;
A step of oxidizing the back surface of the silicon wafer to form an oxide film;
A method for manufacturing a semiconductor device, comprising: attaching a dicing tape to a back surface of a silicon wafer; dicing the wafer into chips; and picking up silicon chips.
前記シリコンウエハ裏面の酸化処理を、含酸素雰囲気中における短波長紫外線照射により行う請求項1に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation treatment of the back surface of the silicon wafer is performed by short-wave ultraviolet irradiation in an oxygen-containing atmosphere. ウエハの裏面研削装置と、ウエハ裏面への短波長紫外線照射装置とを備える半導体ウエハ加工装置。 A semiconductor wafer processing apparatus comprising a wafer back surface grinding device and a short wavelength ultraviolet irradiation device for the wafer back surface. ウエハ裏面への短波長紫外線照射装置と、ダイシングテープ貼着装置とを備える半導体ウエハ加工装置。 A semiconductor wafer processing apparatus comprising a short-wavelength ultraviolet irradiation device on a wafer back surface and a dicing tape sticking device.
JP2003297617A 2003-08-21 2003-08-21 Method of manufacturing semiconductor device and method of processing semiconductor wafer Pending JP2005072140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003297617A JP2005072140A (en) 2003-08-21 2003-08-21 Method of manufacturing semiconductor device and method of processing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003297617A JP2005072140A (en) 2003-08-21 2003-08-21 Method of manufacturing semiconductor device and method of processing semiconductor wafer

Publications (1)

Publication Number Publication Date
JP2005072140A true JP2005072140A (en) 2005-03-17

Family

ID=34403415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003297617A Pending JP2005072140A (en) 2003-08-21 2003-08-21 Method of manufacturing semiconductor device and method of processing semiconductor wafer

Country Status (1)

Country Link
JP (1) JP2005072140A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005210038A (en) * 2003-12-26 2005-08-04 Renesas Technology Corp Fabrication method of semiconductor integrated circuit device
JP2007027577A (en) * 2005-07-20 2007-02-01 Disco Abrasive Syst Ltd Processing device and method
JP2007220863A (en) * 2006-02-16 2007-08-30 Nitto Denko Corp Active surface-pasted dicing adhesive tape or sheet, and method of picking up cutting of workpiece
JP2007220694A (en) * 2005-05-16 2007-08-30 Nitto Denko Corp Adhseive sheet and method of processing workpiece using the same
JP2008060434A (en) * 2006-09-01 2008-03-13 Nitto Denko Corp Active surface attachment adhesive tape or sheet for dicing and pickup method for cut piece of workpiece
JP2010239161A (en) * 2003-12-26 2010-10-21 Renesas Electronics Corp Method of fabricating semiconductor integrated circuit device
JP2013236098A (en) * 2013-07-17 2013-11-21 Lintec Corp Wafer processing sheet

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6438209A (en) * 1987-08-04 1989-02-08 Nec Corp Preparation of semiconductor device
JPH1126450A (en) * 1997-07-01 1999-01-29 Matsushita Electron Corp Formation of silicon oxide film
JPH11162883A (en) * 1997-11-25 1999-06-18 Sharp Corp Manufacture of semiconductor device
JP2000100756A (en) * 1998-09-25 2000-04-07 Fujitsu Ltd Manufacture of semiconductor device
JP2002305171A (en) * 2001-04-05 2002-10-18 Matsushita Electric Ind Co Ltd Method for processing surface of silicon substrate
JP2003045835A (en) * 2001-07-31 2003-02-14 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6438209A (en) * 1987-08-04 1989-02-08 Nec Corp Preparation of semiconductor device
JPH1126450A (en) * 1997-07-01 1999-01-29 Matsushita Electron Corp Formation of silicon oxide film
JPH11162883A (en) * 1997-11-25 1999-06-18 Sharp Corp Manufacture of semiconductor device
JP2000100756A (en) * 1998-09-25 2000-04-07 Fujitsu Ltd Manufacture of semiconductor device
JP2002305171A (en) * 2001-04-05 2002-10-18 Matsushita Electric Ind Co Ltd Method for processing surface of silicon substrate
JP2003045835A (en) * 2001-07-31 2003-02-14 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005210038A (en) * 2003-12-26 2005-08-04 Renesas Technology Corp Fabrication method of semiconductor integrated circuit device
JP2010239161A (en) * 2003-12-26 2010-10-21 Renesas Electronics Corp Method of fabricating semiconductor integrated circuit device
JP2007220694A (en) * 2005-05-16 2007-08-30 Nitto Denko Corp Adhseive sheet and method of processing workpiece using the same
JP2007027577A (en) * 2005-07-20 2007-02-01 Disco Abrasive Syst Ltd Processing device and method
US8025069B2 (en) 2005-07-20 2011-09-27 Disco Corporation Semiconductor wafer treating apparatus
JP2007220863A (en) * 2006-02-16 2007-08-30 Nitto Denko Corp Active surface-pasted dicing adhesive tape or sheet, and method of picking up cutting of workpiece
JP2008060434A (en) * 2006-09-01 2008-03-13 Nitto Denko Corp Active surface attachment adhesive tape or sheet for dicing and pickup method for cut piece of workpiece
JP2013236098A (en) * 2013-07-17 2013-11-21 Lintec Corp Wafer processing sheet

Similar Documents

Publication Publication Date Title
US7452787B2 (en) Fabrication method of semiconductor integrated circuit device
TWI618594B (en) Semiconductor wafer manufacturing method and mask integrated surface protection tape therefor
US5476566A (en) Method for thinning a semiconductor wafer
TW200903606A (en) Method for holding semiconductor wafer
JP4614416B2 (en) Semiconductor chip manufacturing method and dicing sheet pasting apparatus
WO2006008824A1 (en) Method for manufacturing semiconductor integrated circuit device
JP2003261842A (en) Tacky sheet for semiconductor wafer processing and method of its use
JP2004349649A (en) Thin processing method of wafer
JP2007165706A (en) Manufacturing method of semiconductor integrated circuit device
US20040097053A1 (en) Semiconductor wafer protective member and semiconductor wafer grinding method
JP4817291B2 (en) Manufacturing method of semiconductor wafer
JP2010239161A (en) Method of fabricating semiconductor integrated circuit device
JP2005072140A (en) Method of manufacturing semiconductor device and method of processing semiconductor wafer
JP2000216123A (en) Back surface grinding of wafer and dicing method
JP2003188129A (en) Device surface protection structure of device wafer
JP3906688B2 (en) Polishing cloth for semiconductor wafer and polishing method
JP2000331963A (en) Method and device for mounting wafer to wafer frame and facing device incorporating mounting device
KR20110055977A (en) Apartus for manufacturing semiconductor package and method for fabricating semiconductor package by using the same
CN108885986B (en) Method for forming protective film of semiconductor substrate
JPH04280446A (en) Manufacture of semiconductor device
JP5564785B2 (en) Manufacturing method of bonded substrate
JP4958287B2 (en) Peeling method in peeling device
JP2011216584A (en) Method of manufacturing semiconductor device
WO2001096065A1 (en) Method for polishing work
JP5196497B2 (en) Manufacturing method of semiconductor chip

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060517

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090120

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090122

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090323

A131 Notification of reasons for refusal

Effective date: 20091117

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Effective date: 20100112

Free format text: JAPANESE INTERMEDIATE CODE: A523

A131 Notification of reasons for refusal

Effective date: 20100622

Free format text: JAPANESE INTERMEDIATE CODE: A131

A02 Decision of refusal

Effective date: 20101019

Free format text: JAPANESE INTERMEDIATE CODE: A02