JPH04280446A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04280446A
JPH04280446A JP3068892A JP6889291A JPH04280446A JP H04280446 A JPH04280446 A JP H04280446A JP 3068892 A JP3068892 A JP 3068892A JP 6889291 A JP6889291 A JP 6889291A JP H04280446 A JPH04280446 A JP H04280446A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
semiconductor device
wafer
tape
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3068892A
Other languages
Japanese (ja)
Other versions
JP3094488B2 (en
Inventor
Hideo Yamanaka
英雄 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6889291A priority Critical patent/JP3094488B2/en
Publication of JPH04280446A publication Critical patent/JPH04280446A/en
Application granted granted Critical
Publication of JP3094488B2 publication Critical patent/JP3094488B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To reduce a defective rate and to improve yield by conducting a semiconductor device functional test, then grinding a rear surface, and then dicing it. CONSTITUTION:A semiconductor functional test in which a probe 2 is brought into contact with an electrode pad, is conducted at a semiconductor wafer 1 in which an opening of a pad film to a passivation film is finished. Then, an UV curing tape 3 is adhered to a surface 1a of the wafer 1. Thereafter, a rear surface 1b of the wafer 1 is ground. Then, the rear surface 1b of the wafer 1 is etched. Subsequently, the tape 3 is irradiated with UV so as to reduce its adhesive strength. Then, a UV irradiation for removing organic contaminants is conducted. Thereafter, the wafer 1 is lightly etched. Then, the wafer 1 is adhered to a die bonding tape 4, and diced to be pelletized.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置の製造方法
、特にパシベーション膜にパッド窓開けを終えた後半導
体装置機能テスト、裏面研削及びダイシングを行う半導
体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device, in which after pad windows are formed in a passivation film, a semiconductor device function test, backside grinding, and dicing are performed.

【0002】0002

【従来の技術】半導体ウェハのパシベーション膜にパッ
ド窓開けを終えた後に行う所謂半導体ウェハ後工程は、
従来、下記のように行われた。先ず、表面保護用のレジ
スト膜を半導体ウェハ表面に塗布し、該レジスト膜の表
面に硬質テープを貼り、その状態で裏面研削をして半導
体ウェハの厚さを所定の値にし、次いで該裏面研削によ
り半導体ウェハ裏面に生じた研削歪を除去すると共にウ
ェハの反りを小さくするために半導体ウェハの裏面エッ
チングを行い、次いで、半導体ウェハのペレットの電極
にプローブを当てての半導体装置機能テスト[2PC(
第2回目のペレットチェック)]を行い、不良ペレット
にはインクでドットマーキングをし、更にこのインクを
焼きつけ、その後、半導体ウェハの裏面をダイシングテ
ープに張り合せてダイシングすることによりペレタイズ
する。
[Prior Art] The so-called semiconductor wafer post-processing is performed after pad windows are opened in the passivation film of a semiconductor wafer.
Conventionally, this was done as follows. First, a resist film for surface protection is applied to the surface of the semiconductor wafer, a hard tape is applied to the surface of the resist film, the back side is ground in this state to make the thickness of the semiconductor wafer a predetermined value, and then the back side is ground. The back surface of the semiconductor wafer was etched to remove the grinding strain generated on the back surface of the semiconductor wafer and to reduce the warpage of the wafer, and then a semiconductor device function test [2PC (
A second pellet check) is carried out, and defective pellets are marked with dots using ink, and the ink is further burned into the wafer.Then, the back side of the semiconductor wafer is pasted onto a dicing tape and diced to pelletize the wafer.

【0003】0003

【発明が解決しようとする課題】ところで、上述した従
来の半導体ウェハ後工程ではパッケージの薄型化の要求
に対応しきれなくなりつつある。というのは、パッケー
ジの厚さを例えば1mm程度あるいはそれ以下にすると
いう要求が為されているが、それに応えるには半導体ペ
レットの厚さを250〜200μmあるいはそれ以下に
しなければならず、そのように薄く裏面研削した後に半
導体装置機能テストを行うと、半導体ウェハに割れ、欠
けが発生し易くなり、歩留り、品質が悪くなるからであ
る。
However, the above-mentioned conventional semiconductor wafer post-processing is becoming unable to meet the demand for thinner packages. This is because there is a demand to reduce the thickness of the package to, for example, 1 mm or less, but in order to meet this requirement, the thickness of the semiconductor pellet must be reduced to 250 to 200 μm or less. This is because if a semiconductor device function test is performed after grinding the back surface thinly, the semiconductor wafer is likely to crack or chip, resulting in poor yield and quality.

【0004】即ち、半導体装置機能テストは、プローブ
を半導体ウェハの電極パッドにあてて電気的に回路の機
能チェックを行うものであるが、正確なチェックを行う
には当然にプローブの半導体ウェハに対する圧力、即ち
針圧がある程度以上必要となる。従って、半導体ウェハ
が薄いとその針圧によって割れ、欠けが生じ易くなるの
である。
That is, in a semiconductor device function test, a probe is applied to the electrode pad of a semiconductor wafer to electrically check the function of the circuit, but in order to perform an accurate check, it is necessary to reduce the pressure of the probe on the semiconductor wafer. In other words, a certain level of stylus pressure is required. Therefore, if the semiconductor wafer is thin, it is more likely to crack and chip due to the stylus pressure.

【0005】本発明はこのような問題点を解決すべく為
されたものであり、半導体ウェハの割れ、欠けが発生す
るのを防止することを目的とし、更には半導体装置機能
テスト時につけたドットマーキングインクによる半導体
ウェハ表面の汚染を少なくすることを目的とする。
The present invention has been made to solve these problems, and aims to prevent the occurrence of cracks and chips in semiconductor wafers, and also to prevent dots placed during semiconductor device function tests. The purpose is to reduce contamination of semiconductor wafer surfaces by marking ink.

【0006】[0006]

【課題を解決するための手段】請求項1の半導体装置の
製造方法は、半導体装置機能テストを行ってから裏面研
削を行い、その後ダイシグを行うことを特徴とする。請
求項2の半導体装置の製造方法は、請求項1の半導体装
置の製造方法において、裏面研削を半導体ウェハ表面に
表面保護テープを貼着した状態で行い、裏面研削後該表
面保護テープを剥離することを特徴とする。
A method of manufacturing a semiconductor device according to claim 1 is characterized in that after performing a semiconductor device function test, back surface grinding is performed, and then dicing is performed. The method for manufacturing a semiconductor device according to claim 2 is the method for manufacturing a semiconductor device according to claim 1, in which backside grinding is performed with a surface protection tape affixed to the surface of the semiconductor wafer, and the surface protection tape is peeled off after backside grinding. It is characterized by

【0007】[0007]

【実施例】以下、本発明半導体装置の製造方法を図示実
施例に従って詳細に説明する。図1(A)乃至(I)は
本発明半導体装置の製造方法の一つの実施例を工程順に
示す断面図である。 (A)パシベーション膜に対するパッド窓開けを終えた
半導体ウェハ1に対して、図1の(A)に示すように電
極パッドにプローブ2をあてての半導体装置機能テスト
を行う。そして、不良のペレットに対してはインクでド
ットマーキングする。そして、マーキングした後、ドッ
トマーキングしたイクを焼き付ける。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention will be explained in detail below according to the illustrated embodiments. FIGS. 1A to 1I are cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps. (A) A semiconductor device function test is performed on the semiconductor wafer 1 after completing the pad window opening for the passivation film by applying the probe 2 to the electrode pad as shown in FIG. 1(A). Then, defective pellets are marked with ink dots. Then, after marking, the dot-marked orgasm is burned.

【0008】(B)次に、図1の(B)に示すように、
半導体ウェハ1の表面1aの表面にUV照射硬化型テー
プ3を貼付ける。これは、裏面研削の際に半導体ウェハ
1の表面1aを保護するためのもので、例えばSP−5
25、SP429、SP−45UM(いずれも商品名)
が用いられる。UV照射硬化型テープ3は半導体ウェハ
1の表面1aに対して強い接着力を有しており、裏面研
削時における半導体ウェハ1表面1a保護能力が強いの
みならず耐酸性が強く半導体ウェハ1裏面1bのエッチ
ング時にエッチング液(HFとHNO3 の混合溶液)
により侵されにくい。従って裏面エッチング厚さを必要
に応じて例えば30〜50μmと相当に厚くすることが
でき、延いては研磨歪を完璧に除去することを可能にす
るという効果をもたらす。また、UV照射硬化型テープ
3は紫外線照射を受けると粘着力が低下するという性質
を有している。そして、UV照射硬化型テープ3のこの
性質は本半導体装置の製造方法にとってきわめて有益で
ある。というのは、テープ3の剥離を容易にするからで
ある。具体的には、UV照射前には1000[g/25
mm]ある強い粘着力がUV照射により10〜20[g
/25mm]程度に低下し、きわめて容易に剥離できる
のである。
(B) Next, as shown in FIG. 1 (B),
A UV radiation curing tape 3 is attached to the front surface 1a of the semiconductor wafer 1. This is to protect the front surface 1a of the semiconductor wafer 1 during back grinding, and for example, SP-5
25, SP429, SP-45UM (all product names)
is used. The UV irradiation-curable tape 3 has strong adhesion to the front surface 1a of the semiconductor wafer 1, and not only has a strong ability to protect the front surface 1a of the semiconductor wafer 1 during back grinding, but also has strong acid resistance and protects the back surface 1b of the semiconductor wafer 1. Etching solution (mixed solution of HF and HNO3) during etching
less likely to be attacked by Therefore, the back surface etching thickness can be increased considerably, for example, from 30 to 50 .mu.m, as required, and this results in the effect that polishing distortion can be completely removed. Further, the UV radiation curable tape 3 has a property that its adhesive strength decreases when it is exposed to UV radiation. This property of the UV radiation curable tape 3 is extremely useful for the present semiconductor device manufacturing method. This is because the tape 3 can be easily peeled off. Specifically, 1000 [g/25
mm] strong adhesive strength can be increased by UV irradiation to 10~20[g
/25 mm] and can be peeled off very easily.

【0009】(C)次に、図1の(C)に示すように、
半導体ウェハ1の裏面1aを研削(BGR)する。これ
は、例えばワンパス(one pass) 方式で#4
000に仕上げ、インフィード(infeed)方式で
#1500に仕上げることにより行う。そして、半導体
ウェハ1の厚さは例えば150μm程度に仕上げる。
(C) Next, as shown in FIG. 1 (C),
The back surface 1a of the semiconductor wafer 1 is ground (BGR). This is, for example, #4 in the one pass method.
This is done by finishing it to #000 and finishing it to #1500 using an infeed method. Then, the thickness of the semiconductor wafer 1 is finished to be about 150 μm, for example.

【0010】(D)次に、図1の(D)に示すように、
半導体ウェハ1の裏面1bをエッチングする。このエッ
チングは半導体ウェハ1の裏面研削により生じた半導体
ウェハ1裏面1bの歪を除去するためのもので、例えば
フッ酸HFと硝酸HNO3 の混合溶液(HF:HNO
3 =1:10)をエッチング液として用い、研削歪を
除去するに必要な厚さエッチングする。例えば、7〜1
0μmで研削歪を充分に除去できる場合にはエッチング
時間は80秒程度である。しかし、厚さ30〜50μm
程度エッチングしなければ研削歪を除去できない場合に
は、300〜420秒程度エッチングする。尚、このよ
うに長くエッチングしても前述のとおりUV照射硬化型
テープ3には耐酸性があるので半導体ウェハ1の表面1
aが侵蝕される虞れはない。
(D) Next, as shown in FIG. 1 (D),
The back surface 1b of the semiconductor wafer 1 is etched. This etching is to remove distortions on the back surface 1b of the semiconductor wafer 1 caused by grinding the back surface of the semiconductor wafer 1. For example, a mixed solution of hydrofluoric acid HF and nitric acid HNO3 (HF:HNO3) is used.
3 = 1:10) as an etching solution, etching is performed to a thickness necessary to remove grinding distortion. For example, 7 to 1
If grinding strain can be sufficiently removed at 0 μm, the etching time is about 80 seconds. However, the thickness is 30-50μm
If the grinding strain cannot be removed without some etching, etching is performed for about 300 to 420 seconds. Incidentally, even if etching is performed for a long time in this way, the surface 1 of the semiconductor wafer 1 is
There is no risk that a will be eroded.

【0011】(E)次に、図1の(E)に示すように、
UV照射硬化型テープ3に対して粘着力低減のためにU
V照射を行う。このUV照射は高圧水銀灯により窒素雰
囲気で365nmの波長の紫外線を50〜100mW/
cm2 を約10秒/s程度照射する。これにより、前
述のとおり粘着力を1000(g/25mm)から10
〜20(g/25mm)程度に弱めることができる。
(E) Next, as shown in FIG. 1 (E),
U to reduce adhesion to UV irradiation curable tape 3
Perform V irradiation. This UV irradiation uses a high-pressure mercury lamp to emit ultraviolet rays with a wavelength of 365 nm at a rate of 50 to 100 mW in a nitrogen atmosphere.
cm2 for about 10 seconds/s. This increases the adhesive strength from 1000 (g/25 mm) to 10
It can be weakened to about 20 (g/25 mm).

【0012】(F)次に、図1の(F)に示すように、
有機物系汚染除去のためのUV照射を行う。このUV照
射は、半導体ウェハ1の裏面1aに対して酸化性雰囲気
で低圧水銀灯により253.7nmの波長の紫外線を4
0mW/cm2 の強さで約5〜10分間程度行う。こ
のUV照射は、雰囲気中の酸素分子O2 を酸素原子O
+Oに分解させ、分解により生じた酸素原子Oは酸素分
子O2 と結合してオゾンO3 をつくるために行う。 そして、このオゾンO3 が強い酸化力で有機物系汚染
を酸化分解するのでUV照射により有機物系汚染をクリ
ーニングすることができるのである。
(F) Next, as shown in FIG. 1 (F),
UV irradiation is performed to remove organic contamination. This UV irradiation is performed by irradiating 4 ultraviolet rays with a wavelength of 253.7 nm onto the back surface 1a of the semiconductor wafer 1 using a low-pressure mercury lamp in an oxidizing atmosphere.
The power is 0 mW/cm2 for about 5 to 10 minutes. This UV irradiation converts oxygen molecules O2 in the atmosphere into oxygen atoms O
This is done to decompose into +O, and the oxygen atoms O generated by the decomposition combine with oxygen molecules O2 to create ozone O3. Since this ozone O3 has strong oxidizing power to oxidize and decompose organic contamination, organic contamination can be cleaned by UV irradiation.

【0013】尚、工程(D)、(E)のUV照射は一つ
のUV照射装置を用いて連続的に行うことができる。た
だ、装置内を窒素パージして工程(D)のUV照射を行
い、その後外気を入れて酸素雰囲気にして工程(E)の
UV照射を行えば良い。というのは、UV照射装置は半
導体ウェハ1の表側からも裏側からも別の水銀灯で紫外
線を照射できるようになっているからである。また、U
V照射硬化型テープの粘着力低減を図るためのUV照射
と、半導体ウェハ裏面の有機物系汚染除去のためのUV
照射との順序を逆にしても良い。即ち、半導体ウェハ裏
面の有機物系汚染除去のためのUV照射[図1の(E)
]の方を先にし、UV照射硬化型テープの粘着力低減の
ためのUV照射[図1の(D)]の方を後にするように
しても良い。
Note that the UV irradiation in steps (D) and (E) can be performed continuously using one UV irradiation device. However, it is sufficient to perform the UV irradiation in step (D) while purging the inside of the apparatus with nitrogen, and then to perform the UV irradiation in step (E) by introducing outside air to create an oxygen atmosphere. This is because the UV irradiation device is capable of irradiating ultraviolet rays from both the front side and the back side of the semiconductor wafer 1 using separate mercury lamps. Also, U
UV irradiation to reduce the adhesive strength of V-irradiation curable tape and UV to remove organic contamination from the backside of semiconductor wafers
The order of irradiation may be reversed. That is, UV irradiation to remove organic contamination from the back surface of a semiconductor wafer [(E in FIG. 1)
] may be performed first, and UV irradiation [(D) in FIG. 1] for reducing the adhesive strength of the UV irradiation-curable tape may be performed later.

【0014】(G)次に、図1の(G)に示すように、
半導体ウェハ1をライトエッチングする。このライトエ
ッチングは工程(E)でのUV照射による酸化分解によ
り生じた低級酸化物を除去するためのもので、1%のフ
ッ酸水溶液を用いて行う。
(G) Next, as shown in (G) of FIG.
A semiconductor wafer 1 is light etched. This light etching is for removing lower oxides generated by oxidative decomposition due to UV irradiation in step (E), and is performed using a 1% hydrofluoric acid aqueous solution.

【0015】(H)次に、図1の(H)に示すように、
UV照射硬化型テープ3を剥離する。この剥離は前述の
工程(D)によりUV照射硬化型テープ3の粘着力が低
減されているので簡単且つ半導体ウェハ1に支障をきた
すことなく行うことができる。
(H) Next, as shown in (H) of FIG.
The UV irradiation curable tape 3 is peeled off. This peeling can be performed easily and without causing any trouble to the semiconductor wafer 1, since the adhesive force of the UV irradiation-curable tape 3 has been reduced in the above-mentioned step (D).

【0016】(I)次に、半導体ウェハ1をダイボンド
用テープ4に貼着して図1の(I)に示すようにダイシ
ングすることによりペレタイズする。1c、1c、…は
半導体ペレットである。
(I) Next, the semiconductor wafer 1 is attached to a die-bonding tape 4 and pelletized by dicing as shown in FIG. 1(I). 1c, 1c, . . . are semiconductor pellets.

【0017】本半導体装置の製造方法によれば、半導体
装置機能テストを裏面研削前の半導体ウェハ1が厚くし
かも反りが少ない状態のときに行うので、半導体装置機
能テスト(ペレットチェック)時にプローブ2、2、…
による針圧によって半導体ウェハ1に欠け、割れが生じ
にくくなる。また、裏面研削時における半導体ウェハ1
表面1a保護のためにUV照射硬化型テープ3を用いた
ので、UV照射硬化型テープ3剥離[工程(H)]の時
に不良を示すところの焼き付けられたマーキングインク
ドッチがUV照射硬化型テープ3と共に剥離されてしま
うので、マーキングインクドットによって半導体ウェハ
1の表面が汚れる虞れがなくなる。ちなみに、従来にお
いては裏面研削後に半導体装置機能テストを行うので表
面保護用のレジスト膜を剥離してもそれによってマーキ
ングインクドッチを除去できるということは有り得なか
った。
According to the present semiconductor device manufacturing method, since the semiconductor device function test is performed when the semiconductor wafer 1 is thick and has little warpage before back grinding, the probe 2, 2,...
The semiconductor wafer 1 is less likely to be chipped or cracked due to the stylus pressure. In addition, the semiconductor wafer 1 during back grinding
Since the UV irradiation curable tape 3 was used to protect the surface 1a, the baked marking ink dots that indicate defects when peeling off the UV irradiation curable tape 3 [step (H)] are removed from the UV irradiation curable tape 3. Since the marking ink dots are peeled off at the same time, there is no possibility that the surface of the semiconductor wafer 1 will be contaminated by the marking ink dots. Incidentally, in the past, since a semiconductor device function test was performed after back grinding, it was impossible to remove the marking ink dots even if the resist film for surface protection was peeled off.

【0018】従って、従来においては電極パッドがイン
クで汚染され、そのためワイヤボンディング不良が生じ
ることが少なくなかったのである。その点でも本半導体
装置の製造方法は優れているといえる。尚、本半導体装
置の製造方法において裏面研削時における半導体ウェハ
表面保護手段としてUV照射硬化型テープに代えて水溶
性接着テープ、例えばイクロステープ(三井東圧化学製
商品名)を用いてもテープ剥離の際にマーキングインク
ドットをテープと共に剥離できるという利点がある。し
かし、表面保護手段としてレジスト膜を用いた場合には
それは期待できない。ちなみに、水溶性接着性テープを
表面保護手段として用いた場合には、その除去は、単に
純水洗浄を行うことによって簡単に行うことができる。
Therefore, in the past, electrode pads were often contaminated with ink, which often resulted in defective wire bonding. In this respect as well, the present method for manufacturing a semiconductor device can be said to be excellent. In addition, in the manufacturing method of this semiconductor device, a water-soluble adhesive tape such as ICROSS tape (trade name manufactured by Mitsui Toatsu Chemical Co., Ltd.) may be used instead of the UV irradiation-curable tape as a means of protecting the surface of the semiconductor wafer during back grinding. There is an advantage that the marking ink dots can be peeled off together with the tape during peeling. However, this cannot be expected when a resist film is used as a surface protection means. Incidentally, when a water-soluble adhesive tape is used as a surface protection means, it can be easily removed by simply washing with pure water.

【0019】そして、本半導体装置の製造方法によれば
、半導体ウェハ保護手段としてレジスト膜を使用しない
ので間接材料(レジスト、レジスト剥離液)費が安くて
済むうえに、洗浄不足によるパッド汚染、Al配線膜表
面の変質の虞れもない。従って、歩留り、品質が向上し
、作業性も良くなる。
According to the present semiconductor device manufacturing method, since a resist film is not used as a means for protecting the semiconductor wafer, the cost of indirect materials (resist, resist stripping solution) is low, and pad contamination due to insufficient cleaning and Al There is no risk of deterioration of the wiring film surface. Therefore, yield and quality are improved, and workability is also improved.

【0020】[0020]

【発明の効果】請求項1の半導体装置の製造方法は、半
導体ウェハ表面にプローブをあてての半導体装置機能テ
ストを行い、次いで、半導体ウェハの裏面研削を行い、
しかる後、半導体ウェハをダイシングしてペレタイズす
ることを特徴とするものである。従って、請求項1の半
導体装置の製造方法によれば、半導体装置機能テストを
半導体ウェハの厚さを薄くする裏面研削前に行うので半
導体装置機能テスト時にプローブによる針圧によりある
いは半導体装置機能テストためのハンドリングにより半
導体ウェハが欠けたり、割れたりする虞れが少なくなり
、不良率を低下させ、歩留りを向上させることができる
。請求項2の半導体装置の製造方法は、裏面研削を半導
体ウェハの表面に表面保護テープを貼着した状態で行い
、裏面研削終了後上記表面保護テープを剥離することを
特徴とするものである。従って、請求項2の半導体装置
の製造方法によれば、半導体装置機能テスト時に付けら
れた不良を示すインクマーキングドットを表面保護テー
プを剥離するときに表面保護テープと共に除去すること
ができる。従って、インクマーキングドットにより半導
体装置表面の電極パッドや配線が汚染されるのを防止す
ることができる。そして、半導体ウェハ表面保護手段と
してレジストを使用しないのでそのレジスト自身及びそ
の剥離液等高価なレジスト工程用間接材料の使用量が少
なくて済み、更に、レジスト塗布、洗浄等の面倒な作業
も不要となる。従って、作業工数も少なくて済む。依っ
て、材料費、作業工数が低減され半導体装置のコストの
低減を図ることができる。
The method for manufacturing a semiconductor device according to claim 1 includes performing a semiconductor device function test by applying a probe to the surface of the semiconductor wafer, and then grinding the back surface of the semiconductor wafer.
After that, the semiconductor wafer is diced and pelletized. Therefore, according to the method for manufacturing a semiconductor device according to claim 1, since the semiconductor device function test is performed before back grinding to reduce the thickness of the semiconductor wafer, the semiconductor device function test is performed by stylus pressure from a probe during the semiconductor device function test or by the semiconductor device function test. This handling reduces the risk of semiconductor wafers being chipped or broken, reducing the defective rate and improving yield. A method of manufacturing a semiconductor device according to a second aspect of the present invention is characterized in that the backside grinding is performed with a surface protection tape attached to the front surface of the semiconductor wafer, and the surface protection tape is peeled off after the backside grinding is completed. Therefore, according to the method for manufacturing a semiconductor device according to the second aspect, ink marking dots indicating defects that are added during a semiconductor device function test can be removed together with the surface protection tape when the surface protection tape is peeled off. Therefore, it is possible to prevent the electrode pads and wiring on the surface of the semiconductor device from being contaminated by the ink marking dots. Furthermore, since resist is not used as a means of protecting the semiconductor wafer surface, the amount of resist itself and expensive indirect materials for the resist process, such as its stripping solution, can be reduced, and there is no need for troublesome work such as resist coating and cleaning. Become. Therefore, the number of work steps can be reduced. Therefore, material costs and work man-hours are reduced, and the cost of the semiconductor device can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】(A)乃至(I)は本発明半導体装置の製造方
法の一つの実施例を工程順に示す断面図である。
FIGS. 1A to 1I are cross-sectional views showing one embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps;

【符号の説明】[Explanation of symbols]

1  半導体ウェハ 1c  ペレット 2  プローブ 3  表面保護テープ 1 Semiconductor wafer 1c pellet 2 Probe 3 Surface protection tape

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  半導体ウェハ表面にプローブをあてて
の半導体装置機能テストを行い、次いで、半導体ウェハ
の裏面研削を行い、しかる後、半導体ウェハをダイシン
グしてペレタイズすることを特徴とする半導体装置の製
造方法。
1. A semiconductor device characterized by performing a semiconductor device function test by applying a probe to the surface of the semiconductor wafer, then grinding the back surface of the semiconductor wafer, and then dicing and pelletizing the semiconductor wafer. Production method.
【請求項2】  裏面研削を半導体ウェハの表面に表面
保護テープを貼着した状態で行い、裏面研削終了後上記
表面保護テープを剥離することを特徴とする請求項1記
載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the backside grinding is performed with a surface protection tape attached to the front surface of the semiconductor wafer, and the surface protection tape is peeled off after the backside grinding is completed. .
JP6889291A 1991-03-07 1991-03-07 Method for manufacturing semiconductor device Expired - Fee Related JP3094488B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6889291A JP3094488B2 (en) 1991-03-07 1991-03-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6889291A JP3094488B2 (en) 1991-03-07 1991-03-07 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04280446A true JPH04280446A (en) 1992-10-06
JP3094488B2 JP3094488B2 (en) 2000-10-03

Family

ID=13386763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6889291A Expired - Fee Related JP3094488B2 (en) 1991-03-07 1991-03-07 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3094488B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878487A (en) * 1994-08-31 1996-03-22 Nec Kyushu Ltd Semiconductor substrate and fabrication of semiconductor
US5972154A (en) * 1995-06-28 1999-10-26 Sony Corporation Methods of dicing flat workpieces
KR19990088109A (en) * 1998-05-08 1999-12-27 스미토모세이미쯔고교가부시키가이샤 Wet etching method and apparatus
US6462274B1 (en) 1998-10-31 2002-10-08 Amkor Technology, Inc. Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682486U (en) * 1993-04-30 1994-11-25 彰夫 片岡 Air supply / exhaust device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878487A (en) * 1994-08-31 1996-03-22 Nec Kyushu Ltd Semiconductor substrate and fabrication of semiconductor
US5972154A (en) * 1995-06-28 1999-10-26 Sony Corporation Methods of dicing flat workpieces
KR19990088109A (en) * 1998-05-08 1999-12-27 스미토모세이미쯔고교가부시키가이샤 Wet etching method and apparatus
US6462274B1 (en) 1998-10-31 2002-10-08 Amkor Technology, Inc. Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages

Also Published As

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