JP2005070557A - Spot size converter and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low cost, low loss spot size converter and to provide the manufacturing method thereof. <P>SOLUTION: This spot size converter is constituted such that a first core 2a sets the width and thickness dimensions in a manner fulfilling single mode conditions and that a second core 3a takes a shape in which the width and the thickness dimensions monotonously decrease toward the first core 2a. The width of the cores 2a, 3a are each controlled by patterning a silicon layer, i.e., a semiconductor layer formed on one surface of a substrate 1, and are designed so that both side surfaces of the first core 2a and those of the second core 3a continue smoothly. In addition, a second upper clad 3b is formed on the second core 3a on the side opposite to the substrate 1 in a manner that the distance from the upper clad 3b to the substrate 1 monotonously decreases toward the first core 2a, with the thickness thereby controlled, and with both surfaces in the thickness direction made smoothly continuous to those in the thickness direction of the first core 2a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a spot size converter and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, spot size converters that change the spot size of guided light are known in fields such as an optical communication system (see, for example, Patent Document 1).

  The spot size converter disclosed in Patent Document 1 has, for example, the configuration shown in FIG. That is, a lower clad layer 102 made of an amorphous material (for example, glass doped with Ge or Ti) is formed on one surface of a substrate 101 made of silicon, and a first mode condition is satisfied on the lower clad layer 102. The first core 103 and the second core 104 for spot size conversion whose cross-sectional area becomes smaller as the first core 103 is approached are formed, and the same amorphous as the lower cladding layer 102 so as to cover both the cores 103 and 104 An upper clad layer 105 made of a material is formed.

By the way, in the manufacture of the spot size converter disclosed in Patent Document 1, the lower cladding layer 102 is formed on one surface of the substrate 101 by a CVD method or the like, and then the lower cladding layer 102 is formed on the lower cladding layer 102. A first glass layer having a refractive index higher than that of the first glass layer is formed by a CVD method or the like, and then the first glass layer is patterned using a photolithography technique and an etching technique to form the first core 103, and then Then, a second glass layer made of the amorphous material is formed on the one surface side of the substrate 101 by a CVD method or the like, and then a part of the second glass layer is focused and irradiated with laser light. The second core 104 is formed by changing the partial refractive index. Note that the portion of the second glass layer excluding the above portion becomes the upper cladding layer 105.
JP 2000-249856 A (pages 4 to 6, FIGS. 1 to 4)

  However, in the spot size converter disclosed in Patent Document 1, the position of the first core 103 is determined by the mask used in the photolithography process, while the position of the second core 104 is the laser. Since it is determined by the position where the light is condensed and irradiated, the relative position between the first core 103 and the second core 104 is shifted, and the loss near the boundary between the first core 103 and the second core 104 is large. It may become. In addition, due to the manufacturing process, the first core 103 has a rectangular cross-sectional shape, whereas the second core 104 has a circular cross-sectional shape. Loss near the interface with the core 104 increases.

  Moreover, since the formation speed at the time of forming the 2nd core 104 by condensing and irradiating a laser beam in the above-mentioned 2nd glass layer is low, productivity will be low and manufacturing cost will become high. In addition, if the spot size is changed rapidly at a short distance, the radiation loss to the outside of the second core 104 increases, so that the cross-sectional area of the second core 104 gradually changes along the light propagation direction. It is necessary to increase the total length of the second core 104 as the difference in spot size between the both end faces of the second core 104 increases, which further reduces the productivity.

  Further, since the first core 103 and the second core 104 are formed by different processes, the manufacturing process becomes complicated, leading to an increase in cost due to a decrease in yield.

  The present invention has been made in view of the above reasons, and an object of the present invention is to provide a spot size converter that can be easily reduced in cost and loss and a manufacturing method thereof.

  According to the first aspect of the present invention, a substrate, a first core made of a semiconductor material formed on one surface side of the substrate, and the first core on the one surface side of the substrate are formed so as to be optically coupled to the first core. And a second core made of a semiconductor material whose cross-sectional area is continuously changed along the propagation direction, and the second core has a shape in which each of the width dimension and the thickness dimension monotonously decreases as the first core is approached. The first core and the second core are defined in width by patterning a semiconductor layer formed on the one surface side of the substrate, and both side surfaces of the first core and the second core are defined. The second core has a thickness by forming a clad such that the distance between the second core and the substrate on the opposite side of the substrate decreases monotonously as the distance from the substrate approaches the first core. The dimensions are defined.

  According to the present invention, the first core and the second core are formed by patterning a semiconductor layer formed on one surface side of the substrate using a lithography technique and an etching technique, which are general semiconductor manufacturing processes. Each width dimension can be defined, both side surfaces of the first core and both side surfaces of the second core can be smoothly continuous, and the thickness dimension of the second core can be reduced by forming a clad. Since both the first core in the thickness direction and the second core in the thickness direction can be smoothly continuous, the cost and loss can be easily reduced.

  According to a second aspect of the present invention, in the first aspect of the invention, the semiconductor material is silicon.

  According to the present invention, the width dimension and thickness dimension of each core can be defined with high accuracy by a general silicon process.

  The invention of claim 3 is the invention of claim 2, wherein the clad is formed by doping the semiconductor layer with an impurity.

  According to the present invention, the cladding can be formed within the thickness dimension of the semiconductor layer, the thickness dimension of the entire spot converter can be reduced, and the thickness dimension and refractive index of the cladding can be easily controlled. be able to.

  According to a fourth aspect of the present invention, in the second aspect of the present invention, the clad is made of a silicon oxide film.

  According to the present invention, the clad can be formed by a general oxidation process, and the refractive index difference between the second core and the clad can be made relatively large to enhance the light confinement effect. In addition, the thickness dimension of the cladding can be defined with high accuracy, and as a result, the thickness dimension of the second core can be defined with high accuracy.

  According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the clad is formed by a LOCOS method.

  According to the present invention, the clad defining the thickness dimension of the second core can be formed relatively easily by the LOCOS method used in the manufacturing process of a MOS device or the like, and the thickness dimension of the second core can be changed smoothly. Can be made.

  According to a sixth aspect of the present invention, in the first to fifth aspects of the present invention, in each of the cores, the thickness dimension of the portion of the semiconductor layer that does not correspond to the core is larger than the thickness dimension of the portion that corresponds to the core. It is formed by patterning the semiconductor layer so as to be smaller.

  According to the present invention, since the single mode state can be obtained even if the width dimension of the first core is relatively wide, the processing accuracy is relaxed and the manufacture is facilitated.

  According to a seventh aspect of the invention, in the first to sixth aspects of the invention, the first core has a thickness dimension by forming another clad made of the same material as the clad on the opposite side of the substrate. It is characterized by being defined.

  According to the present invention, the clad that defines the thickness dimension of the second core and the other clad that defines the thickness dimension of the first core can be smoothly continued.

  According to an eighth aspect of the present invention, in the first to sixth aspects of the present invention, the surface of the first core opposite to the substrate is exposed.

  According to this invention, the light confinement action in the thickness direction of the first core can be enhanced, and the loss can be further reduced.

  The invention of claim 9 is the method for manufacturing the spot size converter according to claim 3, wherein the first core and the second core are patterned by patterning a semiconductor layer formed on one surface side of the substrate. A patterning step for defining a width dimension; and a clad forming step for forming a clad by doping an impurity on a surface side of a region corresponding to the second core in the semiconductor layer after the patterning step. .

  According to this invention, the width dimension of the first core and the second core can be defined by the patterning process for patterning the semiconductor layer, and the region corresponding to the second core in the semiconductor layer after the patterning process can be defined. Since the thickness dimension of the second core can be defined by forming a clad by doping impurities on the surface side, it is possible to provide a spot size converter that facilitates cost reduction and loss reduction. .

  According to a tenth aspect of the present invention, in the ninth aspect of the invention, in the clad forming step, the semiconductor layer is subjected to a plurality of impurity ion implantation processes in which an acceleration voltage is varied according to a thickness dimension of the second core. After performing, the clad is formed by performing an annealing process.

  According to this invention, the thickness dimension of the cladding can be controlled with high accuracy, and as a result, the thickness dimension of the second core can be controlled with high accuracy.

  According to an eleventh aspect of the present invention, in the clad forming step according to the ninth aspect of the invention, the opening width is set wider as the first core is closer to the surface of the region corresponding to the second core in the semiconductor layer. After forming a mask in which a plurality of apertures are arranged in parallel, the impurity is ion-implanted into the semiconductor layer, and then the annealing is performed to form the clad.

  According to this invention, since the number of times of ion implantation necessary for forming the cladding is only one, the manufacture is facilitated and the manufacturing cost is reduced as compared with the invention of claim 10 in which the ion implantation is performed a plurality of times. be able to.

  The invention of claim 12 is characterized in that, in the invention of claim 11, in the clad formation step, an impurity having a large diffusion coefficient in the semiconductor layer is used as the impurity.

  According to the present invention, the annealing time can be shortened, and the throughput is improved.

  The invention of claim 13 is the method for manufacturing the spot size converter according to claim 4, wherein the first core and the second core are patterned by patterning a semiconductor layer formed on one surface side of the substrate. A patterning step for defining the width dimension, and after the patterning step, the semiconductor layer is subjected to a plurality of oxygen ion implantation processes with different acceleration voltages according to the thickness dimension of the second core, followed by a heat treatment. Thus, the clad is formed.

  According to this invention, the width dimension of the first core and the second core can be defined by the patterning process for patterning the semiconductor layer, and the region corresponding to the second core in the semiconductor layer after the patterning process can be defined. Since the thickness dimension of the second core can be defined by forming a clad by implanting oxygen ions on the surface side and performing heat treatment, a spot size converter that is easy to reduce cost and loss Can be provided.

  The invention of claim 14 is the method for manufacturing the spot size converter according to claim 5, wherein the first core and the second core are patterned by patterning a semiconductor layer formed on one surface side of the substrate. A patterning step for defining the width dimension and a clad forming step for forming a clad made of a silicon oxide film using the LOCOS method after the patterning step are provided.

  According to the present invention, the width dimension of the first core and the second core can be defined by the patterning process for patterning the semiconductor layer, and the cladding made of the silicon oxide film using the LOCOS method after the patterning process Since the thickness dimension of the second core can be defined by forming the spot size converter, it is possible to provide a spot size converter that can be easily reduced in cost and loss.

  According to the first to eighth aspects of the present invention, the first core is formed by patterning a semiconductor layer formed on one surface side of the substrate using a lithography technique and an etching technique, which are general semiconductor manufacturing processes. The width dimension of each of the first core and the second core can be defined, and both side surfaces of the first core and both side surfaces of the second core can be smoothly connected to each other. The thickness dimension of the core can be defined and both the first core in the thickness direction and the second core in the thickness direction can be smoothly continuous, so cost and loss can be easily reduced. The effect is that

  According to the ninth to twelfth aspects of the present invention, the width dimension of the first core and the second core can be defined by the patterning process for patterning the semiconductor layer, and the second core in the semiconductor layer after the patterning process. Since the thickness dimension of the second core can be defined by forming a clad by doping impurities on the surface side of the region corresponding to the above, a spot size converter that facilitates cost reduction and loss reduction There is an effect that it can be provided.

  In the invention of claim 13, the width dimension of the first core and the second core can be defined by the patterning step of patterning the semiconductor layer, and the region corresponding to the second core in the semiconductor layer after the patterning step Since the thickness dimension of the second core can be defined by forming a clad by implanting oxygen ions on the surface side of the metal and performing a heat treatment, a spot size converter that facilitates cost reduction and loss reduction There is an effect that can be provided.

  In the invention of claim 14, the width dimension of the first core and the second core can be defined by the patterning process for patterning the semiconductor layer, and the silicon oxide film is formed using the LOCOS method after the patterning process. Since the thickness dimension of the second core can be defined by forming the clad, there is an effect that it is possible to provide a spot size converter that can be easily reduced in cost and loss.

(Embodiment 1)
As shown in FIG. 1, the spot size converter A of this embodiment is a linear plate made of a rectangular plate-like substrate 1 and a semiconductor material (silicon in this embodiment) formed on one surface of the substrate 1. The core (hereinafter referred to as the first core) 2a and the first core 2a formed on the one surface of the substrate 1 are formed so as to be optically coupled, and the cross-sectional area is continuous along the light propagation direction. And a refractive index lower than that of the first core 2a formed on the first core 2a and the core (hereinafter referred to as the second core) 3a made of the semiconductor material (silicon in this embodiment) changed to A clad (hereinafter referred to as a first upper clad) 2b, and a clad (hereinafter referred to as a second upper clad) 3b having a lower refractive index than the second core 3a formed on the second core 3a; It has. Here, the first core 2a has a fixed width dimension and thickness dimension so as to satisfy the single mode condition, the spot sizes at both ends in the traveling direction of the propagation light are the same, and the second core 3a is formed in a shape in which the width dimension and the thickness dimension monotonously decrease as it approaches the first core 2a, and the spot sizes at both ends in the light propagation direction are different. That is, the spot size of light is different between the incident end face and the exit end face.

As shown in FIG. 2A, the spot size converter A of the present embodiment is an SOI substrate in which a silicon layer 10c is formed on a support substrate 10a made of a silicon substrate via an insulating layer 10b made of a silicon oxide film. 10, the support substrate 10 a and the insulating layer 10 b constitute the above-described substrate 1, each core 2 a, 3 a is composed of part of the silicon layer 10 c, and each upper clad 2 b, 3 b is silicon In the layer 10c, the regions where the upper claddings 2b and 3b are to be formed are formed by doping impurities (for example, phosphorus, boron, arsenic, BF _2, etc.) at a high concentration, and the first core of the insulating layer 10b is formed. The portion overlapping 2a constitutes the first lower cladding, and the portion of the insulating layer 10b overlapping the second core 3a constitutes the second lower cladding. In short, in the present embodiment, the first lower cladding, the first core 2a, and the first upper cladding 2b constitute the single-mode optical waveguide 2, and the second lower cladding, the second core 3a, and the first The optical waveguide 3 for converting the spot size is constituted by the upper clad 3b. Each core 2a, the refractive index of Si which is a material of 3a about 3.4, the refractive index of SiO ₂ which is the material of the lower cladding is about 1.5, the upper clad 2b, 3b on the Si Doping with a high concentration of impurities makes the refractive index 1 to several percent lower than the refractive index of Si (for example, when the impurity is boron or phosphorus, the impurity concentration is set to 10 ¹⁹ atoms / cm ^3. Refractive index decreases by 1%). In short, each core 2a, 3a has a higher refractive index than the upper cladding 2b, 3b and the lower cladding.

  By the way, the first core 2a and the second core 3a have a width dimension defined by patterning a silicon layer 10c, which is a semiconductor layer formed on one surface side of the substrate 1, and both side surfaces of the first core 2a. And both side surfaces of the second core 3a are smoothly continuous, and the second core 3a monotonously decreases as the distance from the substrate 1 on the side opposite to the substrate 1 approaches the first core 2a. By forming the second upper clad 3b as described above, the thickness dimension is defined.

  Therefore, in the spot size converter A of the present embodiment, the silicon layer 10c formed on the one surface side of the substrate 1 is patterned by using a lithography technique and an etching technique, which are general semiconductor manufacturing processes. Thus, the width dimension of the first core 2a and the second core 3a can be defined, and both the side surfaces of the first core 2a and the both side surfaces of the second core 3a can be smoothly continuous, By forming the second upper cladding 3b, the thickness dimension of the second core 3a can be defined, and both the thickness direction of the first core 2a and the thickness direction of the second core 3a can be smooth. Therefore, it is possible to easily reduce the cost and the loss.

  Hereinafter, the manufacturing method of the spot size converter A of the present embodiment will be described with reference to FIG.

  First, patterning is performed in order to form the optical waveguides 2 and 3 on the main surface side of the SOI substrate 10 (in order to define the width dimensions of the cores 2a and 3a and the upper claddings 2b and 3b) using the lithography technique. The resist layer 41 is formed (see FIG. 2A), and then the resist layer 41 (the resist layer 41 corresponds to the first mask portion 41a corresponding to the optical waveguide 2 and the optical waveguide 3). The silicon layer 10c is patterned by carrying out a patterning process in which the silicon layer 10c of the SOI substrate 10 is dry-etched to a depth reaching the insulating layer 10b using the mask material layer of 2 as a mask material layer (FIG. 2B). reference). In this patterning step, the silicon layer 10c is etched using the insulating layer 10b as an etching stopper layer, and by performing the patterning step, portions of the cores 2a and 3a and the upper clads 2b and 3b that will be formed later are obtained. A width dimension is defined.

  After performing the above-described patterning process, the resist layer 41 is removed (see FIG. 2C), and then a lithography technique is used on the portion of the patterned silicon layer 10c corresponding to the optical waveguide 3. Then, using the resist layer 42 as a mask material layer, impurities such as boron are ionized at a predetermined acceleration voltage and dose amount on the surface side of the portion corresponding to the optical waveguide 2 in the silicon layer 10c. Implantation is performed (see FIG. 2D), the resist layer 42 is removed, and an annealing process is performed to form the first upper clad 2b and at the same time the first core 2a is formed (see FIG. 2E). . Here, since the sum of the thickness dimension of the first core 2a and the thickness dimension of the first cladding 2b is the thickness dimension of the silicon layer 10c, the thickness dimension of the first core 2a is the same as that of the first upper cladding 2b. It is defined by the thickness dimension.

  Thereafter, a lithography process is performed to form a resist layer 43 that covers the silicon layer 10c except for the surface of a part of the region corresponding to the optical waveguide 3 and covers the surface of the first upper cladding 2b (FIG. 2 ( f)), an impurity ion implantation step of ion-implanting impurities such as boron at a predetermined acceleration voltage and dose is performed (see FIG. 2G), and a resist removal step of removing the resist layer 43 is performed (see FIG. 2G). (Refer FIG.2 (h)). A basic process including such a lithography process, an impurity ion implantation process, and a resist removal process is repeated a plurality of times (see FIG. 2I). However, when the basic process is repeated, the position of the partial region in the lithography process and the acceleration voltage in the impurity ion implantation process are changed stepwise. More specifically, in the lithography process, the position of the partial region that exposes the surface of the portion corresponding to the optical waveguide 3 is gradually separated from the first upper cladding 2b, and the acceleration voltage is increased in the impurity ion implantation process. To make it smaller.

  Subsequently, annealing is performed to diffuse the impurities, thereby forming the second upper clad 3b and simultaneously forming the second core 3a (see FIG. 2 (j)).

In short, in the manufacturing method of the present embodiment, the silicon layer 10c that is a semiconductor layer formed on one surface side of the substrate 1 is patterned to define the width dimension of the first core 2a and the second core 3a. And a clad forming step of forming a second upper clad 3b by doping impurities on the surface side of the region corresponding to the second core 3a in the silicon layer 10c after the patterning step. The impurity is not limited to boron, and for example, phosphorus, arsenic, BF ₂ or the like may be employed.

  According to the manufacturing method described above, the width dimension of the first core 2a and the second core 3a can be defined by the patterning process for patterning the silicon layer 10c, and the second dimension in the silicon layer 10c after the patterning process. Since the thickness of the second core 3a can be defined by forming the second upper cladding 3b by doping impurities on the surface side of the region corresponding to the core 3a, the cost and the loss can be reduced. It is possible to provide a spot size converter A that can be easily realized. In the cladding formation step, an ion treatment having a large diffusion coefficient in the silicon layer 10c (for example, boron or phosphorus whose diffusion coefficient in the silicon layer 10c is larger than that of arsenic) is used as the impurity. The processing time can be shortened and the throughput is improved.

  By the way, as an optical device using the spot size converter A of the present embodiment, for example, as shown in FIG. 3, an optical functional element 5 (for example, an optical filter, a multiplexer, a duplexer, a directional coupler). Type optical switch, etc.), an optical integrated functional element in which spot size converters A are arranged on both sides in the light propagation direction, and a light emitting element (for example, a laser diode, a light emitting diode, etc.) 6 and an optical function as shown in FIG. An optical integrated function module in which the spot size converter A is disposed between the element 5 and between the optical function element 5 and the light receiving element (for example, a photodiode) 7 can be realized. 3, the end surface of the optical waveguide 2 of the spot size converter A opposite to the optical waveguide 3 is optically coupled to the optical functional element 5. In the optical integrated functional module having the configuration shown in FIG. 4, the spot size converter A arranged between the light emitting element 6 and the optical functional element 5 has the optical waveguide 3 on the light emitting element 6 side and the optical waveguide 2 on the optical function. The spot size converter 5 disposed so as to be on the element 5 side and disposed between the optical functional element 5 and the light receiving element 7 has the optical waveguide 2 on the optical functional element 5 side and the optical waveguide 3 on the light receiving element 7 side. Arrange so that In such an optical integrated function module, the light emitted from the light emitting element 5 can be incident on the light receiving element 7 through the path of the spot size converter A → the optical function element 5 → the spot size converter A → the light receiving element 7. Therefore, the optical coupling efficiency between the light emitting element 6 and the light receiving element 7 can be increased. The spot size converter A includes only one set of the optical waveguide 2 and the optical waveguide 3, but may include a plurality of sets. For example, the optical functional element 5 in FIG. In the case of an optical switch, the spot size converter A only needs to include two sets of the optical waveguide 2 and the optical waveguide 3.

(Embodiment 2)
Since the structure of the spot size converter of the present embodiment is the same as that of the first embodiment and only the manufacturing method is different, only the manufacturing method will be described with reference to FIG. However, steps similar to those of the first embodiment will be briefly described.

  First, a resist layer 41 patterned to form the respective optical waveguides 2 and 3 is formed on the surface side of the SOI substrate 10 by using a lithography technique (see FIG. 5A), and then the resist layer 41 The silicon layer 10c is patterned by performing a patterning process in which the silicon layer 10c of the SOI substrate 10 is dry-etched to a depth reaching the insulating layer 10b by using as a mask (see FIG. 5B).

  After performing the above-described patterning process, the resist layer 41 is removed (see FIG. 5C), and subsequently, a lithography technique is used on the portion of the patterned silicon layer 10c corresponding to the optical waveguide 3. Then, a resist layer 51 patterned so that the opening width changes sequentially is formed (see FIG. 5D), and then an impurity such as boron is predetermined on the surface side of the silicon layer 10c using the resist layer 51 as a mask. Are ion-implanted at an acceleration voltage and dose (see FIG. 5D), and after the resist layer 51 is removed, annealing is performed to form the first upper clad 2b and the second upper clad 3b. The first core 2a and the second core 3a are formed (see FIG. 5G). Here, since the sum of the thickness dimension of the first core 2a and the thickness dimension of the first cladding 2b is the thickness dimension of the silicon layer 10c, the thickness dimension of the first core 2a is the same as that of the first upper cladding 2b. The thickness dimension of the second core 3a is determined by the thickness dimension, and the sum of the thickness dimension of the second core 3a and the thickness dimension of the second cladding 3b is the thickness dimension of the silicon layer 10c. It is defined by the thickness dimension of the cladding 3b. The resist layer 51 described above is formed on a portion of the patterned silicon layer 10c corresponding to the optical waveguide 3, and the upper surface and both side surfaces orthogonal to the longitudinal direction of the portion corresponding to the optical waveguide 2 are opened. The plurality of apertures are arranged side by side in the longitudinal direction, and the aperture width of the apertures gradually increases toward the portion corresponding to the optical waveguide 2.

  Thus, according to the manufacturing method of the present embodiment, the width dimensions of the first core 2a and the second core 3a can be defined by the patterning step of patterning the silicon layer 10c, as in the first embodiment. After the patterning step, the thickness of the second core 3a is defined by forming the second upper cladding 3b by doping impurities in the surface side of the region corresponding to the second core 3a in the silicon layer 10c. Therefore, it is possible to provide a spot size converter that can be easily reduced in cost and loss. In the manufacturing method of the present embodiment, the impurity ion implantation process can be completed only once by forming the resist layer 51 patterned as described above. Therefore, the manufacturing method described in the first embodiment is used. In comparison, the manufacturing process can be simplified, the manufacturing yield can be improved, and the cost can be reduced.

(Embodiment 3)
The basic structure of the spot size converter A of this embodiment is substantially the same as that in Embodiment 1, an upper clad 2b explained in FIG. 1 in that a 3b is formed by SiO ₂ differs.

Thus, in the spot size converter A of the present embodiment, the upper clads 2b and 3b are formed of the same SiO ₂ as the lower clad in each of the optical waveguides 2 and 3, so 2b, 3b and the lower clad can have the same refractive index (that is, the refractive index difference between each core 2a, 3a and each lower clad, each core 2a, 3a, each upper clad 2b, 3b, The refractive index difference between the cores 2a, 3a can be confined in the same manner on both surfaces in the thickness direction of each core 2a, 3a), and the mode disturbance of the propagating light can be suppressed.

  Hereinafter, the manufacturing method will be described with reference to FIG. 6, but the steps similar to those of the first embodiment will be briefly described.

  First, a resist layer 41 patterned to form the respective optical waveguides 2 and 3 is formed on the surface side of the SOI substrate 10 by using a lithography technique (see FIG. 6A), and then the resist layer 41 The silicon layer 10c is patterned by performing a patterning process in which the silicon layer 10c of the SOI substrate 10 is dry-etched to a depth reaching the insulating layer 10b by using as a mask (see FIG. 6B).

After performing the above-described patterning process, the resist layer 41 is removed (see FIG. 6C), and subsequently, a lithography technique is used on a portion of the patterned silicon layer 10c corresponding to the optical waveguide 3. Then, using the resist layer 42 as a mask material layer, oxygen ions (O ⁻ ) are ionized at a predetermined acceleration voltage and a dose amount on the surface side of the portion corresponding to the optical waveguide 2 in the silicon layer 10c. Implantation is performed (see FIG. 6D), and after the resist layer 42 is removed, heat treatment is performed to form the first upper clad 2b made of SiO ₂ and at the same time the first core 2a is formed (FIG. 6E). )reference). Here, since the sum of the thickness dimension of the first core 2a and the thickness dimension of the first cladding 2b is the thickness dimension of the silicon layer 10c, the thickness dimension of the first core 2a is the same as that of the first upper cladding 2b. It is defined by the thickness dimension.

Further, a lithography process is performed to form a resist layer 43 that covers the silicon layer 10c except for the surface of a part of the region corresponding to the optical waveguide 3 and covers the surface of the first upper cladding 2b (FIG. 6 ( f)), an oxygen ion implantation step of implanting oxygen ions (O ⁻ ) with a predetermined acceleration voltage and dose is performed (see FIG. 6G), and a resist removal step of removing the resist layer 43 is performed (see FIG. 6G). (Refer FIG.6 (h)). A basic process including such a lithography process, an oxygen ion implantation process, and a resist removal process is repeated a plurality of times (see FIG. 6I). However, when the basic process is repeated, the position of the partial region in the lithography process and the acceleration voltage in the ion implantation process are changed stepwise. More specifically, in the lithography process, the position of the partial region that exposes the surface of the portion corresponding to the optical waveguide 3 is gradually separated from the first upper clad 2, and the acceleration voltage is increased in the oxygen ion implantation process. To make it smaller.

Subsequently, heat treatment is performed to form the second clad 3b made of SiO ₂ and at the same time the second core 3a is formed (see FIG. 6 (j)).

  Thus, according to the manufacturing method of the present embodiment, the width dimension of the first core 2a and the second core 3a can be defined by the patterning process for patterning the silicon layer 10c, and the silicon layer is formed after the patterning process. In 10c, the thickness dimension of the second core 3a can be defined by forming the second upper cladding 3b by injecting oxygen ions into the surface side of the region corresponding to the second core 3a and performing heat treatment. Therefore, it is possible to provide a spot size converter that can be easily reduced in cost and loss.

(Embodiment 4)
The basic configuration of the spot size converter A of the present embodiment is substantially the same as that of the third embodiment, and the upper clads 2b and 3b shown in FIG. 7 (f) are formed using a LOCOS (Local Oxidatoin of Silicon) method. There is a feature in that.

Thus, also in the spot size converter A of the present embodiment, the upper clads 2b and 3b are formed of the same SiO ₂ as the lower clad in the respective optical waveguides 2 and 3, as in the third embodiment. The refractive indexes of the upper clad 2b and 3b and the lower clad can be set to the same value for each of the waveguides 2 and 3 (that is, the refractive index difference between the cores 2a and 3a and the lower clad and the cores 2a and 3a). And the refractive index difference between each of the upper clads 2b and 3b, and the light can be confined in the same manner on both surfaces in the thickness direction of each of the cores 2a and 3a). Can be suppressed.

  Moreover, in the spot size converter A of this embodiment, the surface on the opposite side to the board | substrate 1 in the 1st core 2a and the surface on the opposite side to the board | substrate 1 in the 2nd core 3a compared with Embodiment 3. It can be continued more smoothly.

  Hereinafter, the manufacturing method of the spot size converter A of the present embodiment will be described with reference to FIG. 7, but the steps similar to those of the third embodiment will be described briefly.

  First, a resist layer patterned to form the optical waveguides 2 and 3 is formed on the surface side of the SOI substrate 10 by using a lithography technique, and then the silicon layer 10c of the SOI substrate 10 is used with the resist layer as a mask. After performing a patterning process for dry etching to a depth reaching the insulating layer 10b, a mask layer 61 is formed on a portion of the patterned silicon layer 10c corresponding to the optical waveguide 2 (see FIG. 7A). .

Thereafter, a pad oxide film 62 made of SiO _{2 is} formed on the exposed surface of the silicon layer 10c (see FIG. 7B), and then a silicon nitride film 63 is formed on the pad oxide film 62 (see FIG. 7). 7 (c)), the above-described mask layer 61 is removed (see FIG. 7 (d)).

Next, by selectively oxidizing the portion of the silicon layer 10c that is not covered by the silicon nitride film 63, the upper claddings 2b and 3b made of SiO ₂ are formed, respectively, and at the same time, from a part of the silicon layer 10c. Each core 2a, 3a is formed (see FIG. 7E), and the silicon nitride film 63 is removed to form a spot size converter A (see FIG. 7F).

  Thus, according to the manufacturing method of the present embodiment, the width dimensions of the first core 2a and the second core 3a are defined by the patterning step of patterning the silicon layer 10c, as in the manufacturing method of the third embodiment. Since the thickness of each of the cores 2a and 3a can be defined by forming the upper clads 2bb and 3b using the LOCOS method after the patterning step, the cost and loss can be easily reduced. A spot size converter A can be provided. Moreover, the second upper cladding 3b that defines the thickness dimension of the second core 3a can be formed relatively easily by the LOCOS method used in the manufacturing process of MOS devices and the like, and the thickness dimension of the second core 3b can be changed smoothly. Can be made.

(Embodiment 5)
The basic configuration of the spot size converter A of the present embodiment is substantially the same as that of the first embodiment, and the surface of the first core 2a opposite to the substrate 1 is exposed as shown in FIG. Is different. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

  Thus, in the spot size converter A of the present embodiment, when the refractive index of the first upper clad 2b is only 1 to several percent lower than the refractive index of the first core 2a as in the first embodiment. In comparison, the light confinement effect in the thickness direction of the first core 2a can be enhanced, and the loss can be further reduced. Further, by enhancing the light confinement action in the thickness direction of the first core 2a, it is possible to cope with a design in which a sharp bent portion is provided in the first core 2a. It is possible to reduce the size.

  The manufacturing method is substantially the same as the manufacturing method described in the first embodiment, and the portion corresponding to the first upper cladding 2b in the silicon layer 10c described in the first embodiment is removed by etching or the like. do it.

(Embodiment 6)
The basic configuration of the spot size converter A of the present embodiment is substantially the same as that of the first embodiment. As shown in FIG. 9, the cores 2a and 3a are connected to the cores 2a and 3a in the silicon layer 10c as a semiconductor layer. The difference is that the silicon layer 10c is formed by patterning so that the thickness dimension of the non-corresponding part is smaller than the thickness dimension of the part corresponding to each core 2a, 3a. In short, the optical waveguides 2 and 3 of the present embodiment are so-called rib-type optical waveguides. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

  Therefore, in the spot size converter A of the present embodiment, a single mode state can be obtained even if the width dimension of the first core 2a is relatively wide, so that the processing accuracy is relaxed and the manufacture becomes easy. Here, the single mode condition of the optical waveguide 2 in the first embodiment is that the thickness and width of the first core 2a are about 0.5 μm, but in the present embodiment, the thickness is about 4 μm. In addition, when optically coupling optical fibers, the diameter of incident light from the optical fiber is about 10 μm.

  The manufacturing method of the spot size converter A of the present embodiment is substantially the same as the manufacturing method described in the first embodiment, but etching is performed so as not to reach the insulating layer 10b when the silicon layer 10c is etched in the patterning step. The difference is that the depth is set.

2 is a schematic perspective view showing a spot size converter in Embodiment 1. FIG. It is explanatory drawing of a manufacturing method same as the above. It is a schematic block diagram of the optical device provided with the spot size converter same as the above. It is a schematic block diagram of the optical device provided with the spot size converter same as the above. It is explanatory drawing of the manufacturing method of the spot size converter in Embodiment 2. FIG. It is explanatory drawing of the manufacturing method of the spot size converter in Embodiment 3. It is explanatory drawing of the manufacturing method of the spot size converter in Embodiment 4. 10 is a schematic perspective view of a spot size converter in Embodiment 5. FIG. It is a schematic perspective view of the spot size converter in Embodiment 6. A conventional example is shown, (a) is a plan view, (b) is a sectional view taken along line BB ′ of (a), (c) is a sectional view taken along line CC ′ of (a), and (d) is a sectional view of (a). It is DD 'sectional drawing.

Explanation of symbols

A Spot size converter 1 Substrate 2 Optical waveguide 2a Core (first core)
2b cladding (first upper cladding)
3 Optical waveguide 3a Core (second core)
3b cladding (second upper cladding)
10 SOI substrate 10a Support substrate 10b Insulating layer 10c Silicon layer

Claims (14)

  A substrate, a first core made of a semiconductor material formed on one surface side of the substrate, and a cross-sectional area along the light propagation direction formed so as to be optically coupled to the first core on the one surface side of the substrate Is formed in a shape in which the width dimension and the thickness dimension decrease monotonously as the first core is approached, and the first core The width of the core and the second core is defined by patterning a semiconductor layer formed on the one surface side of the substrate, and both side surfaces of the first core and both side surfaces of the second core are smooth. The thickness dimension of the second core is defined by forming a clad on the opposite side of the substrate so that the distance between the substrate and the substrate decreases monotonously as the first core is approached. Spot size converter featuring   The spot size converter according to claim 1, wherein the semiconductor material is silicon.   3. The spot size converter according to claim 2, wherein the clad is formed by doping an impurity in the semiconductor layer.   3. The spot size converter according to claim 2, wherein the clad is made of a silicon oxide film.   5. The spot size converter according to claim 4, wherein the cladding is formed by a LOCOS method.   Each of the cores is formed by patterning the semiconductor layer such that a thickness dimension of a portion not corresponding to each core in the semiconductor layer is smaller than a thickness dimension of a portion corresponding to each core. The spot size converter according to any one of claims 1 to 5, wherein   The thickness of the first core is defined by forming another clad made of the same material as that of the clad on the opposite side of the substrate. The spot size converter described in Crab.   The spot size converter according to any one of claims 1 to 6, wherein the first core has an exposed surface opposite to the substrate.   4. The method of manufacturing a spot size converter according to claim 3, wherein a patterning step of defining a width dimension of the first core and the second core by patterning a semiconductor layer formed on one surface side of the substrate. And a clad forming step of forming a clad by doping impurities on the surface side of the region corresponding to the second core in the semiconductor layer after the patterning step. .   In the clad formation step, the semiconductor layer is subjected to an impurity ion implantation process with different acceleration voltages according to the thickness dimension of the second core, and then annealed to form the clad. The method for manufacturing a spot size converter according to claim 9.   In the clad formation step, a mask is formed in which a plurality of apertures having a wider opening width are arranged in parallel with the surface of a region corresponding to the second core in the semiconductor layer as the first core is closer. 10. The method for manufacturing a spot size converter according to claim 9, wherein the cladding is formed by performing ion implantation of the impurity to the semiconductor layer and then performing an annealing process.   12. The method of manufacturing a spot size converter according to claim 11, wherein in the cladding formation step, an impurity having a large diffusion coefficient in the semiconductor layer is used as the impurity.   5. The method of manufacturing a spot size converter according to claim 4, wherein a patterning step of defining a width dimension of the first core and the second core by patterning a semiconductor layer formed on one surface side of the substrate. Then, after the patterning process, the semiconductor layer is subjected to a plurality of oxygen ion implantation processes with different acceleration voltages according to the thickness dimension of the second core, and then the heat treatment is performed to form the cladding. A method for manufacturing a spot size converter.   6. The method for manufacturing a spot size converter according to claim 5, wherein a patterning step of defining a width dimension of the first core and the second core by patterning a semiconductor layer formed on one surface side of the substrate. And a clad forming step of forming a clad made of a silicon oxide film using a LOCOS method after the patterning step.

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