JP2005064972A - Signal processor and signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent disturbance of sound field when audio reproduction is performed by a class D amplifier of multichannel system, and to reduce noise due to switching. <P>SOLUTION: The sampling rate converter 2a at each voice output section of front left channel, front right channel, surround left channel and surround right channel is asynchronous type. ΔΣ modulation/PWM sections 3a-3d provided at the poststage output PWM signals to respective switching/amplifying sections 4a-4d by performing modulation with sync signals shifted by delay circuits 8a-8c to have a different timing from each other. Since phase shift (mismatch of reproduction time axis) does not occur among digital audio signals being processed at the ΔΣ modulation/PWM sections 3a-3d and the timing of carrier period T of the PWM signals being inputted to the switching/amplifying sections 4a-4d is shifted, switching timing of the switching/amplifying sections 4a-4d is shifted and noise is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is a signal processing device provided with a plurality of signal processing systems that execute ΔΣ modulation processing and PWM modulation processing on a digital signal obtained by sampling (sampling), for example, in a multi-channel sound reproduction device. It is suitable for application.

  In recent years, so-called multi-channel audio output devices including a plurality of audio output units called 5.1 channel surround systems have become widespread for the purpose of obtaining acoustic effects full of realism.

  In the conventional audio output devices, signal amplifiers using a method called Class A amplification or Class B amplification have been used as power amplifiers. In such multi-channel audio output devices, the number of power amplifiers corresponding to the number of channels is required. Therefore, in recent years, a class D amplification (Class D amplification) signal amplifier that uses less power loss than the above class A amplifier or class B amplifier is widely known.

The block diagram of FIG. 6 shows a configuration example corresponding to a multi-channel audio signal as an audio output device including a so-called class D power amplifier using the class D amplification described above.
In FIG. 6, a description will be given by taking as an example an example of a 4-channel audio output unit including a front left channel, a front right channel, a surround left channel, and a surround right channel.

In FIG. 6, a predetermined sampling frequency is used for each of the audio output units of the front left channel (Front Lch), front right channel (Front Rch), surround left channel (Front Rch), and surround right channel (Front Rch). The audio signal (digital audio signal) converted into a digital signal by the quantization bit is input.
The four digital audio signals input to each of these sound output units are simultaneously output from the speaker units 7a to 7d of each sound output unit as described later, thereby forming one sound field. Accordingly, these four digital audio signals are actually input in a state in which the reproduction time axes are synchronized, although they are different from each other as the sound signal waveforms.

The configuration of each of these audio output units will be described by taking the front left channel (Front Lch) audio output unit as an example.
The front left channel (Front Lch) audio output unit includes a delta-sigma modulation / pulse width modulation unit (hereinafter referred to as “ΔΣ modulation / PWM unit”) 3a, a switching amplification unit 4a, and a low-pass filter as shown in the figure. (LPF) 5a, LPF 6a, and speaker unit 7a.

The digital audio signal input to the audio output unit of the front left channel (Front Lch) is first input to the ΔΣ modulation / PWM unit 3a.
The ΔΣ modulation / PWM unit 3a performs ΔΣ modulation on the input digital audio signal. The ΔΣ modulation signal obtained by this ΔΣ modulation processing is subjected to PWM modulation (pulse width modulation). Thus, as is well known, the ΔΣ modulation signal is output as a PWM signal represented by a change in the pulse width direction.

A sync signal is input to the ΔΣ modulation / PWM unit 3a. This synchronization signal is generated so as to be synchronized with the digital audio signal input as a processing target, and the ΔΣ modulation / PWM unit 3a captures the digital audio signal at a timing according to the synchronization signal and The ΔΣ modulation processing and PWM modulation processing that have been performed are executed.
Therefore, in this case, the ΔΣ modulation / PWM unit 3a operates at a timing synchronized with the input digital audio signal.

  The switching amplifier 4a is configured by a switching element such as an FET, for example, and receives a PWM signal output from the ΔΣ modulation / PWM unit 3a and performs a switching operation according to the waveform of the PWM signal to amplify the signal. To do. Thus, the amplified switching output signals SA_FL and SB_FL are output from the switching amplifier 4a. These switching output signals SA_FL and SB_FL are supplied to the speaker unit 7a via low-pass filters (LPF) 5a and LPF 6a, respectively. As a result, a driving current i_FL having a waveform corresponding to the reproduced sound flows through the speaker unit 7a, and the reproduced sound is output from the speaker unit 7a by being driven by the driving current i_FL.

Similarly, the audio output unit of the front right channel (Front Rch) includes a ΔΣ modulation / PWM unit 3b, a switching amplifier unit 4b, LPF 5b, LPF 6b, and a speaker unit 7b.
The surround left channel (Surround Lch) audio output unit also includes a ΔΣ modulation / PWM unit 3c, a switching amplification unit 4c, an LPF 5c, an LPF 6c, and a speaker unit 7c.
The sound output unit of the surround right channel (Surround Rch) also includes a ΔΣ modulation / PWM unit 3d, a switching amplification unit 4d, LPF 5d, LPF 6d, and a speaker unit 7d.
These audio output units also perform the same signal processing as the above-described front left channel audio output unit, amplify the input digital audio signal, and finally output as audio from the speaker units 7b to 7d. To do.

  Here, the ΔΣ modulation / PWM units 3b, 3c, and 3d in the front right channel, surround left channel, and surround right channel audio output units are synchronized in the same manner as the front left channel ΔΣ modulation / PWM unit 3a. A digital audio signal is captured at a timing according to the signal, and the above-described ΔΣ modulation processing and PWM modulation processing are executed.

  In FIG. 6, as can be understood from the fact that one synchronization signal is branched and inputted to each ΔΣ modulation / PWM unit 3a, 3b, 3c, 3d, the ΔΣ modulation / PWM unit 3a, 3b is also understood. , 3c and 3d execute processing on the input digital audio signal at the same timing based on the synchronization signal.

  In the following description, each of the ΔΣ modulation / PWM units 3a to 3d, the switching amplifiers 4a to 4d, the LPFs 5a to 5d, the LPFs 6a to 6d, and the speaker units 7a to 7d constituting each audio output unit will be described for convenience of explanation. When there is no need to distinguish between them, they are also simply referred to as ΔΣ modulation / PWM unit 3, switching amplification unit 4, LPF 5, LPF 6, and speaker unit 7, respectively.

FIG. 7 shows the operation of the functional circuit units after the switching amplifiers 4a to 4d provided in each audio output unit of the audio output device shown in FIG.
As described above, the PWM signals output from the ΔΣ modulation / PWM units 3a to 3d are input to the switching amplifiers 4a to 4d, and the PWM signals are switched and amplified according to the pulse waveforms. Output.

In this way, the switching output signals SA_FL and SB_FL shown in FIG. 8A are output from the switching amplifier 4a as switching output signals which are PWM signals amplified and output by the switching amplifiers 4a to 4d. Has been.
These switching output signals SA_FL and SB_FL are configured to drive the speaker unit 7a through LPFs 5a and 6a inserted in the + line and the − line of the speaker unit 7a as shown in the figure. As a result, when a level difference occurs between SA_FL and SB_FL, a drive current i_FL in which a pulse having a polarity corresponding to the relationship between the polarities of SA_FL and SB_FL appears flows to the speaker unit 7a. In practice, the waveform of the drive current i_FL corresponds to the amplified PWM signal. Actually, the rectangular-wave-shaped drive current i_FL shown in the figure flows through the speaker unit 7a as an integrated audio signal waveform through the LPFs 5a and 6a.

  Similarly, the switching output signals [SA_FR, SB_FR] [SA_SL, SB_SL] [SA_SR, SB_SR] output from the remaining switching amplifiers 4b, 4c, 4d are also shown in FIGS. 7B, 7C, and 7D. In response to this, the drive currents i_FR, i_SL, i_SR are caused to flow to the speaker units 7b, 7c, 7d, respectively.

In this case, as described above, the ΔΣ modulation / PWM units 3a to 3d perform signal processing on the digital audio signal using the same synchronization signal and output the signal to the switching amplifiers 4a to 4d. That is, the ΔΣ modulation / PWM units 3a to 3d execute signal processing at the same timing.
Accordingly, the carrier cycle timings of the respective PWM signals output from the ΔΣ modulation / PWM units 3a to 3d are also output so as to coincide with each other. Since the ΔΣ modulation / PWM units 3a to 3d execute signal processing at the same timing as described above, the reproduction time axes of the digital audio signals input to the ΔΣ modulation / PWM units 3a to 3d are synchronized. If this is the case, the playback time axis is synchronized with the sound output from the speaker units 7a to 7d via the ΔΣ modulation / PWM units 3a to 3d. In order to make the explanation easy to understand, assuming that the same digital audio signal is input to the ΔΣ modulation / PWM units 3a to 3d, the speaker unit via the ΔΣ modulation / PWM units 3a to 3d is assumed. The sound signal waveforms (reproduced signal waveforms) output from 7a to 7d have the same phase.
That is, the synchronization signal supplied to the ΔΣ modulation / PWM units 3a to 3d synchronizes the signal processing timing in each of the ΔΣ modulation / PWM units 3a to 3d when performing multi-channel reproduction. As a result, the ΔΣ modulation / PWM unit The original purpose is to prevent the sound output from 3a to 3d from shifting in the reproduction time axis.

Here, the section T in FIG. 7 corresponds to one cycle of the carrier of the PWM signal. As described above, the ΔΣ modulation / PWM units 3a to 3d output the PWM signal with the same carrier cycle timing.
Accordingly, the waveforms of the switching output signals [SA_FL, SB_FL] [SA_FR, SB_FR] [SA_SL, SB_SL] [SA_SR, SB_SR] obtained by switching the PWM signals by the switching amplifiers 4a to 4d are illustrated. Thus, the timing for each section T corresponding to the carrier period of the PWM signal matches. That is, at the timing shown as time points t1, t2, t3, and t4 in FIG. 7, switching is performed by simultaneously raising the switching output signal.

  However, in the operation as described above, a switching current flows simultaneously from the switching amplifiers 4a to 4d corresponding to each carrier period of the PWM signal. Since the switching amplifiers 4a to 4d perform power amplification by switching, the amount of rectangular-wave-like switching current flowing corresponding to each carrier period of the PWM signal is considerably large. For this reason, noise due to unnecessary radiation or interference between channels occurs in the carrier period of the PWM signal.

  In the switching amplifiers 4a to 4d, it is known that, for example, two switching elements are bridge-connected to form a switching circuit. In the case of such a switching circuit configuration, the carrier of the PWM signal When switching is performed at the start timing of the cycle, the switching elements may be simultaneously turned on and a through current may flow from the power supply line. As described above, when the carrier periods of the PWM signals coincide between the audio output units, the timing at which the through current flows for each carrier period is also the same between the switching amplifiers 4a to 4d. Become. As a result, the through current flowing from the power source may be further excessive. For example, depending on the through current, a burden is imposed on elements such as switching transistors constituting the switching amplifiers 4a to 4d, and a problem such as fluctuations in the power supply voltage occurs. Therefore, it is required to be suppressed as much as possible.

Therefore, an audio output device configured as shown in FIG. 8 has been proposed.
In the audio output device shown in FIG. 8, for the sake of easy understanding, an audio output device including an audio output unit having two channels, that is, a front left channel and a front right channel will be described as an example. Also, the same parts as those of the audio output device shown in FIG.

In the audio output device shown in FIG. 8, a delay circuit 8a for delaying the synchronization signal is provided. Thus, the synchronization signal input to the ΔΣ modulation / PWM unit 3b is delayed by the delay time set in the delay circuit 8a with respect to the synchronization signal input to the ΔΣ modulation / PWM unit 3a.
As a result, the signal processing timing between the ΔΣ modulation / PWM units 3a and 3b is shifted by the delay time of the delay circuit 8a.

  FIG. 9 schematically shows the operation timing of the ΔΣ modulation / PWM units 3a and 3b in the audio output device shown in FIG. 9A shows a digital audio signal processed by the ΔΣ modulation / PWM unit 3a (front left channel side), and FIG. 9B shows a ΔΣ modulation / PWM unit 3b (front right channel side). The digital audio signal to be processed is shown. Here, in order to make the explanation easy to understand, the digital audio signals inputted to the ΔΣ modulation / PWM units 3a and 3b are assumed to be the same.

First, in the ΔΣ modulation / PWM unit 3a, processing is performed on the digital audio signal to be processed at the timing shown in FIG. 9A based on the input of the synchronization signal that is not delayed by the delay circuit 8a. And That is, the process for the sample data at the equally spaced sample positions P1, P2,... Shown in FIG.
On the other hand, in the ΔΣ modulation / PWM unit 3b, since the input synchronization signal is delayed by the delay time Td by the delay circuit 8a, the signal processing of the sample data at the sample position P1 is performed for the same digital audio signal. The operation starts from time t2 after the delay time Td minutes from time t1.
In addition, when the processing of the sample data at the same sample position (P1, P2,...) Is delayed between the ΔΣ modulation / PWM units 3a and 3b in this way, the ΔΣ modulation / PWM unit is used as the synchronization signal. Since the signal is synchronized with the original digital audio signal input to 3a and 3b, the phase of the digital audio signal processed by the ΔΣ modulation / PWM units 3a and 3b is also shown in FIGS. As can be seen from the comparison, the time is shifted corresponding to the delay time Td.

  If the processing timing in the ΔΣ modulation / PWM units 3a, 3b is shifted by the delay time Td in this way, the timing of the carrier period of the PWM signal output from the ΔΣ modulation / PWM units 3a, 3b is also the delay time. It will be shifted by Td. Therefore, the timing for raising the switching output signal corresponding to the carrier period of the PWM signal between the switching amplifiers 4a and 4b for switching and amplifying these PWM signals is also shifted by the delay time Td. And not at the same time.

Although not shown here, for the ΔΣ modulation / PWM unit 3c of the audio output unit corresponding to the remaining surround left channel, for example, a delay time is further increased from the synchronization signal of the ΔΣ modulation / PWM unit 3b. The synchronization signal delayed by Td is input, and the ΔΣ modulation / PWM unit 3d of the audio output unit corresponding to the surround right channel is further delayed by the delay time Td from the synchronization signal of the ΔΣ modulation / PWM unit 3c. Input the sync signal.
By doing so, each of the ΔΣ modulation / PWM units 3a to 3d executes signal processing at different timings shifted by the delay time Td. As a result, the timing for starting up the switching output signals among the switching amplifiers 4a to 4d of all the audio output units is shifted without being simultaneous.

The fact that the timing for raising the switching output signal between the switching amplifiers 4a to 4d is shifted means that the noise generation timing is dispersed, thereby suppressing the level of unnecessary radiation. Further, interference between the switching amplifiers 4a to 4d (between channels) is also reduced, and noise due to this is also suppressed.
In addition, since the timing at which the through current flows is also distributed among the channels, the level of the through current that flows at one time is also suppressed.

  Note that the same technique as in FIG. 8 is also disclosed in Patent Document 1 below.

JP 2003-60443 A

However, in the audio output device as shown in FIG. 8, the delay circuit 8a delays the synchronization signal of the ΔΣ modulation / PWM unit 3b from the synchronization signal of the ΔΣ modulation / PWM unit 3a. For this reason, as can be seen from FIG. 9, the phase of the waveform (solid line) of the digital audio signal captured by the ΔΣ modulation / PWM unit 3b is greater than the waveform of the digital audio signal (solid line) captured by the ΔΣ modulation / PWM unit 3a. It is delayed by the delay time Td.
This means that, for example, when the same digital audio signal is processed between channels and output as sound, a phase shift occurs in the output audio signal. As a result, when audio is actually reproduced by multi-channel, there is a problem that the sound field is disturbed.

In view of the above problems, the present invention is configured as a signal processing apparatus as follows.
The signal processing apparatus of the present invention includes a plurality of signal processing units that input different digital signals.
Each signal processing unit is operated by at least a first clock and a second clock that are asynchronous with each other, and a digital signal sampled at a predetermined first sampling frequency is at a timing based on the first clock. Sampling frequency conversion means for executing the input and conversion processing to the second sampling frequency at a timing based on the second clock, and performing modulation processing on the digital signal output from the sampling frequency conversion means, Performs ΔΣ modulation processing at a timing based on a synchronization signal with a predetermined frequency, and further executes pulse width modulation processing on the ΔΣ modulation signal obtained by this ΔΣ modulation processing to perform pulse width modulation according to a predetermined carrier frequency. Modulation processing means for outputting as signals, and each signal processing The modulation processing unit of the unit executes modulation processing on the digital signal output from the sampling frequency conversion unit based on a synchronization signal input at a timing different from that of the synchronization signal used by the other modulation processing unit. It was decided to be configured.

  Each of a plurality of signal processing systems that input different digital signals is operated at least by a first clock and a second clock that are asynchronous with each other, and is sampled at a predetermined first sampling frequency. A sampling frequency conversion procedure for performing a process of inputting a digital signal at a timing based on the first clock and converting it to the second sampling frequency at a timing based on the second clock, and a digital signal output by the sampling frequency conversion procedure Modulation processing is executed, ΔΣ modulation processing is executed at a timing based on a synchronization signal having a predetermined frequency, and pulse width modulation processing is executed on the ΔΣ modulation signal obtained by this ΔΣ modulation processing, Pulse width modulation signal according to the carrier frequency of The modulation processing procedure in each signal processing system is performed by a sampling frequency conversion procedure based on a synchronization signal having a timing different from that of the synchronization signal used by the modulation processing in another signal processing system. The signal processing method is configured to perform modulation processing on the output digital signal.

In the above configuration, at least each of the plurality of signal processing units (signal processing systems) executes sampling frequency conversion processing, and ΔΣ modulation processing and PWM modulation processing for the signal converted by the sampling frequency conversion processing. ing.
In addition, in the sampling frequency conversion process, the digital signal input at the timing based on the first clock is converted and output at the timing according to the second clock asynchronous with the first clock. Also. The modulation processing as the ΔΣ modulation processing and the PWM modulation processing of each signal processing unit is executed at a timing based on a synchronization signal input at a different timing corresponding to each signal processing unit.

In such a configuration, it can be said that sampling frequency conversion processing that operates with an asynchronous input-side clock and output-side clock is performed on digital signals as pre-processing for executing ΔΣ modulation processing and PWM modulation processing. .
As a result, the ΔΣ modulation processing and PWM modulation processing side does not depend on the sampling frequency (input side clock) of the original digital signal before the sampling frequency conversion processing, but depends on the second clock of the sampling frequency conversion processing. The process is executed at the timing. However, the synchronization signal that determines the processing timing of the ΔΣ modulation processing and the PWM modulation processing has different timing between the signal processing units.
For example, if the same signal is input to each signal processing unit, the signal after the sampling frequency conversion process is output in the same phase, and the PWM signal after the ΔΣ modulation process and the PWM modulation process is also in the same phase. Although it is output at the timing to be reproduced, it means that the carrier period of the PWM signal is shifted between the signal processing units according to the input timing of the synchronization signal.

Therefore, according to the present invention, the carrier period of the PWM signal is shifted between a plurality of signal processing units. For example, switching according to the carrier period that occurs when these PWM signals are switched and amplified. Noise generation timing is distributed. Thereby, unnecessary radiation and interference noise between signal processing units are reduced. In addition, the timing at which the through current flows in the switching amplification stage of each signal processing unit is also distributed, so that an excessive through current does not flow, the component elements forming the switching amplification stage are protected, and the power supply voltage is stabilized. Is achieved. In addition, even if the carrier period of the PWM signal is shifted between the signal processing units, the phase of the signal to be output is not shifted.
That is, in the present invention, when ΔΣ modulation processing and PWM modulation processing are performed in a plurality of signal processing units, an effect such as noise reduction is obtained by shifting the carrier period of the PWM signal, and the output signal It is compatible with ensuring that there is no phase shift. For example, if the signal processing device of the present invention is applied to a multi-channel sound reproduction system, it is possible to obtain a noise reduction effect and a through current suppression effect, and there is no phase shift between each channel, and an appropriate sound field can be reproduced. High quality products can be obtained.

Hereinafter, embodiments of the signal processing apparatus of the present invention will be described.
FIG. 1 is a block diagram showing a configuration example when the signal processing apparatus according to the embodiment of the present invention is applied to a multi-channel audio output apparatus.
The audio output device 1 shown in FIG. 1 corresponds to the multi-channel method as described above, and corresponds to the front left channel (Front Lch), the front right channel (Front Rch), and the surround left channel (Surround Lch). , A surround right channel (Surround Rch) 4 channel audio output unit (audio signal processing unit, audio signal processing system) is provided.
The audio output apparatus 1 having such a configuration can be regarded as an audio reproduction system that supports, for example, a 5.1 channel surround system, omitting an audio signal processing system that outputs audio corresponding to so-called subwoofers and center channels. .

In FIG. 1, an audio signal (digital audio signal) converted into a digital signal with a predetermined sampling frequency and quantization bits is input to each audio output unit.
The four digital audio signals input to each of these sound output units are simultaneously output from the speaker units 7a to 7d of each sound output unit as described later, thereby forming one sound field. Accordingly, these four digital audio signals are actually input in a state in which the reproduction time axes are synchronized, although they are different from each other as the sound signal waveforms.

The configuration of each audio output unit in the audio output device 1 configured as described above will be described by taking the audio output unit of the front left channel (Front Lch) as an example.
The front left channel (Front Lch) audio output unit includes a sampling rate converter 2a, a ΔΣ modulation / PWM unit 3a, a switching amplification unit 4a, a low-pass filter (LPF) 5a, an LPF 6a, and a speaker unit 7a as shown in the figure. It is prepared for.

The digital audio signal input to the front left channel (Front Lch) audio output unit is first input to the sampling rate converter 2a.
The digital audio signal input to the sampling rate converter 2a is output from a signal source (not shown), for example. In this case, the digital audio signal input from the signal source to the sampling rate converter 2a is sampled at a sampling frequency of 8fsA (= 352.8KHz) with a sampling frequency of 44.1KHz as fsA (sample). ) Digital audio signal.

  In the sampling rate converter 2a, the input digital audio signal with the sampling frequency of 8 fsA is further oversampled by 64 times to obtain a digital audio signal sampled with a sampling frequency of 512 (= 8 × 64) fsA. Then, a process of converting the sampling frequency is executed for the digital audio signal having the sampling frequency of 512 fsA. In this case, assuming that the sampling frequency of 48 KHz is fsB, first, it is converted to a sampling frequency of 8 fsB (= 48 × 8 = 384 KHz), further doubled, and a digital audio signal with a sampling frequency of 16 fsB (= 768 KHz) To do.

  As such sampling frequency conversion, an output sampling point is determined based on a ratio of sampling frequency before conversion and after conversion, and linear interpolation is performed based on the determined sampling point.

Here, the sampling rate converter 2a executes processing based on the first clock CLK1 that is the input side clock and the second clock CLK2 that is the output side clock. The clocks CLK2 are in an asynchronous relationship with each other.
The first clock CLK1 is generated by inputting a digital audio signal to be input to each audio output unit to a PLL circuit or the like. That is, the clock is synchronized with the digital audio signal input to the audio output unit (sampling rate converters 2a to 2d). The first clock CLK1 has a frequency of, for example, 256 fsA.
In the sampling rate converter 2a, a digital audio signal is input at a timing according to the first clock CLK1, and is written and held in, for example, an internal memory.

On the other hand, the second clock CLK2 is a signal to be synchronized with the converted sampling frequency fsB, and can be generated based on, for example, an oscillation frequency signal of a crystal oscillator. The frequency of the second clock CLK2 here is, for example, 1024 fsB.
The sampling rate converter 2a reads the digital audio signal held in the memory as described above at a timing according to the second clock CLK2, and executes a sampling frequency conversion process by linear interpolation.

  In this way, the sampling rate converter 2a of the present embodiment is configured to operate with the first clock CLK1 and the second clock CLK2 that are asynchronous with each other on the input side and the output side. That is, it is configured as a so-called asynchronous sampling rate converter. The technique of the sampling rate converter having such an asynchronous type has already been filed by the present applicant, for example.

  The sampling rate converter 2a thus operates asynchronously between the input side and the output side, so that the signal processing timing of the ΔΣ modulation / PWM unit 3a provided at the subsequent stage of the sampling rate converter 2a is as in the conventional case. Thus, it is not necessary to synchronize with the original digital audio signal on the side input to the sampling rate converter 2a, and it is only necessary to synchronize with the digital audio signal after sampling frequency conversion output from the sampling rate converter 2a. Become.

The ΔΣ modulation / PWM unit 3a includes, for example, a ΔΣ modulator and a PWM (Pule Width Moduration) modulator.
The ΔΣ modulator includes an integrator, a quantizer, and the like as is well known, and is configured to negatively feed the output of the quantizer to the input of the integrator. With this configuration, the word length of the quantized bits of the input digital audio signal is shortened to a predetermined number of bits. Also, a so-called noise shaping process is performed in which the quantized noise component generated at this time is moved to a band higher than the audio band.

  In this case, the digital audio signal input from the sampling rate converter 2a has a quantization bit number of 28 bits. The ΔΣ modulator in the ΔΣ modulation / PWM unit 3a converts the 28-bit quantization bit number into 6 bits.

  Further, the PWM modulator in the ΔΣ modulation / PWM unit 3a inputs the ΔΣ modulation signal whose word length has been converted to 6 bits as the number of quantization bits as described above in units of 6 bits, and the 6 bits A PWM signal with a variable pulse width corresponding to the value corresponding to is output. In this way, the ΔΣ modulation signal is converted into a PWM signal by PWM modulation. In addition, the PWM signal obtained in this way also shows a change in pulse width according to the waveform amplitude of the digital audio signal, as is well known.

  In the present embodiment, four PWM signals S10, S11, S20, and S21 are output as PWM signals output from the ΔΣ modulation / PWM unit 3a as illustrated. The relationship between these PWM signals S10, S11, S20, S21 will be described later.

The second clock CLK2, which is the same as the clock on the output side of the sampling rate converter 2a, is input to the ΔΣ modulation / PWM unit 3a as the operation clock, and the above-described ΔΣ modulation processing and PWM modulation processing are performed on this clock CLK2. It is executed at the timing that follows.
Since the sampling frequency of the digital audio signal input to the ΔΣ modulation / PWM unit 3a is 16 fsB and the clock CLK2 is 1024 fsB, the ΔΣ modulation / PWM unit 3a has processing timing according to the clock CLK2, It will be understood that the modulation processing of the input digital audio signal can be processed at an appropriate timing. It is also understood that this modulation processing can be performed with a resolution of 64 steps as represented by 1024fsB / 16fsB = 64.

  In this case, the ΔΣ modulation / PWM unit 3a also receives a synchronization signal for synchronizing the modulation processing timing with the other audio output units, and at the timing according to the synchronization signal, the previous sampling rate The digital audio signal transferred from the converter 2a is input to perform modulation processing.

However, as described above, in the present embodiment, the sampling rate converter 2a is provided in the preceding stage of the ΔΣ modulation / PWM unit 3a, so that the ΔΣ modulation / PWM unit 3a can be replaced with the ΔΣ of another audio output unit. When synchronizing the signal processing timing with the modulation / PWM units 3b, 3c, 3d, there is no need to synchronize with the original digital audio signal supplied from the signal source side, and the digital audio output from the sampling rate converter 2a What is necessary is just to synchronize with a signal.
Therefore, as described above, the ΔΣ modulation / PWM unit 3a receives the second clock CLK2, which is the output side clock of the sampling rate converter 2a. Also, as the synchronization signal, it is appropriate that the synchronization signal is not synchronized with the original digital audio signal but is synchronized with the output side of the sampling rate converter 2a. In this case, the frequency of the synchronization signal is as follows: For example, 48KHz = 1fsB. Further, the synchronization signal in this case can be generated using, for example, CLK2.

As described above, the ΔΣ modulation / PWM unit 3a in this case outputs four PWM signals S10, S11, S20, and S21.
In the switching amplifier 4a, these PWM signals S10, S11, S20, and S21 are input as switching drive signals and a switching operation is performed to obtain an amplified output.

An example of the internal configuration of such a switching amplifier 4a is shown in FIG. 2 together with the low-pass filters 5a and 6a and the speaker unit 7a in the subsequent stage. This figure shows a case where the switching amplifier 4a is configured by a BTL (Bridge Tied Load) method.
In this case, the switching amplification unit 4a includes a switching circuit 20 formed by serially connecting the source of the switching element 11 and the drain of the switching element 12 and a source of the switching element 13 and the drain of the switching element 14 in a series bridge. And a switching circuit 21 formed by connection.
In the switching circuit 20, a positive power source is connected to the drain of the switching element 11. The source of the switching element 12 is connected to the ground (negative power source).
Also in the switching circuit 21, a positive power source is connected to the drain of the switching element 11, and the source of the switching element 12 is connected to the ground.
These switching elements 11 to 14 are, for example, N-channel type power MOS-FETs.

In the switching circuit 20, the PWM signal S 10 output from the ΔΣ modulation / PWM unit 3 a is applied to the gate of the switching element 11. The PWM signal S11 is applied to the gate of the switching element 12.
The switching elements 11 and 12 perform a switching operation in response to the application of the PWM signals S10 and S11, so that the switching output signal is output from the switching circuit 20 (the connection point between the source of the switching element 11 and the drain of the switching element 12). SA_FL is output.

In the switching circuit 21, the PWM signal S <b> 20 is applied to the gate of the switching element 13, and the PWM signal S <b> 21 is applied to the gate of the switching element 14.
The switching elements 13 and 14 perform a switching operation in response to the application of the PWM signals S20 and S21, so that the switching output signal is output from the switching circuit 20 (the connection point between the source of the switching element 11 and the drain of the switching element 12). SB_FL is output.

  The switching output signals SA_FL and SB_FL are supplied to the + line and the − line of the speaker unit 7a through the low-pass filters (LPF) 5a and 6a, respectively, so that the driving current i_FL is supplied to the speaker unit 7a. Is made to flow.

FIG. 3 is a waveform diagram showing the operation of the switching amplifier 4a having the configuration shown in FIG.
Here, the significance of the four PWM signals S10, S11, S20, and S21 output from the ΔΣ modulation / PWM unit 3a will be described.
First, the PWM signal S10 corresponds to an original PWM signal obtained by PWM modulating a ΔΣ modulation signal. The PWM signal S11 is generated by inverting the PWM signal S10.
The PWM signal S20 is generated so as to have a 2's complement relationship with respect to the PWM signal S10. The PWM signal S21 is generated by inverting the PWM signal S20.

Here, the PWM signal S10 is a signal whose pulse width is changed according to the ΔΣ modulation signal for each carrier period T of the PWM signal, and the remaining PWM based on the PWM signal S10. The signals S11, S20, and S21 also have a pulse width change corresponding to the PWM signal S10.
The carrier period T of the PWM signal S10 (and S11, S20, S21) here corresponds to the digital audio signal input to the ΔΣ modulation / PWM unit 3a having a sampling frequency of 16fsB. It corresponds to the frequency. As described above, since the number of quantization bits for each sample of the digital audio signal corresponding to one carrier period T is 6 bits, the resolution of the pulse width that is variable for each carrier period T is 64. (2 to the sixth power).

  First, in the switching circuit 20, the switching elements 11 and 12 perform a switching operation based on the PWM signals S10 and S11 applied to the respective gates. Thereby, for example, as shown in FIG. 3, the switching output signal SA_FL is output. The pulse change of the waveform of the switching output signal SA_FL is the same as that of the PWM signal S10. That is, it can be said that the switching output signal SA_FL is a signal obtained by power amplification of the PWM signal S10.

  Further, the switching elements 13 and 14 of the switching circuit 21 perform the switching operation by the PWM signals S20 and S21 applied to the respective gates, thereby outputting the switching output signal SB_FL shown in FIG. The pulse change of the waveform of the switching output signal SB_FL is the same as that of the PWM signal S20. Therefore, the switching output signal SB_FL is a signal obtained by power amplification of the PWM signal S20.

In this way, switching output signals SA_FL and SB_FL are output from the switching circuits 20 and 21 as amplified outputs. The switching output signal SA_FL is obtained as a current flowing through the + line of the speaker unit 7a, and the switching output signal SB_FL is obtained as a current flowing through the − line of the speaker unit 7a.
Then, as can be seen from the relationship between the waveforms of the switching output signals SB_FL and SB_FL and the waveform of the drive current i_FL in FIG. 3, when a level difference in an inversion relationship occurs between the switching output signals SA_FL and SB_FL, A drive current i_FL having a polarity according to the level difference is obtained and flows to the speaker unit 7a.
Actually, the drive current i_FL flowing through the speaker unit 7a is converted into an audio signal waveform by integrating the waveforms shown in FIG. 3 by the LPFs 5a and 6a. When the drive current i_FL having such a sound signal waveform flows, sound is output from the speaker unit 7a. The LPFs 5a and 6a are formed by LC, for example.

In the switching amplification unit 4a having such a configuration, the waveform of the drive current i_FL always expands and contracts in the front-rear direction with respect to the intermediate point in the period as the carrier period T of the PWM signal. In this way, the pulse width is changed.
By driving with such a drive current i_FL, distortion components and the like generated by the shift of the center position of the drive current waveform in the carrier period T can be removed, so that higher quality reproduced sound is output. Is possible.
Note that the configuration of the switching amplification unit described above is merely an example, and of course, a configuration using, for example, a single-ended pulse width amplifier or the like is also possible.

The description so far has been of the configuration of the audio output unit of the front left channel, but each remaining audio output unit is also provided with a similar functional circuit unit.
That is, in FIG. 1, the audio output unit of the front right channel is configured by a sampling rate converter 2b, a ΔΣ modulation / PWM unit 3b, a switching amplification unit 4b, LPF 5b, LPF 6b, and a speaker unit 7b.
Then, switching output signals SA_FR and SB_FR are output from the switching amplifier 4b, and the drive current i_FR flows through the speaker 7b.

The audio output section of the surround left channel includes a sampling rate converter 2c, a ΔΣ modulation / PWM section 3c, a switching amplification section 4c, LPF 5c, LPF 6c, and a speaker section 7c.
Then, switching output signals SA_SL and SB_SL are output from the switching amplifier 4c, and the drive current i_SL flows through the speaker 7c.

Similarly, the sound output unit of the surround right channel includes a sampling rate converter 2d, a ΔΣ modulation / PWM unit 3d, a switching amplification unit 4d, LPF 5d, LPF 6d, and a speaker unit 7d.
Then, switching output signals SA_SL and SB_SL are output from the switching amplifier 4c, and the drive current i_SL flows through the speaker 7c.

As shown in FIG. 1, in the present embodiment, the synchronization signal for synchronizing the signal processing timing of the ΔΣ modulation / PWM unit 3 of each audio output unit is expressed as follows. -It inputs with respect to PWM part 3a-3d.
First, the synchronization signal is input to the ΔΣ modulation / PWM unit 3a as it is. A synchronization signal via the delay circuit 8a is input to the ΔΣ modulation / PWM unit 3b. The ΔΣ modulation / PWM unit 3c receives a synchronization signal via the delay circuit 8a → 8b. The ΔΣ modulation / PWM unit 3d receives a synchronization signal via the delay circuits 8a → 8b → 8c.

Here, it is assumed that the same delay time Td is set in each of the delay circuits 8a, 8b, and 8c. As a result, synchronization signals are sequentially input to the ΔΣ modulation / PWM units 3a, 3b, 3c, and 3d at a timing delayed by the delay time Td.
Note that the delay circuits 8a, 8b, and 8c are configured to receive the second clock CLK2 having a frequency of 1024 fsB and set the delay time Td using the second clock CLK2. Alternatively, for example, a CR time constant circuit may be used.

The operation of the ΔΣ modulation / PWM unit 3 in each audio output unit when the synchronization signal delayed by the delay time Td is input will be described with reference to FIG. In this figure, only the front left channel ΔΣ modulation / PWM unit 3a and the front right channel ΔΣ modulation / PWM unit 3b are shown for the sake of simplicity.
4A and 4B schematically show digital audio signals output from the sampling rate converters 2a and 2b as audio signal waveforms. Here, in order to make the explanation easy to understand, the digital audio signals processed by the sampling rate converters 2a and 2b are assumed to be the same.
As can be understood from the above description, if the digital audio signals input to the sampling rate converters 2a and 2b are the same (reproduction time axes match), the sampling rate converters 2a and 2b have the same processing timing. Since the sampling frequency conversion is performed at, the phase of the output digital audio signal matches. This is indicated by the phase of the signal waveforms shown in FIGS. 4 (a) and 4 (b) being the same.

When the digital audio signals transferred from the sampling rate converters 2a and 2b in this way are captured by the ΔΣ modulation / PWM units 3a and 3b and subjected to modulation processing, the synchronization signal is followed as described above. The delay circuit 8a delays the synchronization signal of the ΔΣ modulation / PWM unit 3b by the delay time Td with respect to the synchronization signal of the ΔΣ modulation / PWM unit 3a.
For this reason, as shown in FIG. 4A, in the ΔΣ modulation / PWM unit 3a, at the time point t1, from the sample position P1, the timing of sample positions P2 and P3 obtained at a constant time interval according to the sampling period. The modulation process is executed.
On the other hand, in the ΔΣ modulation / PWM unit 3b, from the time point t2 when the delay time Td has elapsed from the time point t1, like the sample positions P1, P2, P3. The modulation process is executed at this timing.
In this way, in the ΔΣ modulation / PWM units 3a and 3b, the data processing for each sampling period is shifted by the delay time Td. However, the audio signal waveform of the digital audio signal to be processed is in a state where the same phase is maintained.

As will be understood from the description with reference to FIG. 4, in the ΔΣ modulation / PWM unit 3c, the data processing timing for each sampling period is shifted by the delay time Td with respect to the ΔΣ modulation / PWM unit 3b. It will be. Further, in the ΔΣ modulation / PWM unit 3d, the data processing timing for each sampling period is shifted by the delay time Td with respect to the ΔΣ modulation / PWM unit 3c.
That is, in the ΔΣ modulation / PWM units 3a to 3d, the data processing timing for each sampling period is sequentially shifted according to the delay time Td. However, the phases of these four digital audio signals processed in the ΔΣ modulation / PWM units 3a to 3d are the same.

With this operation, the switching amplifiers 4a, 4b, 4c, and 4d that operate by inputting the PWM signals (S10, S11, S20, and S21) output from the ΔΣ modulation / PWM units 3a to 3d are as follows. As shown in the waveform diagram of FIG.
FIGS. 5A, 5B, 5C, and 5D show the switching timings of the switching amplifiers 4a, 4b, 4c, and 4d, respectively.

As shown in this figure, assuming that the switching operation at the timing according to the carrier period T of the PWM signal in the switching amplifier 4a is started from the time point t1, the carrier period of the PWM signal in the switching amplifier 4b. The switching operation at a timing according to T is started from time t2 delayed by delay time Td from time t1.
Similarly, the switching operation at the timing according to the carrier period T of the PWM signal in the switching amplifier 4c is further started from a time point t3 delayed by a delay time Td from the time point t2. The switching operation at a timing corresponding to the carrier period T of the PWM signal in the switching amplifier 4d is started from a time point t4 delayed by a delay time Td from the time point t3.
That is, the switching operation of the PWM signal in the carrier period T in the switching amplifiers 4a, 4b, 4c, and 4d is sequentially distributed so as to be delayed by the delay time Td.
This is because the ΔΣ modulation / PWM units 3a to 3d execute modulation processing on the input digital audio signal based on the synchronization signals input at the mutually shifted timings, and output them as PWM signals. It depends.

  However, as described above with reference to FIG. 4, the phases of the digital audio signals processed by the ΔΣ modulation / PWM units 3 a to 3 d of the respective audio output units are the same (reproduction time axes match). Thus, the playback time axes are actually made to coincide with the sound output from the speaker units 7a to 7d of each sound output unit.

In this way, in the present embodiment, for example, noise is suppressed by distributing the switching timings in the switching amplification units of the respective audio output units. Further, even when a through current flows through the switching amplifiers 4a to 4b, the flow timing does not coincide between the switching amplifiers, so that the amount of through current flowing at a time can be suppressed.
In addition, the sound output from the speaker unit 7a of each audio output unit is set so that there is no deviation in the reproduction time axis (phase), which may disturb the sound field reproduced as a multi-channel. The quality of sound reproduction is improved, such as not to be.

In the present embodiment, the three delay circuits 8a to 8c are provided. However, if the configuration is such that a synchronization signal can be output from one delay circuit at different timings, the configuration is made up of one delay circuit. Is also possible.
Further, as the delay time Td set in the delay circuits 8a to 8c, for example, a time difference between the ΔΣ modulation / PWM modulation unit 3a that is the earliest processing timing and the ΔΣ modulation / PWM modulation unit 3d that is the latest processing timing, It is preferable that the PWM signal is within the carrier period T (digital audio signal sampling period), but may be set arbitrarily as long as a satisfactory operation can be obtained. In that case, for example, the time length (delay time) of each period from the time point t1 to the time point 2, the time point t2 to the time point t3, and the time point t3 to the time point t4 in FIG. 5 is not necessarily the same.

  The configuration of the audio output device of the present embodiment described so far is merely an example, and the present invention is applicable to all audio output devices provided with at least two or more audio output units. Furthermore, even when applied to a signal processing apparatus other than the audio output apparatus that is required to output while maintaining the coincidence of the reproduction time axes of a plurality of input signals, noise reduction and through current This is useful because inconvenience due to the increase can be avoided.

It is the block diagram which showed the structure of the audio | voice output apparatus as embodiment of this invention. It is the figure which showed the circuit structure of the switching amplifier. It is a wave form diagram which shows operation | movement of a switching amplifier. It is a figure for demonstrating the signal processing timing of the delta-sigma modulation and PWM part of embodiment. It is a wave form diagram which shows operation | movement of each switching amplification part in the audio | voice output apparatus of embodiment. It is the block diagram which showed the structure of the conventional audio | voice output apparatus. It is a figure which shows operation | movement of each switching amplification part in the audio | voice output apparatus shown in FIG. It is the block diagram which showed the other structure of the conventional audio | voice output apparatus. FIG. 9 is a diagram for explaining signal processing timing of a ΔΣ modulation / PWM unit of the audio output device shown in FIG. 8.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Audio | voice output apparatus, 2a-2d Sampling rate converter, 3a-3d delta-sigma modulation | alteration PWM part, 4a-4d switching amplification part, 5a 6a Low pass filter, 7a-7d Speaker part, 8a-8c Delay circuit, 11-14 Switching element

Claims (4)

A plurality of signal processing units for inputting different digital signals,
Each of the signal processing units is at least
The first clock and the second clock that are asynchronous with each other are operated, and a digital signal sampled at a predetermined first sampling frequency is input at a timing based on the first clock to obtain a second sampling frequency. Sampling frequency conversion means for executing the conversion process at a timing based on the second clock;
Modulation processing is performed on the digital signal output from the sampling frequency conversion means, ΔΣ modulation processing is performed at a timing based on a synchronization signal with a predetermined frequency, and ΔΣ modulation obtained by the ΔΣ modulation processing is performed. Modulation processing means for performing pulse width modulation processing on a signal and outputting as a pulse width modulation signal according to a predetermined carrier frequency, and
The modulation processing means of each signal processing unit is configured to perform modulation processing on the digital signal output from the sampling frequency conversion means based on a synchronization signal input at a timing different from the synchronization signal used by the other modulation processing means. Configured to run the
A signal processing apparatus.   The signal processing apparatus according to claim 1, wherein the first sampling frequency and the second sampling frequency are different from each other. In each of a plurality of signal processing systems for inputting different digital signals, at least,
The first clock and the second clock that are asynchronous with each other are operated, and a digital signal sampled at a predetermined first sampling frequency is input at a timing based on the first clock to obtain a second sampling frequency. A sampling frequency conversion procedure for performing the conversion process at a timing based on the second clock;
Modulation processing is performed on the digital signal output by the sampling frequency conversion procedure. ΔΣ modulation processing is executed at a timing based on a synchronization signal having a predetermined frequency, and ΔΣ modulation obtained by the ΔΣ modulation processing is executed. A pulse width modulation process is performed on the signal, and a modulation process procedure for outputting the pulse width modulation signal according to a predetermined carrier frequency is executed.
The modulation processing procedure in each signal processing system is based on the synchronization signal input at a timing different from the synchronization signal used by the modulation processing in the other signal processing system, and the digital signal output by the sampling frequency conversion procedure. To perform the modulation process of
And a signal processing method. The signal processing apparatus according to claim 3, wherein the first sampling frequency and the second sampling frequency are different from each other.

Images