JP2005064405A - Silicon wafer and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon wafer which includes a high-quality DZ layer formed near the surface of the wafer and has an oxygen deposit of sufficient density formed in a bulk, hence having a high gettering capability, and which suppresses the generation of heat during the operation of a device and can efficiently diffuse generated heat. <P>SOLUTION: In the method of manufacturing the silicon wafer using a silicon polycrystalline material which contains isotope<SP>28</SP>Si by 92.3% or above, a silicon single crystal rod having a resistivity of 100Ω cm or above and an initial interstitial oxygen density of 8-25 ppma is grown at least by the Czochralski pulled method. The silicon single crystal rod is then sliced into wafers, and these wafers are heat-treated to make a residual interstitial oxygen density 8 ppma or less. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a silicon wafer for manufacturing semiconductor devices and a silicon wafer. More specifically, the present invention relates to a high resistivity, a low defect density near the wafer surface, a high gettering capability, and a high thermal conductivity. The present invention relates to a silicon wafer manufacturing method and a silicon wafer.

  Conventionally, there are a Czochralski method (CZ method) and a floating zone (FZ method) as a method for producing a silicon single crystal for producing a silicon wafer for semiconductor production. Conventionally, high resistivity silicon wafers manufactured by the FZ method have been used for manufacturing power devices such as high voltage power devices and thyristors. However, it is difficult to produce a large-diameter silicon wafer having a diameter of 200 mm or more by the FZ method, and the in-plane resistivity distribution of a normal FZ wafer is inferior to that of a CZ wafer. For this reason, a silicon wafer by the CZ method is promising in the future, which can produce a wafer excellent in in-plane resistivity distribution and can sufficiently produce a large-diameter wafer having a diameter of 200 mm or more.

  In recent years, it is necessary to reduce parasitic capacitance in semiconductor devices for mobile communication and the most advanced C-MOS devices. For this reason, a silicon wafer having a large diameter and a high resistivity is required. In addition, the effect of using a high resistivity substrate has been reported to reduce signal transmission loss and parasitic capacitance in a Schottky barrier diode. Furthermore, in order to make the semiconductor device have higher performance, a so-called SOI (Silicon On Insulator) wafer may be used. Even when a semiconductor device is manufactured using an SOI wafer, the above-described large diameter of the wafer is used. In order to solve the problems such as the increase in the signal transmission loss and the signal transmission loss, it is required to use a high resistivity wafer by the CZ method as a base wafer.

  However, in the CZ method, since a quartz crucible is used to accommodate a silicon raw material melt, oxygen (interstitial oxygen) melted from the crucible is mixed in the silicon crystal to be grown. Such oxygen atoms are normally electrically neutral by themselves, but when subjected to a low temperature heat treatment of about 350 to 500 ° C., a plurality of oxygen atoms gather to emit electrons and electrically active oxygen. Become a donor. Therefore, when the high resistivity wafer obtained by the CZ method is subjected to a heat treatment of about 350 to 500 ° C. in a semiconductor device manufacturing process or the like, the resistivity of the high resistivity CZ wafer is reduced due to the formation of this oxygen donor. There is a problem.

  In order to prevent a decrease in resistivity due to oxygen donors as described above and to obtain a silicon wafer with a high resistivity, a silicon single crystal having a low interstitial oxygen concentration is manufactured from the beginning of crystal growth by a magnetic field application CZ method (MCZ method). Have been proposed (see, for example, Patent Document 1 and Patent Document 2). Further, by reversely utilizing the phenomenon of forming an oxygen donor, a low impurity concentration and low oxygen concentration P-type silicon wafer is subjected to a heat treatment at 400 to 500 ° C. to generate an oxygen donor. There has also been proposed a method for producing a high resistivity N-type silicon wafer by canceling P-type impurities in the silicon wafer to be N-type (see, for example, Patent Document 3).

  However, when a silicon single crystal having a low interstitial oxygen concentration is manufactured by the MCZ method or the like as described above, the density of internal defects generated by heat treatment in the device manufacturing process is low, and a sufficient gettering effect is difficult to obtain There are drawbacks. In a highly integrated device, it is essential to provide a gettering effect by a certain amount of oxygen precipitation.

  Further, the method of generating an oxygen donor by heat treatment and canceling P-type impurities in the wafer to be N-type is a complicated method that requires long-time heat treatment, and a P-type silicon wafer cannot be obtained. In addition, there is a drawback that the resistivity varies depending on the subsequent heat treatment. Further, since the wafer resistivity is difficult to control when the interstitial oxygen concentration is increased by this method, the initial interstitial oxygen concentration of the silicon wafer is low. In other words, the gettering effect of the wafer becomes low.

  In order to solve such problems, a positive so-called DZ-IG treatment in which nitrogen is doped to a high resistivity wafer is applied, and a high-quality surface-free layer without oxygen precipitates (Denuded Zone layer: DZ layer) ), A bulk oxygen precipitate layer, and a transition region having a steep profile between the DZ layer and the oxygen precipitate layer, suppressing changes in resistivity due to oxygen donors, Discloses a method for manufacturing a wafer having excellent gettering ability by internal gettering (IG) (see, for example, Patent Document 4). According to this method, a wafer having a performance equivalent to that of an SOI wafer can be realized by a bulk wafer whose manufacturing cost is lower than that of an SOI wafer. In this method, the size of a grown-in defect such as COP (Crystal Originated Particle) can also be made extremely small by nitrogen doping.

Incidentally, for the suppression of oxygen donors, a stable which is an isotope ^{28 Si,} 29 ^Si, 30 Si composition ratio of the silicon, ²⁸ Si where a composition ratio in the natural silicon ^92.23%, 29 Si Of 4.67% and ³⁰ Si from 3.10%, it is possible to control the generation of oxygen donors and the generation of oxygen precipitates that are thought to be caused by the formation of silicon isotope clusters as nuclei. (See, for example, Patent Document 5).

  On the other hand, in recent years, heat generation of the element itself due to rapid high integration, high speed operation and high power in the silicon integrated circuit element has become a problem. Since heat generation in an integrated circuit causes a reduction in device speed due to a decrease in carrier mobility or causes malfunction or destruction, countermeasures against heat generation are an important issue, and a solution to that is required. The same applies to the above power device using a silicon substrate.

In order to solve the problem of heat generation, a technique is disclosed in which the thermal conductivity of silicon is improved by increasing the content of isotope ²⁸ Si to 98% higher than that of natural silicon, and heat dissipation is improved (for example, (See Patent Document 6). Si having an increased content of one kind of isotope can be produced by a gas diffusion method, a centrifugal separation method, a laser separation method, or the like (see, for example, Patent Document 7).

Japanese Patent Publication No. 8-10695 Japanese Patent Laid-Open No. 5-58788 Japanese Patent Publication No. 8-10695 JP 2002-1000063 A Japanese Patent No. 2701809 US Pat. No. 5,144,409 JP 2001-199792 A

  In the present invention, a high-quality DZ layer is formed in the vicinity of the wafer surface, and oxygen precipitates having a sufficient density are formed in the bulk. A high-quality, high-resistivity DZ-IG wafer that can be used as a substitute for an SOI wafer that does not exist in the past is provided. The purpose is to provide.

In order to achieve the above object, the present invention provides a method for producing a silicon wafer, comprising at least a silicon polycrystalline material having a content of isotope ²⁸ Si of 92.3% or more by a Czochralski method. A silicon single crystal rod having a rate of 100 Ω · cm or more and an initial interstitial oxygen concentration of 8 to 25 ppma is grown, the silicon single crystal rod is sliced and processed into a wafer, and the wafer is heat-treated. A residual silicon interstitial oxygen concentration of 8 ppma or less is provided (claim 1).

In this way, a silicon single crystal rod having a resistivity of 100 Ω · cm or more and an initial interstitial oxygen concentration of 8 to 25 ppma is grown using a silicon polycrystalline material having a content of isotope ²⁸ Si of 92.3% or more. If the residual interstitial oxygen concentration is set to 8 ppma or less by slicing and processing this into a wafer, a silicon wafer having sufficiently high heat conduction and carrier mobility and high heat dissipation can be obtained. By precipitating interstitial oxygen so that the residual interstitial oxygen concentration is a low oxygen concentration of 8 ppma or less, the decrease in resistivity due to the generation of oxygen donors is suppressed, and oxygen precipitation is caused by outdiffusion of interstitial oxygen near the wafer surface. As a result, a DZ layer with reduced defects near the surface is formed, and oxygen precipitates are sufficiently present in the oxygen precipitate layer. Allowing high high resistivity manufacture of silicon wafers.
In order to further increase the thermal conductivity and carrier mobility, the ²⁸ Si content is more preferably 94% or more, and even more preferably 98% or more.

At this time, it is preferable to dope nitrogen when growing the silicon single crystal rod.
Thus, if nitrogen is doped, the generation of oxygen precipitates in the oxygen precipitate layer is promoted, and a silicon wafer having a higher gettering capability and a very small size of grown-in defects such as COP in the vicinity of the surface. Can be manufactured.

In this case, it is preferable that the nitrogen concentration to be doped is 1 × 10 ^{13 to} 5 × 10 ¹⁵ atoms / cm ³ (Claim 3).
Thus, if the nitrogen concentration is 1 × 10 ¹³ atoms / cm ³ or more, the effect of oxygen precipitation by doping nitrogen is clear, and if it is 5 × 10 ¹⁵ atoms / cm ³ or less, the crystal is pulled. There is no hindrance to single crystallization at the time, nor does it cause destabilization of continuous operation. More preferably, the nitrogen concentration is less than 1 × 10 ¹⁴ atoms / cm ³ . This is because when the nitrogen concentration is 1 × 10 ¹⁴ atoms / cm ³ or more, oxygen-nitrogen donors formed by heat treatment at about 600 ° C. increase, and the resistivity may be lowered. That is, it is known that the nitrogen contributing to the formation of the oxygen-nitrogen donor is about 10% of the doped nitrogen, and with a doping amount of 1 × 10 ¹⁴ atoms / cm ³ , 1 × 10 ¹³ atoms / cm 3. ^Three oxygen-nitrogen donors can be formed. If all of the donors are activated, the resistivity varies about several hundred Ω · cm. Conversely, if the amount of donors generated is less than this, it can be said that there is almost no influence.

Further, as the heat treatment, heat treatment is preferably performed at a temperature of 1000 to 1200 ° C. for 1 to 20 hours in an atmosphere of hydrogen gas, an inert gas, or a mixed gas of hydrogen gas and an inert gas. .
Thus, by setting the heat treatment atmosphere to an inert gas such as hydrogen gas or argon, or a mixed gas atmosphere thereof, the wafer surface and the COP in the vicinity thereof are effectively eliminated, and at the same time, oxygen precipitates in the bulk Can grow. In this case, if the heat treatment temperature is lower than 1000 ° C., a long heat treatment exceeding 20 hours is required to sufficiently eliminate COP. In addition, if the heat treatment is 1200 ° C., COP can be sufficiently eliminated by heat treatment for about 1 hour, but if the temperature exceeds 1200 ° C., the oxygen precipitation nuclei formed during crystal growth are likely to be dissolved again. It becomes difficult to obtain a sufficient oxygen precipitate density after the heat treatment. Therefore, the heat treatment temperature is preferably set to 1000 to 1200 ° C.

The diameter of the silicon wafer is preferably 200 mm or more.
Thus, if the diameter of the silicon wafer is 200 mm or more, the thermal conductivity is high, so the heat dissipation efficiency is high, and the carrier mobility is high, so that the high resistance DZ suitable for manufacturing a device with a high response speed in a high yield. -IG wafers can be manufactured, and 200 mm and 300 mm large-diameter silicon wafers, in particular, whose demand has been increasing in recent years can be manufactured.

The present invention also provides a silicon wafer produced by the above method (claim 6).
As described above, the silicon wafer manufactured by the above method has a high resistivity of 100 Ω · cm or more and an interstitial oxygen concentration of 8 ppm or less, so that resistance due to oxygen donor formation in the device manufacturing process is low. Therefore, a high-quality, high-resistance DZ-IG wafer is obtained in which the thermal conductivity and carrier mobility are sufficiently high and there are very few grown-in defects such as COP in the DZ layer on the wafer surface layer.

Further, the present invention is a silicon wafer having a resistivity of 100 Ω · cm or more grown by the Czochralski method, having an interstitial oxygen concentration of 8 ppma or less and an internal defect density of 1 × 10 ⁸ to 2 × 10 ^10. / Cm ³ , and the content of the isotope ²⁸ Si is 92.3% or more. A silicon wafer is provided (claim 7).

In this way, it has a high resistivity of 100 Ω · cm or more, which has been required in recent years, the interstitial oxygen concentration is as low as 8 ppm or less, and the generation of oxygen donors is suppressed, and there are sufficient oxygen precipitates and internal defect density. Is a sufficient density of 1 × 10 ^{8 to} 2 × 10 ¹⁰ pieces / cm ³ , so that the gettering ability is high and the content of the isotope ²⁸ Si is 92.3% or more. The related defects near the surface can be reduced, and a silicon wafer with sufficiently high thermal conductivity and carrier mobility can be obtained.

At this time, the silicon wafer is preferably doped with nitrogen.
As described above, in the case of a silicon wafer doped with nitrogen, the generation of oxygen precipitates in the bulk portion is promoted, silicon having higher gettering capability and extremely small size of grown-in defects such as COP. Become a wafer.

In this case, it is preferable that the concentration of the doped nitrogen is 1 × 10 ^{13 to} 5 × 10 ¹⁵ atoms / cm ³ .
Thus, if the nitrogen concentration is 1 × 10 ¹³ atoms / cm ³ or more, the effect of oxygen precipitation by nitrogen doping is high, and if it is 5 × 10 ¹⁵ atoms / cm ³ or less, a single crystal is excellent. It is a silicon wafer with high manufacturing efficiency. More preferably, the nitrogen concentration is less than 1 × 10 ¹⁴ atoms / cm ³ . Oxygen nitrogen concentration is formed by the 1 × ¹⁰ 14 atoms / cm ³ or more when it comes to about 600 ° C. heat treatment - nitrogen donors is increased, but the resistivity may deteriorate, the nitrogen concentration is 1 × ¹⁰ 14 atoms / If it is less than cm ^3, it can be said that there is almost no influence.

The COP density having a diameter of 0.12 μm or more on the surface of the silicon wafer is preferably 0.05 / cm ² or less (claim 10).
As described above, if the silicon wafer has a defect density on the surface of the silicon wafer, particularly a COP density having a diameter of 0.12 μm or more of 0.05 pieces / cm ² or less, high-quality silicon having a very low COP density. The wafer is a silicon wafer suitable for the production of a semiconductor device having low defects and high thermal conductivity.

The silicon wafer preferably has a diameter of 200 mm or more.
As described above, when the diameter of the silicon wafer is 200 mm or more, it becomes possible to produce a device with high heat dissipation efficiency and a high response speed with a high yield. Particularly, the 200 mm and 300 mm large-diameter silicon wafers that have been increasing in demand in recent years. Is preferable.

According to the present invention, a silicon single crystal rod having a resistivity of 100 Ω · cm or more and an initial interstitial oxygen concentration of 8 to 25 ppma is grown using a silicon polycrystalline raw material having a content of isotope ²⁸ Si of 92.3% or more. If the residual interstitial oxygen concentration was reduced to 8 ppma or less by slicing and processing this into a wafer, not only oxygen precipitates but also defects such as COP were greatly reduced near the wafer surface. A high-quality DZ layer is formed, oxygen precipitates of sufficient density are formed in the bulk to obtain a high gettering ability, heat generation is suppressed during device operation, and the generated heat is also diffused It is possible to produce a high-resistance silicon wafer that can be efficiently performed and that the generation of oxygen donors is suppressed and the resistivity variation is small. Alternative will achieve high-quality high resistivity DZ-IG wafer of SOI wafer Tsu is possible to provide a.

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited thereto.
The inventors performed angle polishing on a high resistivity DZ-IG wafer in which the resistivity is lowered by a heat treatment at about 350 ° C. to 500 ° C. in the device manufacturing process, and then performs selective etching to obtain a depth. The result of observing the distribution of oxygen precipitates (etch pits) in the direction is schematically shown in FIG.

  From FIG. 1, about 20 μm from the surface is a DZ layer, a deep region of about 30 μm or more from the surface is an oxygen precipitate layer, and a region about 20 to 30 μm deep from the surface in between is a transition region ( It can be seen that the region is not a complete DZ layer and has a slight amount of oxygen precipitates). The vicinity of this transition region coincides with the region where the resistivity is extremely lowered by the heat treatment in the device manufacturing process. Later, when the interstitial oxygen concentration in this part was confirmed by infrared absorption, It was found that the oxygen concentration exceeded 8 ppma.

  From these results, in order to reliably obtain a “high resistivity DZ-IG wafer” that can achieve the same level of performance as a bulk wafer with an SOI wafer for mobile communications using a high resistivity wafer as a base wafer. If not only the DZ layer and the oxygen precipitate layer but also the interstitial oxygen concentration in the transition region between them is 8 ppma or less, or the transition region width can be made as steep as possible, the entire transition region Since the amount of interstitial oxygen is less, the effect of oxygen donor formation can be reduced. In addition, in order to obtain a higher quality DZ-IG wafer, it was considered necessary to reduce the COP in the DZ layer.

  In this case, as described above, a high resistance wafer is subjected to nitrogen doping and DZ-IG heat treatment to have a DZ layer having no crystal defects near the surface and an oxygen precipitate layer in which oxygen precipitates are sufficiently deposited. Although it has been disclosed that a high-resistivity DZ-IG wafer can be obtained, in order to meet the recent demand for higher-resistance and high-quality DZ-IG wafers, generation of oxygen donors, COP, etc. It was necessary to suppress crystal defects.

  In addition, heat generation of the element itself due to rapid high integration, high speed operation and high power in the silicon integrated circuit element manufactured using such a high resistance and high quality silicon wafer has become a problem. A solution was sought.

The present inventors have grown a silicon single crystal rod having a resistivity of 100 Ω · cm or more and an initial interstitial oxygen concentration of 8 to 25 ppma, sliced this, processed into a wafer, and subjected to heat treatment, thereby performing residual interstitials. If a silicon wafer is produced using an oxygen concentration of 8 ppma or less and a silicon polycrystal raw material having an isotope ²⁸ Si content of 92.3% or more, generation of oxygen donors and crystal defects in the DZ layer are suppressed. In addition, the present inventors have found that the thermal conductivity and carrier mobility can be increased, the heat dissipation effect and the operation speed can be increased, and the present invention has been completed.

Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto.
First, it has a desired resistivity of 100 Ω · cm or more by a known CZ method or a known MCZ method in which a magnetic field is applied to a silicon melt in this CZ method to control the convection of the melt to pull up a single crystal, The silicon single crystal rod is pulled up so that the initial interstitial oxygen concentration is 10 to 25 ppma. At this time, the silicon polycrystal used as a raw material has an isotope ²⁸ Si content of 92.3% or more. The content in this case is preferably 94% or more, and more preferably 98% or more, in order to make the thermal conductivity and carrier mobility sufficiently high. Since the isotope ratio of the single crystal to be grown is almost determined by the isotope ratio of the raw material polycrystal, the quartz crucible and the seed crystal can be made of silicon having a natural isotope ratio. However, if the content of the isotope ²⁸ Si is 92.3% or more, the content of ²⁸ Si in the single crystal to be grown can be reliably increased.

  The CZ method and the MCZ method are methods for growing a single crystal rod having a desired diameter by bringing a seed crystal into contact with a melt of a polycrystalline silicon raw material contained in a quartz crucible and slowly pulling it up while rotating it. However, a conventional method may be used to set the initial interstitial oxygen concentration to the desired value. For example, by appropriately adjusting parameters such as the number of revolutions of the crucible, the flow rate of the introduced gas, the atmospheric pressure, the temperature distribution and convection of the silicon melt, or the strength of the applied magnetic field, the amount of oxygen melted from the crucible and the crystals are taken into the crystal. Since the amount of oxygen produced can be adjusted, crystals having a desired oxygen concentration can be obtained.

Doping nitrogen in the silicon single crystal to be grown can be easily performed by, for example, introducing a nitride such as a silicon wafer having a nitride film formed on the surface into a raw material polycrystal of a quartz crucible. . Further, the concentration of nitrogen doped in the crystal to be grown can be obtained by calculation from the amount of nitride introduced into the raw material polycrystal or the crucible, the segregation coefficient of nitrogen, and the like. At this time, it is preferable to introduce nitride so that the nitrogen concentration is 1 × 10 ^{13 to} 5 × 10 ¹⁵ atoms / cm ³ .

  The CZ silicon single crystal rod thus obtained is sliced by a cutting device such as a wire saw or an inner peripheral slicer according to a normal method, and then processed into a CZ silicon wafer through processes such as chamfering, lapping, etching, and polishing. Of course, these steps are merely exemplified and enumerated, and there are various other steps such as cleaning and heat treatment, and the steps are appropriately changed according to the purpose such as changing the order of the steps or partially omitting the steps.

  Next, heat treatment is performed so that the residual interstitial oxygen concentration is 8 ppma or less. Here, the heat treatment in which the residual interstitial oxygen concentration is 8 ppma or less cannot necessarily be specified because the oxygen precipitation amount depends on the initial interstitial oxygen concentration of the wafer to be heat-treated and the thermal history during crystal growth. It can be set experimentally according to conditions such as interstitial oxygen concentration and thermal history. Oxygen is precipitated by the heat treatment, and the initial interstitial oxygen concentration and the heat treatment conditions are set so that the interstitial oxygen concentration (residual interstitial oxygen concentration) after the heat treatment is 8 ppma or less, and the oxygen precipitation amount is controlled. Oxygen donor generation can be suppressed by reducing the residual interstitial oxygen concentration to 8 ppma or less. Preferably, the residual interstitial oxygen concentration is 6 ppma or less.

  In the present invention, it is necessary to consider not only the formation of oxygen precipitates by heat treatment but also the disappearance of COP. As a heat treatment for eliminating COP, it is preferable to perform a high-temperature heat treatment in an inert gas such as hydrogen gas or argon gas, or a mixed gas atmosphere thereof. Moreover, since there exists a bad effect that the width | variety of a transition area | region becomes wide, as heat processing temperature, 1000-1200 degreeC is preferable. Even at such a relatively low temperature, when the nitrogen is doped, the size of the COP is small, so that it can be sufficiently eliminated. Even when the nitrogen is not doped, the size of the COP is sufficiently large. Can be made smaller. Further, on the wafer surface side, reduction by out-diffusion of interstitial oxygen is also possible. Further, by using an inert gas such as hydrogen gas or argon gas, or a mixed gas thereof, the outward diffusion profile of oxygen changes abruptly on the wafer surface, so that a steeper transition region can be formed. .

  At this time, the heat treatment is divided into two stages of, for example, 1200 ° C. and 1000 ° C., COP is sufficiently extinguished or miniaturized by the first high-temperature heat treatment, and then oxygen precipitates are sufficiently grown by the second low-temperature heat treatment. This process is also possible. In addition, these heat processing can be performed using the normal vertical furnace and horizontal furnace (diffusion furnace) which can heat-process many wafers at once.

Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples, but the present invention is not limited to these examples.
(Example 1)
The ^{28 Si} silicon wafer content are formed is 98% of the raw material polycrystalline silicon and the surface of the nitride film was put into a quartz crucible, CZ method nitrogen-doped silicon single crystal ingot pulled by (without magnetic field application) Normal The CZ silicon wafer having a diameter of 200 mm, an initial interstitial oxygen concentration of 18 ppma (JEIDA), a nitrogen concentration of 8 × 10 ¹³ atoms / cm ³ (calculated value), and a resistivity of 2500 Ω · cm was manufactured.

  This wafer was heat-treated in a vertical heat treatment furnace at 1100 ° C. for 2 hours and 1000 ° C. for 16 hours in a 100% argon atmosphere, and further heat treatment assuming a device manufacturing process in a nitrogen atmosphere (3% oxygen mixture) (1200 1 hour at 450C + 5 hours at 450 ° C). The silicon wafer thus obtained was subjected to measurement of the residual interstitial oxygen concentration of the whole wafer by the infrared absorption method, and it was confirmed that the residual interstitial oxygen concentration in the wafer was 8 ppma or less.

Then, after angle-polishing these heat-treated wafers and measuring the resistivity from the surface to a depth of 100 μm by the spreading resistance method, any region in the wafer may have a high resistivity of 2000 Ω · cm or more. confirmed. Next, as a result of selectively etching the angle polished surface and observing with an optical microscope, the width of the transition region is as narrow and steep as about 5 μm, and the defect density in the oxygen precipitation region is sufficient as 5-8 × 10 ⁹ pieces / cm ^3. Value. In other words, it can be seen that the silicon wafer of Example 1 is a DZ-IG wafer having a very small gettering ability even when subjected to a heat treatment assuming a device manufacturing process, which is extremely less affected by the decrease in resistivity due to oxygen donors.

Further, the COP density having a diameter of 0.12 μm or more present on the surface of the wafer after the heat treatment and the surface polished by 3 μm was measured with a particle counter (SP1 manufactured by KLA Tencor). The measured COP density was 0.04 pieces / cm ² or less on both sides, and the density was low both on the wafer surface and at a depth of 3 μm from the surface. The precipitation distribution in the depth direction in the silicon wafer obtained in this example is schematically shown in FIG.

(Comparative Example 1)
A silicon single crystal pulled up under the same conditions as in Example 1 except that a raw material silicon polycrystal having a natural isotope composition ratio was used was processed by a normal method to obtain a diameter of 200 mm and an initial interstitial oxygen concentration of 18 ppma ( JEIDA), a CZ silicon wafer having a resistivity of 2500 Ω · cm was produced.

  This wafer was heat-treated in a vertical heat treatment furnace at 1100 ° C. for 2 hours and 1000 ° C. for 16 hours in a 100% argon atmosphere, and further heat treatment assuming a device manufacturing process in a nitrogen atmosphere (3% oxygen mixture) (1200 1 hour at 450C + 5 hours at 450 ° C). The silicon wafer thus obtained was subjected to measurement of the residual interstitial oxygen concentration of the whole wafer by the infrared absorption method, and it was confirmed that the residual interstitial oxygen concentration in the wafer was 8 ppma.

  And after angle-polishing the wafer after the heat treatment, the resistivity from the surface to a depth of 100 μm was measured by a spreading resistance measurement method. As a result, every region in the wafer had a resistivity of 1000 Ω · cm or more. It was found that the resistivity decreased slightly from 30 μm to 40 μm.

Further, the COP density having a diameter of 0.12 μm or more present on the surface of the wafer after the heat treatment and the surface polished by 3 μm was measured with a particle counter (SP1 manufactured by KLA Tencor). The measured COP density was about 0.06 / cm ^{2 on} either side, which was slightly higher than that in Example 1.

From the above results, it was confirmed that the defect-free layer can be widened by increasing the ratio of ²⁸ Si. Moreover, it can be expected that the heat dissipation effect and the operation speed are increased.
The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has the same configuration as that of the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

It is the schematic diagram which showed the precipitation distribution of the depth direction in the conventional silicon wafer. It is the schematic diagram which showed the precipitation distribution of the depth direction in the silicon wafer of Example 1 of this invention.

Claims (11)

A silicon wafer manufacturing method using at least a Czochralski method, a silicon polycrystalline material having a content of isotope ²⁸ Si of 92.3% or more, a resistivity of 100 Ω · cm or more, and an initial interstitial Growing a silicon single crystal rod having an oxygen concentration of 8 to 25 ppma, slicing the silicon single crystal rod into a wafer, and subjecting the wafer to a heat treatment, the residual interstitial oxygen concentration in the wafer is set to 8 ppma or less. A method for producing a silicon wafer, comprising:   The method for producing a silicon wafer according to claim 1, wherein nitrogen is doped when growing the silicon single crystal rod. ^{3. The} method for producing a silicon wafer according to claim 2, wherein the nitrogen concentration to be doped is 1 * 10 < ¹³ > to 5 * 10 < ¹⁵ > atoms / cm < ³ >.   The heat treatment is performed at a temperature of 1000 to 1200 ° C. for 1 to 20 hours in an atmosphere of hydrogen gas, an inert gas, or a mixed gas of hydrogen gas and an inert gas. Item 4. A method for producing a silicon wafer according to any one of Items 3 to 3.   The silicon wafer manufacturing method according to any one of claims 1 to 4, wherein a diameter of the silicon wafer is 200 mm or more.   A silicon wafer manufactured by the manufacturing method according to any one of claims 1 to 5. A silicon wafer having a resistivity of 100 Ω · cm or more grown by the Czochralski method, having an interstitial oxygen concentration of 8 ppma or less, an internal defect density of 1 × 10 ⁸ to 2 × 10 ¹⁰ pieces / cm ³ , and an isotope Body ²⁸ A silicon wafer having a Si content of 92.3% or more.   The silicon wafer according to claim 7, wherein the silicon wafer is doped with nitrogen. The silicon wafer according to claim 8, wherein the concentration of the doped nitrogen is 1 × 10 ^{13 to} 5 × 10 ¹⁵ atoms / cm ³ . 10. The COP density having a diameter of 0.12 μm or more on the surface of the silicon wafer is 0.05 pieces / cm ² or less, and is described in any one of claims 7 to 9. Silicon wafer.   The silicon wafer according to any one of claims 7 to 10, wherein the diameter is 200 mm or more.

Images