JP2005056239A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a DMA function for controlling data transfer between a RAM and peripherals and capable of smoothly adjusting access requests from the plurality of peripherals to the RAM. <P>SOLUTION: The semiconductor integrated circuit comprises: memory access control means 22a or the like connected to a peripheral circuit for generating access request signals requesting access to memory; a bus adjustment means 70 by which access to either one of the memory access control means issuing the access request signals is permitted according to priority set for the memory access control means; a counter 33a or the like which provides a count about the access state of the memory access control means to the memory; and a priority varying means 40 by which the priority set for the memory access control means is varied depending on the count provided by the counter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is a DMA that controls data transfer between a random access memory (RAM) and a peripheral (peripheral device or peripheral circuit of a RAM) without going through a central processing unit (CPU). The present invention relates to a semiconductor integrated circuit having a (direct memory access) function.

  Conventionally, in order to reduce the processing load on the CPU, a DMA data transfer method is known in which data transfer between a RAM and a peripheral is directly performed without the CPU performing a transfer process. In the DMA data transfer method, data transfer for writing data output from a peripheral to the RAM or outputting data read from the RAM to the peripheral is controlled by a DMAC (DMA controller) having an independent buffer inside. Done under.

  In a system using a plurality of peripherals, a plurality of DMACs are provided corresponding to the peripherals. In such a case, the DMA arbiter arbitrates the bus between the RAM and the plurality of peripherals based on the priority set in the DMAC so that data transfer under the control of the plurality of DMACs does not compete. Thus, any one of the plurality of DMACs is permitted to access the RAM.

  However, when the DMA arbiter permits access to the RAM based on a fixed priority set in advance at the time of manufacture, a necessary data transfer capability can be obtained for a peripheral corresponding to a DMAC having a low priority. There was a problem that there was no fear. That is, when a fixed priority is used, when access requests are continuously generated from the DMAC to which the highest priority is given, the access requests are always accepted. Requests could not be accepted for a long time, causing problems such as timeouts and overruns. On the other hand, when the priority is set to be quasi-fixed by the firmware, there is a problem that the CPU performance is lowered because the CPU resources are used accordingly.

  On the other hand, when the priority is recursively changed according to the access order of multiple peripherals, the priority is averaged over a certain number of accesses, so peripherals that perform high-speed operations and peripherals that perform low-speed operations are mixed. In such a system, there is a problem that the maximum system performance intended by the designer may not be obtained.

  As a related technique, the following Patent Document 1 describes an arbitration system and an arbitration method that reliably guarantees data transfer to a device or a DMA channel that needs to transfer data within a certain time. This arbitration system measures the time from the start of memory access to the start of the next memory access of a specific device that needs to transfer data within a certain time among multiple devices subject to arbitration. If it is detected that the specific device has not been selected for a certain period of time, the priority of the arbitration means is changed so that the priority of the specific device is the highest, or at least the second highest, and the memory access request of the specific device Can be permitted at regular intervals.

However, in this arbitration system, it is necessary to set a certain time regarding the memory access interval for all the specific devices whose priority is to be increased. For example, when data recorded in an external hard disk drive is written to a RAM, there is no need to set a transfer amount that must be transferred within a unit time, so there is no need to set a fixed time for a memory access interval. However, when it is desired to increase the priority of the external hard disk drive, since it is necessary to set a certain time for the memory access interval for the external hard disk drive, the setting becomes complicated.
JP-A-9-91194 (pages 1, 7 and FIG. 1)

  Therefore, in view of the above points, the present invention provides a semiconductor integrated circuit having a DMA function for controlling data transfer between a RAM and a peripheral without using a CPU. Even in a system using a large number of peripherals, An object of the present invention is to provide a semiconductor integrated circuit capable of smoothly arbitrating access requests from a plurality of peripherals to a RAM even in a system using the peripherals.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having a direct memory access function for controlling access to a memory from a plurality of peripheral circuits without using a central processing unit. Multiple memory access control that controls the data transfer between the peripheral circuit and the memory when an access request signal is generated to request access to the memory connected to the peripheral circuit and access to the memory is permitted And one of the memory access control means for generating an access request signal is allowed to access the memory based on the priority set for the means and the plurality of memory access control means, and access to the memory is permitted. Bus arbitration means for arbitrating the bus between the memory access control means and the memory, and a plurality of memory access control means A plurality of counters for obtaining a plurality of count values relating to the access state of the memory, and a priority set for the plurality of memory access control means is changed based on the plurality of count values obtained by the plurality of counters. Priority order changing means.

  Here, the priority order changing means includes a register that holds a plurality of predetermined values, and is based on a comparison result between a plurality of count values obtained by the plurality of counters and a plurality of predetermined values held by the register. Thus, the priority order set for a plurality of memory access control means may be changed.

  The semiconductor integrated circuit further includes a plurality of second counters for obtaining a plurality of count values related to access requests to the memories of the plurality of memory access control means, and the priority changing means is obtained by the plurality of counters. The priority order set for the plurality of memory access control means may be changed based on the plurality of count values and the plurality of count values obtained by the plurality of second counters.

  In addition, the semiconductor integrated circuit stores the information related to the memory access control means that is finally permitted to access the memory, and the memory access is finally performed based on the information stored in the storage means. Access request signal masking means for masking the access request signal output from the permitted memory access control means for a predetermined period so as not to be input to the bus arbitration means may be provided.

  According to the present invention, the priority set for the plurality of memory access control means is changed based on the plurality of count values related to the memory access states of the plurality of memory access control means. In both the system used and the system using a small number of peripherals, access requests from a plurality of peripherals to the RAM can be smoothly arbitrated.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a system including a semiconductor integrated circuit according to the first embodiment of the present invention. This system is a system for processing print data in a printer. As shown in FIG. 1, this system includes a RAM 10 that stores data, a semiconductor integrated circuit 20 that writes data to and reads data from the RAM 10 by a DMA data transfer method, and a CPU 90 that controls the entire system. Including.

  The semiconductor integrated circuit 20 is provided corresponding to a plurality of peripherals 21a, 21b,..., And a plurality of DMACs 22a, 22b,... That control data transfer between these peripherals and the RAM 10. And a memory interface 23 that exchanges data with the RAM 10 and a DMA arbiter 30 that performs bus arbitration between the plurality of DMACs and the memory interface 23.

  Here, as the peripherals 21a, 21b,..., A print data interface for transferring data to and from the printing unit inside the printer, and a scanner for transferring data to and from the scanner attached to the printer. Interface, IEEE1394 or USB (universal serial bus) that is a serial interface for transferring data to and from an external device such as a personal computer or digital camera, IEEE1284 that is a parallel interface, or a device connected to a network This corresponds to a network interface for transferring data between the two.

  Each of the DMACs 22a, 22b,... Has an independent buffer, and writes data output from each peripheral to the RAM 10, and outputs data read from the RAM 10 to each peripheral. Each of the DMACs 22a, 22b,... Generates a request signal for requesting access to the RAM 10, and receives an acknowledge signal when the access is permitted.

  The DMA arbiter 30 performs bus arbitration between the DMACs and the memory interface 23 based on the request signals input from the DMACs 22a, 22b,... Do. In the present embodiment, the DMA arbiter 30 receives a request signal output from each DMAC to request use of the bus and an acknowledge signal input to permit each DMAC to use the bus. By sampling in a predetermined period, the priority order of the DMACs 22a, 22b,... Is changed based on the time when the request signal is output and the time when the acknowledge signal is input.

  FIG. 2 is a block diagram showing a detailed configuration of the DMA arbiter shown in FIG. FIG. 2 shows an example using three DMACs. As shown in FIG. 2, the DMA arbiter 30 has two timers 31 and 32, counters 33a to 33c for accumulating the time when the request signal is output from each DMAC, and an acknowledge signal is input to each DMAC. Including a counter 34a to 34c that accumulates a certain amount of time, a priority generator unit 40 that changes the priority order of a plurality of DMACs, an arbiter unit 70 that permits any DMAC to access the RAM 10, and a multiplexer 35. Yes.

  The timer 31 outputs a timing signal that defines a period during which sampling is continued. The timer 32 outputs a sampling clock signal used for sampling the request signal and the acknowledge signal.

  The counter 33a is reset by the timing signal, and outputs a count value Ca1 corresponding to the time when the request signal is output from the DMAC 22a by counting the pulses of the sampling clock signal when the request signal is output from the DMAC 22a. To do. Similarly, the counter 33b outputs a count value Cb1 corresponding to the time during which the request signal is output from the DMAC 22b by counting pulses of the sampling clock signal when the request signal is output from the DMAC 22b. 33c outputs a count value Cc1 corresponding to the time during which the request signal is output from the DMAC 22c by counting the pulses of the sampling clock signal when the request signal is output from the DMAC 22c.

  The counter 34a is reset by the timing signal, and when the acknowledge signal indicating the bus access right to the RAM 10 is input to the DMAC 22a, by counting the pulses of the sampling clock signal, the time during which the acknowledge signal is input to the DMAC 22a A count value Ca2 corresponding to is output. Similarly, the counter 34b counts the pulses of the sampling clock signal when the acknowledge signal is input to the DMAC 22b, thereby outputting the count value Cb2 corresponding to the time when the acknowledge signal is input to the DMAC 22b. 34c outputs the count value Cc2 corresponding to the time when the acknowledge signal is input to the DMAC 22c by counting the pulses of the sampling clock signal when the acknowledge signal is input to the DMAC 22c.

  The priority generator unit 40 changes the priority order of the already set DMACs based on the counter values obtained in the counters 33a to 33c and 34a to 34c. The arbiter unit 70 outputs an acknowledge signal to one of the DMACs and outputs a bus arbitration signal based on the request signals output from the plurality of DMACs and the priority order of the plurality of DMACs. The multiplexer 35 connects the bus between any DMAC and the memory interface 23 based on the bus arbitration signal.

  In this embodiment, the sampling duration is defined by the pulse period T1 of the timing signal output from the timer 31, and the sampling period is defined by the pulse period T2 (<T1) of the sampling clock signal output from the timer 32. To do.

That is, as shown in FIG. 3, when the request signal Ra is output from the DMAC 22a, the count value Ca1 in the counter 33a is incremented by 1 every sampling period T2, and the count value Ca1 is N during the sampling period T1. Increase to _R. In this case, the request signal is output during the period N _R × T2.

Further, when the acknowledge signal is inputted to the DMAC22a count value Ca2 in the counter 34a for each sampling period T2 is incremented by 1, the count value Ca2 during the sampling period T1 is increased to _{N A.} In this case, the acknowledge signal is output during the period of N _A × T2. Thus, by counting in synchronization with the sampling clock signal output from the timer 32, it is not necessary to use a high bit counter.

  Referring to FIG. 2 again, the priority generator 40 synchronizes with the timing signal output from the timer 31 based on the count values Ca1 to Cc1 and Ca2 to Cc2 output from the counters 33a to 33c and 34a to 34c, respectively. Then, the priority order of the DMACs 22a to 22c is changed using a plurality of different changing methods, and signals P1 and P2 representing the changed priority order are output.

  The arbiter unit 70 is one of the acknowledge signals Aa to Ac based on the signals P1 and P2 indicating the priority order output from the priority generator unit 40 and the request signals Ra to Rc output from the DMACs 22a to 22c. Is output to the corresponding DMAC, and a bus arbitration signal BA for connecting the DMAC that has output the acknowledge signal and the memory interface 23 is output.

  FIG. 4 is a block diagram showing a detailed configuration of the priority generator unit shown in FIG. As shown in FIG. 4, the priority generator unit 40 includes a priority generator 50 that changes the priority order used in the first arbiter and a priority generator 60 that changes the priority order used in the second arbiter.

  Based on the count values Ca2 to Cc2, the priority generator 50 changes the signal P1 that gives priority to the DMACs 22a to 22c in synchronization with the timing signal output from the timer 31. Further, the priority generator 60 changes the signal P2 giving the priority of the DMACs 22a to 22c in synchronization with the timing signal output from the timer 31 based on the count values Ca1 to Cc1 and Ca2 to Cc2. Signals P1 and P2 indicating the priority changed by the priority generators 50 and 60 are output to the arbiter unit 70, respectively.

  FIG. 5 is a block diagram showing a detailed configuration of the priority generator 50 shown in FIG. The priority generator 50 changes the priority of the highest priority peripheral such as an interface of a printing unit or a scanner that must transfer a predetermined amount of data within a predetermined time, and has a desired transfer capability for the peripheral. It is a functional block for guaranteeing.

  As shown in FIG. 5, the priority generator 50 includes registers 51a to 51c that hold data representing desired transfer capacities set corresponding to the DMACs 22a to 22c, and a count value Ca2 when a timing signal is input. Based on the actual transfer capability calculation unit 52a for calculating the amount per unit time of the data actually transferred by the DMAC 22a during the sampling continuation period, and the data actually transferred by the DMAC 22b based on the count value Cb2. An actual transfer capability calculator 52b that calculates the amount per unit time, and an actual transfer capability calculator 52c that calculates the amount per unit time of data that the DMAC 22c actually transferred based on the count value Cc2. Contains.

Each transfer amount calculating unit uses the following equation (1) to calculate the actual transfer capability of each DMAC _Q R a (Mbps).
_{Q R = Q A × N A} × T2 / T1 ··· (1)
However, _{Q A} is data transferable per unit time (Mbps), _{N A} is the count value output from each counter 34a~34c when the timing signal is input.

  The priority generator 50 also compares the data representing the desired transfer capability held in the registers 51a to 51c with the comparison units 53a to 53c that compare the actual transfer capability calculated by the actual transfer capability calculation units 52a to 52c, respectively. , And a priority changing unit 54 that changes the priority based on the result of comparison in the comparing units 53a to 53c.

Here, the priority changing unit 54, based on the comparison result of the comparing unit 53a-53c, the DMAC priority real transfer capacity Q _R is below the desired transfer capability, and change the priority of the upper, change The signal P1 indicating the priority order is output to the arbiter unit 70. Here, the priority change portion 54, to the actual transfer capacity Q _R may change the priority as the priority of the DMAC is below the desired transfer capability is increased by one, to the desired transfer capacity the ratio of the actual transfer capacity Q _R may change the priority as the priority as the smallest DMAC increases. Note that the initial value of the priority order is set by the CPU 90 at startup.

  FIG. 6 is a block diagram showing a detailed configuration of the priority generator 60 shown in FIG. The priority generator 60, like an external hard disk drive, does not define the amount of data to be transferred within a certain period of time. However, the priority generator 60 can smoothly transfer data without much delay in being granted permission to use the bus. Is a functional block for changing the priority of a semi-priority peripheral as desired and ensuring smooth data transfer to that peripheral.

  As shown in FIG. 6, the priority generator 60 is based on the standby time calculation unit 61a that calculates the standby time of the DMAC 22a based on the count values Ca1 and Ca2 when the timing signal is input, and on the basis of the count values Cb1 and Cb2. The standby time calculation unit 61b that calculates the standby time of the DMAC 22b and the standby time calculation unit 61c that calculates the standby time of the DMAC 22c based on the count values Cc1 and Cc2.

The standby time calculation units 61a to 61c calculate the standby times T of the bus use requests of the DMACs 22a to 22c, respectively, using the following equation (2).
T = (N _R −N _A ) × T2 (2)
Here, N _R is a count value input from each counter when a timing signal is input from the timer 31 shown in FIG. 2 to each standby time calculation unit.

  The priority generator 60 includes a comparison unit 62 that compares the standby times T calculated by the standby time calculation units 61a to 61c, and a priority order change unit 63 that changes the priority order based on the comparison result in the comparison unit 62. Contains.

  Here, the priority changing unit 63 compares the standby times T corresponding to the respective DMACs, changes the priority so that the higher the standby time T is, the higher the priority is, and a signal indicating the changed priority P2 is output to the arbiter unit 70. Note that the initial value of the priority order is set by the CPU 90 at startup.

  FIG. 7 is a block diagram showing a detailed configuration of the arbiter unit shown in FIG. As shown in FIG. 7, the arbiter unit 70 includes registers 71a to 71c and 72a to 72c that hold data set by the CPU 90 in order to select a method for changing the priority order, three-input AND circuits 73a to 73c, 74a-74c, 75a-75c, and arbiters 76a-76c and 77 are included. Each of the arbiters 76a to 76c selects one of the request signals Ra to Rc (when it exists) based on the respective priorities, and outputs a signal representing the DMAC that has output the selected request signal. To do.

  Here, the arbiter 76a selects a request signal input from one of the DMACs via the AND circuits 73a to 75a based on the signal P1 indicating the priority order, and a signal indicating the DMAC that has output the selected request signal. S1 is output. The arbiter 76b selects a request signal input from any of the DMACs via the AND circuits 73b to 75b based on the signal P2 indicating the priority, and outputs a signal S2 indicating the DMAC that has output the selected request signal. To do. The arbiter 76c selects a request signal input from one of the DMACs via the AND circuits 73c to 75c based on a predetermined priority, and outputs a signal S3 representing the DMAC that has output the selected request signal. Output.

  Here, each of the arbiters 76a to 76c selects the request signal of the DMAC having the highest priority among the DMACs that output the input request signals based on the respective priority orders, and selects the selected request signal. Is output to the arbiter 77.

  Further, the arbiter unit 77 selects one of the signals S1 to S3 input from the arbiters 76a to 76c based on a predetermined priority order, and acknowledges the DMAC indicated by the selected signal. Is output to the multiplexer 35 as the bus arbitration signal BA.

  In this embodiment, the arbiter 77 selects the signal S1 output from the arbiter 76a with the highest priority based on the priority changed to guarantee the desired transfer capability, and is output from the arbiter 76b. The signal S2 is selected with the next highest priority, and the signal S3 output from the arbiter 76c is selected with the lowest priority based on the fixed priority.

  That is, when a request signal is input from any DMAC to the arbiter 76a, the arbiter 77a outputs the signal S1 output from the arbiter 76a because the arbiter 76a outputs the signal S1 having the highest priority. select.

  If no request signal is input from any DMAC to the arbiter 76a and a request signal is input from any DMAC to the arbiter 76b, the signal S1 is not output from the arbiter 76a, and the arbiter 76b Since the signal S2 is output, the arbiter 77 selects the signal S2 output from the arbiter 76b.

  Further, when a request signal is not input from any DMAC to the arbiters 76a and 76b and a request signal is input from any DMAC to the arbiter 76c, signals S1 and S2 are output from the arbiters 76a and 76b. Since the signal S3 is output from the arbiter 76c, the arbiter 77 selects the signal S3 output from the arbiter 76c.

  Based on the signal input from any arbiter, the arbiter 77 outputs an acknowledge signal to the DMAC represented by the signal, and outputs the signal to the multiplexer 35 as the bus arbitration signal BA. The multiplexer 35 performs bus arbitration between the DMAC and the memory interface 23 based on the bus arbitration signal BA.

  Note that the priority changing method for accessing a RAM by a plurality of DMACs is set by data held in the registers 71 and 72. That is, whether the peripheral corresponding to each DMAC is the highest priority peripheral, the semi-priority peripheral, or the low-priority peripheral is set by the data held in the registers 71 and 72.

  For example, when arbitrating the bus between the DMAC 22a and the memory interface 23 based on the signal P1 indicating the priority, the register 71a and 72a holds the high level signal “1” and is output from the DMAC 22a. The request signal is input to the arbiter 76a via the AND circuit 73a, and the output signals of the AND circuits 74a and 75a are always at the low level, so that they are not input to the arbiters 76b and 76c. Therefore, the bus between the DMAC 22a and the memory interface 23 is arbitrated by the arbiter 76a based on the signal P1 indicating the priority.

  Similarly, when the bus between the DMAC 22a and the memory interface 23 is arbitrated based on the signal P2 indicating the priority, a high level signal “1” is stored in the register 71a and a low level signal “0” is stored in the register 72a. , The request signal output from the DMAC 22a is input to the arbiter 76b via the AND circuit 74a. Therefore, the bus between the DMAC 22a and the memory interface 23 is arbitrated by the arbiter 76b based on the signal P2 indicating the priority.

  When arbitrating the bus between the DMAC 22a and the memory interface 23 based on a preset priority, the register 71a holds a low level signal “0” and the register 72a holds a high level signal “1”. As a result, the request signal output from the DMAC 22a is input to the arbiter 76c via the AND circuit 75a. Therefore, the bus between the DMAC 22a and the memory interface 23 is arbitrated by the arbiter 76c based on a preset priority.

  Next, a semiconductor integrated circuit according to a second embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration of a system including a semiconductor integrated circuit according to the second embodiment of the present invention. In this semiconductor integrated circuit, instead of the DMA arbiter 30, the DMA arbiter 80 performs bus arbitration between the plurality of DMACs and the memory interface 23. Other configurations are the same as those of the semiconductor integrated circuit shown in FIG.

  FIG. 9 is a block diagram showing a detailed configuration of the DMA arbiter shown in FIG. As shown in FIG. 9, the DMA arbiter 80 stores the bus arbitration signal BA to the past recorder 81 that stores the information of the DMAC that used the bus lastly, and the bus arbitration signal BA that the past recorder 81 stores. The request maskers 82a to 82c mask the request signal output to the arbiter unit 70 by not outputting the request signal output from the DMAC using the bus for one clock signal. Other configurations are the same as those of the DMA arbiter 30 shown in FIG.

  Next, operations of the past recorder 81 and the request maskers 82a to 82c will be described. The past recorder 81 stores the bus arbitration signal BA last output from the arbiter unit 70. Since the bus arbitration signal BA is a signal for the multiplexer 35 to connect one of the buses of the memory interface 23 and the DMAC, the bus arbitration signal BA output last is the information of the DMAC that last accessed the RAM 10. Equivalent to.

  Here, for example, when a request signal is continuously output from the DMAC corresponding to the highest priority peripheral, the request signal is output from the DMAC corresponding to the semi-priority peripheral during the period in which the request signal is output. However, there is a possibility that the RAM control by the DMAC corresponding to the highest priority peripheral is continuously performed.

  Therefore, in the present embodiment, the past recorder 81 outputs a mask control signal for masking the request signal to the request masker corresponding to the DMAC represented by the bus arbitration signal BA, and the request masker to which the mask control signal is input is output. The request signal output from the DMAC represented by the bus arbitration signal BA is masked for one clock in synchronization with the mask control signal.

  As a result, even if the request signal is output from the DMAC corresponding to the semi-priority peripheral within the period in which the request signal is continuously output from the DMAC corresponding to the highest priority peripheral, it is output from the DMAC corresponding to the highest priority peripheral. The DMAC corresponding to the semi-priority peripheral can start controlling the RAM during the period when the request signal to be processed is masked.

  Thereby, in this embodiment, even when a request signal is continuously output from a DMAC having a high priority, the other DMAC uses the bus without being exclusively used by the DMAC having a high priority. It becomes possible to do.

  As described above, the present invention can be used for a system for processing print data in a printer having different types of peripherals such as a video interface and a network interface.

1 is a block diagram showing a configuration of a system including a semiconductor integrated circuit according to a first embodiment of the present invention. The block diagram which shows the detailed structure of the DMA arbiter shown in FIG. The timing chart which shows the operation | movement in each part of DMA arbiter. The block diagram which shows the detailed structure of the priority generator part shown in FIG. The block diagram which shows the detailed structure of the priority generator 50 shown in FIG. The block diagram which shows the detailed structure of the priority generator 60 shown in FIG. The block diagram which shows the detailed structure of the arbiter part shown in FIG. The block diagram which shows the structure of the system containing the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. The block diagram which shows the detailed structure of the DMA arbiter shown in FIG.

Explanation of symbols

10 RAM, 20 semiconductor integrated circuit, 21a-21c peripheral, 22a-22c DMAC, 23 memory interface, 30, 80 DMA arbiter, 31, 32 timer, 33a-33c, 34a-34c counter, 35 multiplexer, 40 priority generator section, 50, 60 priority generator, 51a-51c, 71a-71c, 72a-72c register, 52a-52c actual transfer capacity calculation unit, 53a-53c, 62 comparison unit, 54, 63 priority change unit 61a-61c standby time calculation unit 73a-73c, 74a-74c, 75a-75c AND circuit, 76a-76c, 77 arbiter, 81 past register, 82a-82c request masker, 90 CPU (center Arithmetic unit)

Claims (4)

A semiconductor integrated circuit having a direct memory access function for controlling access to a memory from a plurality of peripheral circuits without going through a central processing unit,
An access request signal connected to each peripheral circuit to request access to the memory is generated, and when access to the memory is permitted, data transfer between the peripheral circuit and the memory is controlled. A plurality of memory access control means;
Based on the priority set for the plurality of memory access control means, any one memory access control means for generating an access request signal is allowed to access the memory, and access to the memory is allowed. Bus arbitration means for performing bus arbitration between the memory access control means and the memory,
A plurality of counters for obtaining a plurality of count values related to an access state to the memory of the plurality of memory access control means;
Priority order changing means for changing the priority order set for the plurality of memory access control means based on a plurality of count values obtained by the plurality of counters;
A semiconductor integrated circuit comprising: The priority changing unit includes a register that holds a plurality of predetermined values, and is based on a comparison result between a plurality of count values obtained by the plurality of counters and a plurality of predetermined values held by the register. 2. The semiconductor integrated circuit according to claim 1, wherein the priority order set for said plurality of memory access control means is changed. A plurality of second counters for obtaining a plurality of count values related to access requests to the memory by the plurality of memory access control means;
The priority changing unit is configured to control the plurality of memory access control units based on a plurality of count values obtained by the plurality of counters and a plurality of count values obtained by the plurality of second counters. Change the set priority,
The semiconductor integrated circuit according to claim 1 or 2. Storage means for storing information relating to the memory access control means that was last granted access to the memory;
Based on the information stored in the storage means, the access request signal output from the memory access control means that is finally permitted to access the memory is masked for a predetermined period so as not to be input to the bus arbitration means. Access request signal masking means;
The semiconductor integrated circuit according to claim 1, further comprising:

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