JP2014004694A - Liquid discharge device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To distribute data transfer.SOLUTION: A liquid discharge device for discharging liquid from a head in response to data transmitted from a system comprises: a first data transmission line of a system side; a second data transmission line of a head side; a bridge for performing data conversion between the first data transmission line and the second data transmission line; a memory controller connected to the first data transmission line; a memory connected to the memory controller; and a plurality of head controllers that is connected to the second transmission line and is provided with direct memory access controllers. The bridge transmits requests less than the number of the head controllers that are the requests from the plurality of head controllers to the memory controller via the first transmission line at predetermined time intervals.

Description

  The present invention relates to a liquid ejection apparatus.

Inkjet printers that eject ink and form images have been put into practical use. A print head of an ink jet printer is formed with a nozzle row in which nozzles form a row in the paper feed direction, and a plurality of such nozzle rows are provided. Each of these nozzles is driven simultaneously, and a liquid such as ink is ejected.
An image formed by ink ejection is performed by sending pixel data corresponding to each pixel stored in the buffer to the print head. As described above, since the nozzles are driven simultaneously, the pixel data of the buffer is sent out simultaneously. Therefore, requests for image blocks are generated at the same time in requests for pixel data to be stored in the buffer. The requests that occur at the same time are subjected to arbitration for sequential processing.

  According to Patent Document 1, a DMA arbiter adjusts a bus between a RAM and a plurality of peripherals based on the priority set in the DMAC, thereby allowing a RAM for any one of the plurality of DMACs. Has been shown to allow access to.

JP 2005-56239 A

  In data transfer in an ink jet printer, as described above, a data transfer request for a predetermined image block may be made, but the rate of data transfer during the entire processing is low. However, even if the total ratio is low, since requests for image blocks are made, there may be a timing when many requests are concentrated at the same time. In this case, other devices may be affected in the meantime, which is undesirable from the viewpoint of QoS (Quality of Service) of the entire system. In other words, it can be said that it is desirable to further distribute the data transfer.

  The present invention has been made in view of such circumstances, and an object thereof is to distribute data transfer.

The main invention for achieving the above object is:
In a liquid ejection apparatus that ejects liquid from the head according to data sent from the system,
A first data transmission path on the system side;
A second data transmission path on the head side;
A bridge that performs data conversion between the first data transmission path and the second data transmission path;
A memory controller connected to the first data transmission path;
A memory connected to the memory controller;
A plurality of head controllers connected to the second transmission line and provided with a direct memory access controller;
With
The bridge sends requests from the head controller that are smaller in number than the number of head controllers to the memory controller via the first transmission path at a predetermined time interval. This is a liquid ejection device.

  Other features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

1 is a block diagram of a printing system 100 in the present embodiment. 1 is a perspective view of an inkjet printer 1 in the present embodiment. It is an internal side view of the inkjet printer 1 in this embodiment. It is explanatory drawing of the nozzle structure in the head in this embodiment. 2 is a block diagram of a controller 50 in the printer 1. FIG. It is explanatory drawing of the data transfer type | system | group in a reference example. It is a graph of an unresolved request in a reference example. It is explanatory drawing of the data transfer type | system | group in this embodiment. It is a block diagram explaining operation | movement of the bridge | bridging 515 in this embodiment. It is explanatory drawing of the data conversion example of the bridge | bridging 516 in this embodiment. It is a transaction chart in this embodiment. It is a graph of an unresolved request in this embodiment. It is a transaction chart in a reference example.

At least the following matters will become clear from the description of the present specification and the accompanying drawings. That is,
In a liquid ejection apparatus that ejects liquid from the head according to data sent from the system,
A first data transmission path on the system side;
A second data transmission path on the head side;
A bridge that performs data conversion between the first data transmission path and the second data transmission path;
A memory controller connected to the first data transmission path;
A memory connected to the memory controller;
A plurality of head controllers connected to the second transmission line and provided with a direct memory access controller;
With
The bridge sends requests from the head controller that are smaller in number than the number of head controllers to the memory controller via the first transmission path at a predetermined time interval. This is a liquid ejection device.
By doing so, requests from the head controller can be sent to the memory controller with a predetermined time interval, so that data transfer can be distributed. At this time, since the number of requests smaller than the number of head controllers is sent, data transfer can be further distributed.

In the liquid ejecting apparatus, the bridge may request one request from each head controller at the predetermined time interval, and send one request at the predetermined time interval via the first transmission path. It is desirable to send it to the memory controller.
In this way, since one request is sent at every predetermined time interval, data transfer can be reliably distributed.

In this liquid ejection apparatus, it is preferable that the bridge includes a timer for measuring the predetermined time interval.
In this way, since a request can be sent at predetermined time intervals using a timer, data transfer can be distributed.

In the liquid ejecting apparatus, it is preferable that the bridge includes a buffer that stores the request.
In this way, requests accumulated in the buffer can be sent sequentially at predetermined time intervals.

In this liquid ejection apparatus, it is preferable that the band of the second data transmission path is narrower than the band of the first transmission path.
Even in such a transmission line, the bridge performs data conversion, so that data can be transferred appropriately and resources of the second data transmission line can be saved.

In such a liquid ejection apparatus, it is preferable that the bridge performs ID conversion of the direct memory access controller in the head controller inside the bridge.
By doing so, it is possible to suppress an increase in ID management resources that accompanies an increase in the number of IDs. Further, even if the number of direct memory access controllers varies, there is an advantage that the first data transmission path is not affected.

In the liquid ejecting apparatus, it is preferable that the system sends data in response to a request from the head controller.
By doing so, data is sent in response to requests sent at predetermined time intervals, so that data transfer can be distributed.

In such a liquid ejecting apparatus, it is preferable that the data sent from the system side is data defining a dot size formed by ejecting the liquid.
As described above, in a situation where liquids are simultaneously ejected from a plurality of nozzles at a predetermined timing to form an image, there may be a request for data defining the dot size all at once. If there is, the data request is distributed, so the data transfer can be distributed.

=== Embodiment ===
FIG. 1 is a block diagram of a printing system 100 in the present embodiment. FIG. 2 is a perspective view of the ink jet printer 1 according to the present embodiment. FIG. 3 is an internal side view of the inkjet printer 1 in the present embodiment.

  The printing system 100 includes an inkjet printer 1 (hereinafter simply referred to as “printer 1”) as a printing apparatus and a computer 110. The printer 1 prints an image on a medium such as paper, cloth, or film. The computer 110 is communicably connected to the printer 1 via an interface (not shown). In order to cause the printer 1 to print an image, the computer 110 outputs print data including pixel data corresponding to the image to the printer 1. Computer programs such as application programs and printer drivers are installed on the computer 110.

  The ink jet printer 1 includes a paper transport unit 20, a recording unit 40, a controller 50, an external memory 60, and a drive signal generation unit 70.

  The paper transport unit 20 includes a transport roller 22 and a paper discharge roller 24. The transport roller 22 supplies the medium from the roll R to the recording unit 40. The paper discharge roller 24 discharges the printed medium.

The recording unit 40 includes a head 41 that ejects ink onto a medium conveyed along the conveyance path 26. The head 41 is mounted on a carriage 43 that is movable in the width direction of the transport path 26. An ink cartridge (not shown) that stores ink is mounted on the carriage 43. The head 41 includes a plurality of nozzle rows and is configured to eject each ink. The head 41 performs image formation for recording information such as a predetermined image and characters by ejecting ink onto the recording surface of the medium.

  The ink jet printer 1 includes a controller 50 that comprehensively controls the operation of each of the constituent devices. The controller 60 controls the paper transport unit 20, the recording unit 40, and the drive signal generation unit 70. The controller 60 controls data transfer between the head 41 and the external memory 60 as will be described later.

  The drive signal generation unit 70 supplies a drive signal to each piezo element (not shown) of the head 41 of the recording unit 40. The drive signal generation unit 70 receives digital data defining the shape of the drive signal from the controller 50, and generates a drive signal COM that is a voltage waveform based on the digital data.

  FIG. 4 is an explanatory diagram of a nozzle configuration in the head in the present embodiment. FIG. 4 shows a state when the nozzle row is visually recognized from the upper surface of the head. The head 41 is composed of four nozzle rows. Each nozzle row has 100 nozzles from nozzle number # 1 to nozzle number # 100. In FIG. 4, nozzle numbers # 1 to # 100 are assigned from nozzles on the downstream side in the medium conveyance direction to nozzles on the upstream side. These nozzles are arranged in the transport direction at a nozzle pitch P.

  The four nozzle arrays are a yellow ink nozzle array that ejects yellow ink Y, a magenta ink nozzle array that ejects magenta ink M, a cyan ink nozzle array C that ejects cyan ink C, and a black that ejects black ink K. Ink nozzle row K is included. That is, the head 41 has 400 nozzles.

  In the printer 1, based on print data including image data, an ejection operation for intermittently ejecting ink from the head 41 that moves in the movement direction by the carriage 43 to form a dot row on the medium along the movement direction, and paper The conveyance operation of conveying the medium in the conveyance direction by the conveyance unit 20 is repeated alternately. As a result, dots can be formed at positions different from the positions of the dots formed by the previous dot formation operation, and a two-dimensional image can be formed on the paper.

  In such a head, one nozzle forms four types of pixel states of “no dot”, “small dot”, “medium dot”, and “large dot” for one pixel. That is, in this embodiment, 2-bit pixel data is sent for one pixel.

  Such pixel data is generated by the printer driver in the computer 110 described above, data such as a command is added, and the print data is sent to the controller 50 of the printer 1. Print data is stored in the external memory 60 via the controller 50.

  The accumulated data is sent to each DMA controller via the controller 50 in accordance with a request from the DMA controller in the head 41.

  FIG. 5 is a block diagram of the controller 50 in the printer 1. The controller 50 includes a communication interface 52, a processor 511, and a module 513. The controller 50 includes a secondary cache, a shared memory, a memory controller, and a network on chip 51.

  A communication interface 52, a processor 511, a module 513, and a neck controller unit 517 are connected to the secondary cache, shared memory, memory controller, and network-on-chip 51. Further, it is connected to the external memory 60 via a physical interface.

  The communication interface 52 is connected to the computer 110 as described above and performs various communications. The processor 511 performs processing such as computation in the controller 50. The module 513 is, for example, an image processor that performs processing related to an image. A head control unit (hereinafter sometimes simply referred to as “HCU”) 517 is a unit that controls the head 41 and, as will be described later, a direct memory access controller (hereinafter referred to as “DMA controller” or simply “DMA”). And a request for data read is sent to the external memory 60.

  The head control unit 517 that sends data to the head 41 reads necessary data from the image buffer on the external memory 60 and stores it in a buffer inside the head control unit 517 for use.

  When the buffer inside the head control unit 517 becomes empty, ink cannot be ejected from the head 41. Therefore, the head control unit 517 replenishes data from the image buffer of the external memory 60 before the buffer becomes empty.

  In order for the head control unit 517 to read data from the image buffer, DMA is performed without using the processor 511. A plurality of DMAs are mounted in the head control unit 517, and each DMA constantly monitors the buffer in the head control unit 517 during printing, and when this buffer becomes empty by a certain amount, reading from the image buffer of the external memory 60 is performed. I do.

  As described above, the head 41 of the inkjet printer 1 employs a structure in which a large number of nozzles are arranged in the paper feeding direction and a plurality of such nozzle rows are provided. Needless to say, one nozzle row is driven at the same time, and ink ejection is driven at almost the same timing even between different nozzles. Then, the pixel data of the buffer is used almost at the same time. That is, the read request from the DMA image buffer for replenishing the pixel data of the head control unit 517 is at the same timing for at least the nozzles in the same row.

  Therefore, a large number of read requests are made at a certain timing. In order to cope with this, if a system including a DMA that performs long burst transfer is adopted, even if the number of DMAs is small, it affects other devices and guarantees the responsiveness of real-time control. The design is prone to problems.

  FIG. 6 is an explanatory diagram of a data transfer system in the reference example. FIG. 6 shows an external memory 60 used as an image buffer and 20-channel head control units (ch1 to ch20). The head control unit of each channel includes a DMA for printing data transfer including pixel data, a buffer, and a head control unit subsequent stage processing unit.

  The print data transfer DMA reads the print data from the image buffer and sends it to the head 41 via the buffer and the head control unit post-processing unit.

  Here, it is assumed that data transfer of 400 nozzles per channel is performed. Since there are 20 print data transfer DMAs, data transfer for a total of 8000 nozzles is performed. When each channel issues a request with an unprocessed number (Outstanding) “1”, the total number of unprocessed requests is 20.

  FIG. 7 is a graph of unresolved requests in the reference example. In FIG. 7, time is shown on the horizontal axis, and the number of unresolved requests is shown on the vertical axis. In addition, a deadline is shown at a certain time. The deadline indicates a time restriction in which the pixel data buffer in the head 41 is not emptied and an image can be appropriately formed if the number of unresolved requests is zero before the deadline.

  FIG. 7 shows a state in which the number of unresolved requests reaches 20 at the moment because a read request is made from the DMA for print data transfer for 20 channels as described above. Thus, although temporarily, the number of unresolved requests increases, requests from other devices cannot be processed during that time.

  However, as shown in FIG. 7, there is still considerable margin before the print data transfer deadline. This is because the ink ejection process for forming an image while moving at a speed of about 1 m / s is a mechanical process, and is slower than the data transfer process.

  Therefore, it is desirable to distribute requests by controlling the request interval in consideration of the deadline and the system speed using the configuration of the present embodiment described below.

  FIG. 8 is an explanatory diagram of a data transfer system in the present embodiment. In FIG. 8, a processor 511, a memory controller 512, an image processor 513, a system NoC 514, a bridge 515, a DMA_NoC 516, and a plurality of head control units 517-N included in the controller 50 are shown.

  The processing of the processor 511 and the image processor 513 is as already described. The memory controller 52 performs processing for the external memory 60.

  A system NoC (system network on chip) 514 is a network that performs data transfer on the system side using a network protocol, and the network is configured on a chip. The processor 511, the memory controller 512, and the image processor 513 are connected to the system NoC 54 and can transfer data using a network protocol.

  The bridge 515 is a bridge that performs packet conversion between the DMA_NoC (DMA network on chip) 516 and the system NoC 514 and connects the two NoCs.

  The DMA_NoC 516 is a network that performs data transfer on the DMA side using a network protocol, and the network is configured on a chip.

  The plurality of head control units 517 -N includes a DMA controller 5171 and is connected to the DMA_NoC 516. Data transfer is possible using a network protocol. Each head control unit 517 -N is connected to a corresponding head 41.

  By adopting a data transmission method as described later using such a configuration, print data including pixel data and the like is transferred from a buffer configured in the external memory 60 in response to a data transfer request from the head 41 side. .

  FIG. 9 is a block diagram for explaining the operation of the bridge 515 in the present embodiment. In FIG. 9, the configuration concept of the bridge 515 and the DMA_NoC 516 is shown in order to explain the operation of the bridge 515. Hereinafter, functions of the bridge 515 and the DMA_NoC 516 will be described with reference to FIG.

  The DMA_NoC 516 includes one buffer 5162 connected to the bridge 515, a plurality of buffers 5164 connected to the head control unit 517, and an arbiter 5163 that arbitrates data transfer of the plurality of buffers 6164. Since the number of buffers 5164 conforms to the number of head control units 517, N buffers are included in the DMA_NoC 516, but only four are shown here for convenience of explanation. Here, the number of buffers 5162 connected to the bridge 515 is one, but the number is not limited to this as long as the number is less than the number of DMAs 5171.

  In FIG. 9, each buffer is shown in a rectangular shape, and a hatched circle represents data. Therefore, when the rectangle is blank, the buffer is empty, and when a circle is shown in the rectangle, it indicates that data exists.

  Having such a configuration, the DMA NoC 516 serves as an arbiter that performs arbitration in response to a request from the DMA 5171 of the head control unit 517. That is, arbitration is performed, and data in the plurality of buffers 5164 is transferred to the buffer 5162.

  The bridge 515 includes a conversion unit 5152 that performs protocol conversion, a buffer 5153 that temporarily stores a plurality of data, and a timer 5151 that can transfer the data in the buffer 5153 to the conversion unit 5152 at predetermined time intervals. . Data is sequentially sent from the buffer 5162 of the DMA_NoC 516 to the buffer 5153. The timer 5151 sends the data in the buffer 5153 to the conversion unit 5152 every set time.

  The conversion unit 5152 has a function of converting the protocol, format, data width, frequency, address, and the like into a format corresponding to the system No. C514.

  Having such a configuration, the bridge 516 changes the number of address bits and various IDs, changes the number of bursts, changes the data width, and changes the bus cycle. Furthermore, the request interval is controlled using a timer.

  Both DMA_NoC 516 and system NoC 514 are on-chip networks that perform data transfer using packets. However, these need not be NoCs having the same bandwidth. Further, in order to save resources (the number of gates and the number of wirings), the DMA_NoC 516 can be configured with a smaller band. A bridge 515 exists to connect these two NoCs.

  FIG. 10 is an explanatory diagram of a data conversion example of the bridge 516 in the present embodiment. In the example shown here, it is assumed that the DMA side has a 32-bit bus and the system side has a 64-bit bus. Considering an increase in the number of masters (DMAs) on the DMA side, conversion is performed so that the device ID on the DMA side is not taken out to the system side. For this purpose, the bridge 516 accesses the external memory 60 using its own ID like a proxy server.

  First, it is assumed that a packet from DMA No. 20 that has won arbitration in DMA NoC 516 is sent with the destination as a bridge 516. As can be seen from FIG. 10, Com is a command, DID is a destination ID, SID is a sender ID, BL is a burst length, and Adr is an address (32-bit length here).

  The bridge 516 converts the transmitted packet into a system No. C514 packet. As described above, since the DMA side bus length is 32 bits and the system side bus length is 64 bits, the burst length is converted. The destination ID is also converted into the destination ID in the system No. C514. In addition, the sender ID is also replaced with the ID of the bridge 516 that is the caller. The address length is also converted from a 32-bit length to a 40-bit length.

  The packet converted in this way is transmitted to the system NoC 514. The system NoC 514 accesses the external memory 60 via the memory controller 512 according to the converted packet.

  The memory controller 512 returns a response packet to the bridge 56. Data for the request is added to the response packet. The bridge 516 converts the received response packet into a DMA NoC 516 packet. At this time, the burst length of 4 times with 64 bits is converted into the burst length of 8 times with 32 bits. At this time, the destination ID is also changed. In this way, 32-bit data is sent to the destination DMA 20 as data for 8 cycles.

  FIG. 11 is a transaction chart in the present embodiment. FIG. 11 shows DMA # 1 as node 1 and DMA3 as node 3 among a plurality of notes (these are the head control units 517-1 to 517-3 in FIG. 9, respectively). It corresponds to this DMA). In addition, DMA_NoC 516 for arbitrating these DMA controllers is shown. Further, an external memory 60, a memory controller 512 that controls reading / writing of the external memory, and a system No. C514 are shown. In addition, a bridge connecting the DMA side NoC and the system side NoC is shown.

  As described above, the bridge 515 has a timer function. The figure shows that the timer is reset and started when t = 0 and time is up when t = T.

  First, read requests are sent from a plurality of nodes to the DMA_NoC 516. The DMA_NoC 516 arbitrates a plurality of read requests and sends the read requests to the bridge 515 in the order determined by the arbitration. Since the bridge 515 has a buffer for temporarily storing the read request, each time the timer is reset, the buffer request is sequentially sent to the system NoC 514.

  In FIG. 11, as a result of the arbitration, DMA_NoC 516 has system NoC 514 in the order of node 1 read request Rdreq (# 1), node 3 read request Rdreq (# 3), and node 2 read request Rdreq (# 2). Allow read requests to.

  When the timer expires (t = T) and the timer is started again, the bridge converts the read request of node 1 temporarily stored in its own buffer into a packet of system No C 514, and converts the read request Rd req ′ (# 1) is sent to the system No. C514.

  The system No. C514 determines that the packet is to be transmitted to the memory controller 512 based on the transmitted packet. Then, the packet is sent to the memory controller 512.

  The memory controller 512 sends a read command to the external memory 60 based on the sent packet. When a read command is sent, read data Rddata (# 1) is returned to the memory controller 512 after the access latency has elapsed. The memory controller 512 converts the read data Rddata (# 1) into a packet corresponding to the system NoC 514 and sends it to the system NoC 514 as a read response packet Rdres' (# 1).

  The system No. 514 sends a read response packet Rdres ′ (# 1) to the bridge 515. The bridge 515 converts the read response packet Rered '(# 1) into a packet corresponding to the DMA_NoC 516. Then, the converted read response packet Rdres (# 1) is sent to the DMA_NoC 516.

  The DMA_NoC 516 refers to the destination ID and sends the converted read response packet Rdres (# 1) to the DMA # 1, which is the node 1. The DMA # 1 stores the data in the read response packet Reres (# 1) in a buffer.

  Although there is a restriction that only one unresolved request can be sent per node, this allows DMA # 1 to send the next read request. Therefore, the next read request is sent from the DMA # 1 to the bridge 515 via the DMA_NoC 516.

  In the bridge 515, when the timer expires, the above operation is processed in the order of the packet that has won the arbitration (here, the read request of the node 3 that has won the node 1 is processed). ).

  In this way, requests are sequentially processed at intervals of the set timer.

  FIG. 12 is a graph of unresolved requests in the present embodiment. Also in FIG. 12, the horizontal axis represents time, and the vertical axis represents the number of unresolved requests. Further, a deadline is provided as in the case of FIG.

  In this embodiment, all the DMA requests are collected in the bridge 515, and after arbitrating the bridge so that the unresolved number is 1 (outbounding 1), the ID is changed, and the bridge 515 for the system NoC is newly represented on behalf of many DMAs. Generate and issue a simple request. At this time, the timer 5151 is used to control not to issue more than a certain amount of transactions. For this reason, as shown in FIG. 12, the number of unresolved requests is always “1” at most. It can also be seen that the unresolved requests are distributed among the deadlines.

  This is because the embodiment as described above can avoid concentration of transactions in the system NoC and minimize the influence on the QoS requested by other masters of the system NoC. Transfer of pixel data for printing as shown in this embodiment is an operation that is known to be completely in the future. Specifically, it is possible to grasp which data should be sent by when. Therefore, it is desirable to distribute data transfer in this way.

  In the present embodiment, the bridge 515 also plays a proxy role. That is, since the bridge 515 separates the DMA_NoC 516, the DMA side can configure a NoC having a necessary and sufficient band with excellent wiring efficiency.

  Further, the bridge 515 performs ID conversion therein, so that it is possible to prevent the system NoC 514 arbitration and the ID management resource increase that accompany the increase in the number of IDs. Moreover, even if the number of DMAs varies, there is an advantage that the system NoC 514 is not affected.

  FIG. 13 is a transaction chart in the reference example. In the reference example, the bridge does not have a timer. Therefore, when the bridge receives a read request from the DMA-side NoC, the bridge sequentially sends the converted read requests to the system-side NoC. For this reason, in the system side NoC, read requests are sequentially sent to the memory controller, and the memory controller also sends data acquired from the external memory to the system side NoC one after another. For this reason, there is a possibility that data transfer is concentrated and it is difficult to resolve requests of other modules.

  On the other hand, in the above-described embodiment, when the bridge 515 receives a read request, the read request converted to the system No. C514 is not transmitted until the timer 5151 expires. Therefore, data transfer can be distributed as a result, and the system NoC 514 can execute transmission / reception of requests of other modules in real time, thereby improving QoS.

=== Other Embodiments ===
In the above-described embodiment, the printer 1 has been described as the liquid ejecting apparatus. However, the present invention is not limited to this, and other fluids other than ink (liquid, liquids in which functional material particles are dispersed, gel Such a fluid can also be embodied in a liquid ejection device that ejects or ejects the fluid. For example, color filter manufacturing apparatus, dyeing apparatus, fine processing apparatus, semiconductor manufacturing apparatus, surface processing apparatus, three-dimensional modeling machine, gas vaporizer, organic EL manufacturing apparatus (especially polymer EL manufacturing apparatus), display manufacturing apparatus, film formation You may apply the technique similar to the above-mentioned embodiment to the various apparatuses which applied inkjet technology, such as an apparatus and a DNA chip manufacturing apparatus. These methods and manufacturing methods are also within the scope of application.

  The above-described embodiments are for facilitating the understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof.

<About the head>
In the above-described embodiment, ink is ejected using a piezoelectric element. However, the method for discharging the liquid is not limited to this. For example, other methods such as a method of generating bubbles in the nozzle by heat may be used.

1 Inkjet printer,
20 paper transport units, 30 detector groups, 40 recording units, 41 heads,
50 controller, 511 processor, 512 memory controller,
513 image processor, 514 system NoC, 515 bridge,
516 DMA_NoC, 517 head control unit,
5171 DMA controller,
5162 buffer, 5164 buffer, 5163 arbiter,
5151 timer, 5152 conversion unit, 5153 buffer,
60 external memory, 70 drive signal generation unit,
110 computer

Claims (8)

In a liquid ejection apparatus that ejects liquid from the head according to data sent from the system,
A first data transmission path on the system side;
A second data transmission path on the head side;
A bridge that performs data conversion between the first data transmission path and the second data transmission path;
A memory controller connected to the first data transmission path;
A memory connected to the memory controller;
A plurality of head controllers connected to the second transmission line and provided with a direct memory access controller;
With
The bridge sends requests from the head controller that are smaller in number than the number of head controllers to the memory controller via the first transmission path at a predetermined time interval. Liquid ejecting device. The liquid ejection device according to claim 1,
The bridge sends a request from each head controller to the memory controller via the first transmission path at a predetermined time interval and sends one request at the predetermined time interval. A liquid ejection device. The liquid ejection device according to claim 1 or 2,
The liquid ejecting apparatus according to claim 1, wherein the bridge includes a timer that measures the predetermined time interval. A liquid ejection apparatus according to any one of claims 1 to 3,
The liquid ejecting apparatus according to claim 1, wherein the bridge includes a buffer for storing the request. A liquid ejection apparatus according to any one of claims 1 to 4, wherein
The liquid ejection apparatus according to claim 1, wherein a band of the second data transmission path is narrower than a band of the first transmission path. A liquid ejection apparatus according to any one of claims 1 to 5,
The liquid ejecting apparatus according to claim 1, wherein the bridge performs ID conversion of a direct memory access controller in the head controller inside the bridge. A liquid ejection apparatus according to any one of claims 1 to 6,
The system according to claim 1, wherein the system sends data in response to a request from the head controller. A liquid ejection apparatus according to any one of claims 1 to 7,
The liquid ejecting apparatus according to claim 1, wherein the data sent from the system side is data defining a dot size formed by ejecting the liquid.

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