JP2005050920A - Capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor provided with a low inductance and a large electrostatic capacity and having high reliability. <P>SOLUTION: A capacitor 10 is provided with a first inner electrode 3 and a second inner electrode 4 opposed by sandwiching a dielectric layer 2 on the inside of a laminate 1 formed by laminating a plurality of the dielectric layers 2, a plurality of first via conductors 5 connected to the first inner electrode 3, a first blank part 7 arranging a plurality of second via conductors 6 connected to the second inner electrode 4 having no conductor material between the first via conductor 5 and the second inner electrode 4, and a second blank part 8 having no conductor material between the second via conductor 6 and the first inner electrode 3. The first via conductor 5 and the second via conductor 6 are annularly arranged along the outer periphery of the laminate 1, and the first via conductor 5 and the second via conductor 6 are arranged proximately in such a manner that the first blank part 7 and the second blank part 8 are partly overlapped in the lamination direction of the laminate 1 are arranged proximately. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor such as a decoupling capacitor connected to a circuit that supplies power to an IC.
[0002]
[Prior art]
As a conventional capacitor, for example, as shown in FIG. 5, a first internal electrode 53 and a second internal electrode 54 facing each other with a dielectric layer 52 sandwiched inside a laminated body 51 in which a plurality of dielectric layers 52 are laminated. And a plurality of first via conductors 55 connected to the first internal electrode 53 and a plurality of second via conductors 56 connected to the second internal electrode 54 are known. Yes. Such a capacitor applies a predetermined voltage between the first internal electrode 53 and the second internal electrode 54 to form a predetermined capacitance in the dielectric layer disposed between the internal electrodes. The first via conductor 55 and the second via conductor 56 adjacent to each other function as a low-inductance capacitor 50 by canceling out the generated magnetic fluxes (see, for example, Patent Document 1).
[0003]
Further, in the conventional capacitor 50 described above, the first blank portion 57 where no conductor material exists between the first via conductor 55 and the second internal electrode 54 is provided between the second via conductor 56 and the first internal electrode 53. The second blank portion 58 is provided, and the first blank portion 57 and the second blank portion 58 are electrically insulated from each other by the first blank portion 57 and the second blank portion 58.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-185442
[Problems to be solved by the invention]
However, the above-described conventional capacitor 50 is located in a region where the first internal electrode 53 and the second internal electrode 54 exist between the first via conductor 55 and the second via conductor 56 in the thickness direction of the multilayer body 51. Distortion is concentrated, and cracks tend to occur starting from this region.
[0006]
That is, in the conventional capacitor 50, the first via conductor 55 and the second via conductor 56 are made of a metal material, and the thermal expansion / shrinkage is larger than that of a dielectric layer made of ceramic or the like. Between the second via conductor 56, the stress strain due to thermal expansion and contraction is concentrated. In addition, the conventional capacitor 50 described above includes a region where only the first internal electrode 53 exists in the thickness direction of the multilayer body 51 between the first via conductor 55 and the second via conductor 56, and There are a region where only the two internal electrodes 54 exist and a region where both the first internal electrode 53 and the second internal electrode 54 exist. Therefore, in the thickness direction of the multilayer body, the region where both the first internal electrode 53 and the second internal electrode 54 exist has a larger amount of thermal expansion and contraction than the other regions. Also between the electrode 53 and the second internal electrode 54, it is a region where stress strain is particularly concentrated.
[0007]
Further, in the above-described conventional capacitor, the first blank portion 57 and the second blank portion 58 reduce the capacitance formation region, which prevents the capacitance from being increased.
[0008]
The present invention has been devised in view of the above drawbacks, and an object thereof is to provide a highly reliable capacitor having a low inductance and a large capacitance.
[0009]
[Means for Solving the Problems]
The capacitor of the present invention is connected to the first internal electrode, the first internal electrode and the second internal electrode, which are opposed to each other with the dielectric layer sandwiched inside the multilayer body in which a plurality of dielectric layers are stacked. A plurality of first via conductors and a plurality of second via conductors connected to the second internal electrode are disposed, and a first conductor material is not present between the first via conductor and the second internal electrode. In the capacitor in which the blank portion is provided with a second blank portion in which no conductor material exists between the second via conductor and the first internal electrode, the first via conductor and the second via conductor are arranged along the outer periphery of the multilayer body. An adjacent first via conductor and second via conductor are arranged close to each other so that the first blank portion and the second blank portion are partially overlapped in the stacking direction of the multilayer body. It is characterized by.
[0010]
In the capacitor of the present invention, the first via conductor is connected to the first internal electrode at the outer peripheral portion of the first internal electrode, and the second via conductor is connected to the second internal electrode at the outer peripheral portion of the second internal electrode. It is characterized by being connected.
[0011]
Furthermore, the capacitor of the present invention is characterized in that each end of the first via conductor and the second via conductor is led out to the lower surface of the multilayer body, and an external terminal is provided in the lead-out portion. It is.
[0012]
In the capacitor according to the present invention, the first via conductor and the second via conductor are alternately arranged along the outer periphery of the multilayer body, and each of the two blank portions is arranged on both sides of the blank portion. Are disposed so as to partially overlap in the stacking direction of the stacked body.
[0013]
According to the present invention, by arranging the first via conductor and the second via conductor adjacent to each other so that the first blank portion and the second blank portion partially overlap in the stacking direction of the multilayer body, Between the first via conductor and the second via conductor, the region where the first internal electrode and the second internal electrode are present in the thickness direction of the multilayer body is reduced. It can be reduced.
[0014]
According to the invention, the first via conductor is connected to the first internal electrode at the outer peripheral portion of the first internal electrode, and the second via conductor is connected to the second internal electrode at the outer peripheral portion of the second internal electrode. By being connected, approximately half of the regions of the first blank portion and the second blank portion overlap the non-formation region of the first internal electrode and the second internal electrode, so the first internal electrode and the second internal electrode Therefore, it is possible to efficiently secure the area of the regions facing each other, and to increase the capacitance.
[0015]
Furthermore, according to the present invention, each end of the first via conductor and the second via conductor is led out to the lower surface of the multilayer body, and an external terminal is provided in the lead-out portion. Since it can be mounted on a substrate, it is not necessary to form a solder fillet, and the mounting area of the capacitor can be reduced.
[0016]
Furthermore, according to the present invention, the first via conductors and the second via conductors are alternately arranged along the outer periphery of the multilayer body, and two blanks arranged on both sides of each blank portion. By arranging the blank portion so as to partially overlap in the stacking direction of the stacked body, adjacent via conductors can more efficiently cancel generated magnetic fluxes to each other, thereby forming a low-inductance capacitor. it can.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
[0018]
1 is an external perspective view of a capacitor according to an embodiment of the present invention as viewed from below, FIG. 2 is a sectional view of the capacitor of FIG. 1, and FIG. 3 is a perspective view of the capacitor of FIG. Is a laminated body, 2 is a dielectric layer, 3 is a first internal electrode, 4 is a second internal electrode, 5 is a first via conductor, 6 is a second via conductor, 7 is a first blank, and 8 is a first 2 blank parts, 11 and 12 are external terminals.
[0019]
The capacitor shown in FIG. 1 is formed by laminating a plurality of rectangular dielectric layers 2 to form a substantially rectangular parallelepiped laminated body 1, and in each of the dielectric layers 2-2 within the laminated body 1. The first internal electrode 3 and the second internal electrode 4 are alternately disposed in a state of being partially opposed to each other.
[0020]
The dielectric layer 2 is formed to a thickness of 1 μm to 3 μm per layer by a dielectric material mainly composed of, for example, barium titanate, calcium titanate, strontium titanate, and the like. For example, the laminated body 1 is formed by laminating only 70 to 600 layers. Note that FIG. 2 shows an example in which the number of stacked dielectric layers 2 is five in order to simplify this embodiment.
[0021]
For example, when the dielectric layer 2 is made of a dielectric material mainly composed of barium titanate, an appropriate organic solvent, glass frit, organic binder, or the like is added to and mixed with the barium titanate powder. In addition, this is formed into a ceramic green sheet having a predetermined shape and thickness by a conventionally known doctor blade method or the like, and then a predetermined number of ceramic green sheets are obtained by a conventionally known green sheet laminating method or the like. By laminating and crimping only, a ceramic green sheet laminate is formed, and this is cut and separated into individual laminates corresponding to individual capacitors. Finally, the individual laminates, for example, from 1100 ° C. It is manufactured by firing at a temperature of 1400 ° C. In addition, the shrinkage rate accompanying baking of the ceramic green sheet used in this process is set to about 10% to 20%, for example.
[0022]
On the other hand, the first internal electrode 3 and the second internal electrode 4 interposed between the dielectric layers 2 are made of a conductive material mainly composed of a metal such as nickel, copper, nickel / copper, silver / palladium, for example, 0. is formed to a thickness of .5Myuemu～2.0Myuemu, opposing areas of both the internal electrodes, for example, when the area of the dielectric layers 2 is 3.3 mm ^2, is set to 2.7 mm 2 ～3.0Mm ² The
[0023]
The plurality of first internal electrodes 3 embedded in the multilayer body 1 are connected to the external terminals 11 on the bottom surface of the multilayer body via the plurality of first via conductors 5 embedded in the multilayer body 1. The plurality of second internal electrodes 4 are commonly connected to the external terminals 12 on the bottom surface of the multilayer body through the plurality of second via conductors 6 embedded in the multilayer body 1. When a predetermined electric field is applied between the first internal electrode 3 and the external terminal 12, the dielectric constant, thickness, facing area, and number of layers of the dielectric layer 2 located between the first internal electrode 3 and the second internal electrode 4 are increased. A corresponding predetermined capacitance is formed.
[0024]
When the first internal electrode 3 and the second internal electrode 4 are made of nickel / copper, for example, a conductor obtained by adding and mixing an appropriate organic solvent, glass frit, organic binder, etc. to nickel / copper powder. The paste is interposed between the ceramic green sheets by printing and applying the paste in a predetermined pattern on the main surface of each ceramic green sheet by a conventionally known screen printing method or the like before laminating the ceramic green sheets. When the green sheet laminate is fired, the first internal electrode 3 and the second internal electrode 4 are simultaneously fired.
[0025]
It should be noted that a dielectric material contained in the ceramic green sheet may be added and mixed separately in the above-described conductor paste.
[0026]
On the other hand, the first via conductor 5 and the second via conductor 6 described above are arranged in parallel to the stacking direction of the dielectric layer 2 so that the lower ends thereof extend to the lower surface of the stacked body 1. The conductive material similar to that of the first internal electrode 3 and the second internal electrode 4 described above is formed in a columnar shape with a diameter of 80 μm to 150 μm, for example.
[0027]
The first via conductor 5 and the second via conductor 6 described above are predetermined by laser irradiation, microdrilling, punching, or the like at a stage before firing with respect to a laminate formed by laminating a plurality of ceramic green sheets. Through-holes and printed and filled with conductive paste in these through-holes by screen printing or the like, and the filled conductive paste is simultaneously fired together with the internal electrodes 3 and 4 at the time of firing the ceramic green sheet. It is formed by doing.
[0028]
Further, the first blank portion 7 in which no conductor material exists between the first via conductor and the second internal electrode, and the second blank portion 8 in which no conductor material exists between the second via conductor and the first internal electrode. Are provided, and the first internal electrode 3 and the second internal electrode 4 are electrically insulated by the first blank portion 7 and the second blank portion 8.
[0029]
In the capacitor according to the present embodiment, the first via conductor 5 and the second via conductor 6 are annularly arranged along the outer periphery of the multilayer body 1, and as shown in FIG. 3, the first via conductor 5 is the first via conductor 5. The outer periphery of the internal electrode 3 is connected to the first internal electrode 3, and the second via conductor 6 is connected to the second internal electrode 4 at the outer periphery of the second internal electrode 4. Since almost half of the region of the second blank portion 8 overlaps with the non-formation region of the first internal electrode 3 and the second internal electrode 4, the area of the region where the first internal electrode 3 and the second internal electrode 4 face each other is reduced. It is ensured efficiently, and the capacitance can be further increased.
[0030]
On the other hand, in the capacitor of this embodiment, adjacent first via conductor 5 and second via conductor 6 are close to each other so that the first blank portion 7 and the second blank portion 8 partially overlap in the stacking direction of the multilayer body 1. By arranging, the area where the first internal electrode 3 and the second internal electrode 4 are present in the thickness direction of the multilayer body 1 is reduced between the first via conductor 5 and the second via conductor 6. It becomes difficult for the strain to concentrate, and the generation of cracks can be reduced. In particular, in the present embodiment, the first blank portion 7 and the second blank portion 8 are overlapped in the stacking direction of the multilayer body 1 on the straight line of the first via conductor 5 and the second via conductor 6. , To reduce distortion.
[0031]
In addition, it is preferable that the first internal electrode 3 and the second internal electrode 4 are arranged so as not to overlap in a region where the first via conductor 5 and the second via conductor 6 are opposed to each other.
[0032]
The first via conductors 7 and the second via conductors 8 are alternately arranged along the outer periphery of the multilayer body 1, and two blank portions arranged on both sides of each blank portion are laminated. Since the via conductors are arranged so as to partially overlap each other in the stacking direction of the body 1 and the generated magnetic fluxes cancel each other efficiently, a capacitor having a lower inductance can be obtained.
[0033]
In addition, the external terminals 11 and 12 provided on the lower surface of the laminate 1 described above are connected to connection pads of the wiring board via a conductive adhesive such as solder when the capacitor is mounted on the wiring board such as a mother board. It functions as a terminal for external connection that is electrically connected. One end of each of the first via conductor and the second via conductor is led to the lower surface of the multilayer body on the lower surface of the multilayer body 1, and the lead-out portion has good solder wettability such as nickel or gold. It is formed by depositing an appropriate metal to a predetermined thickness by a conventionally known electrolytic plating method or the like.
[0034]
As described above, the capacitor 10 according to this embodiment can be mounted on the substrate by bump connection, so that it is not necessary to form a solder fillet, and the mounting area of the capacitor can be reduced.
[0035]
Thus, the above-described capacitor is used as a decoupling capacitor connected to a circuit that supplies power to an IC or the like, and has a low inductance and a large capacitance, thereby responding to a rapid power supply of the IC or the like. The capacitor functions as a highly reliable capacitor even during repeated thermal expansion due to heat generated by the IC or the like.
[0036]
The present invention is not limited to the above-described embodiments, and various changes and improvements can be made without departing from the scope of the present invention.
[0037]
For example, in the above-described embodiment, the stacked body is a rectangular parallelepiped, but may be a cylinder. Even in this case, the first via conductor and the second via conductor can be annularly arranged along the outer periphery of the multilayer body.
[0038]
Further, in the above-described embodiment, the case where one capacitor is manufactured alone has been described as an example, but instead of this, a so-called 'multiple picking' technique is adopted to cut out from a large-sized laminate. It goes without saying that a plurality of capacitors may be obtained simultaneously by firing a plurality of individual pieces.
[0039]
【The invention's effect】
According to the present invention, by arranging the first via conductor and the second via conductor adjacent to each other so that the first blank portion and the second blank portion partially overlap in the stacking direction of the multilayer body, Between the first via conductor and the second via conductor, the region where the first internal electrode and the second internal electrode are present in the thickness direction of the multilayer body is reduced. It can be reduced.
[0040]
According to the invention, the first via conductor is connected to the first internal electrode at the outer peripheral portion of the first internal electrode, and the second via conductor is connected to the second internal electrode at the outer peripheral portion of the second internal electrode. By being connected, approximately half of the regions of the first blank portion and the second blank portion overlap the non-formation region of the first internal electrode and the second internal electrode, so the first internal electrode and the second internal electrode Therefore, it is possible to efficiently secure the area of the regions facing each other, and to increase the capacitance.
[0041]
Furthermore, according to the present invention, each end of the first via conductor and the second via conductor is led out to the lower surface of the multilayer body, and an external terminal is provided in the lead-out portion. Since it can be mounted on a substrate, it is not necessary to form a solder fillet, and the mounting area of the capacitor can be reduced.
[0042]
Furthermore, according to the present invention, the first via conductors and the second via conductors are alternately arranged along the outer periphery of the multilayer body, and two blanks arranged on both sides of each blank portion. By arranging the blank portion so as to partially overlap in the stacking direction of the stacked body, adjacent via conductors can more efficiently cancel generated magnetic fluxes to each other, thereby forming a low-inductance capacitor. it can.
[Brief description of the drawings]
FIG. 1 is an external perspective view from below of a capacitor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the capacitor of FIG.
FIG. 3 is a perspective view of the capacitor of FIG. 1 as viewed from above.
FIG. 4 is a cross-sectional view of a conventional capacitor.
FIG. 5 is a perspective view of a conventional capacitor as viewed from above.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Laminated body 2 ... Dielectric layer 3 ... 1st internal electrode 4 ... 2nd internal electrode 5 ... 1st via conductor 6 ... 2nd via conductor 7 ... 1st 1 blank part 8 ... second blank part 10 ... capacitors 11, 12 ... external terminals

Claims (4)

A first internal electrode and a second internal electrode facing each other with the dielectric layer interposed therebetween, and a plurality of first vias connected to the first internal electrode, in a stacked body in which a plurality of dielectric layers are stacked. A conductor and a plurality of second via conductors connected to the second internal electrode are disposed, and a first blank portion in which no conductive material exists between the first via conductor and the second internal electrode In a capacitor in which a second blank portion having no conductor material is provided between the via conductor and the first internal electrode,
The first via conductor and the second via conductor are annularly arranged along the outer periphery of the multilayer body, and the first blank portion and the second blank portion partially overlap in the stacking direction of the multilayer body. Thus, the capacitor | condenser which adjoined and arrange | positioned the adjacent 1st via conductor and 2nd via conductor. The first via conductor is connected to the first internal electrode at an outer peripheral portion of the first internal electrode, and the second via conductor is connected to the second internal electrode at an outer peripheral portion of the second internal electrode. The capacitor according to claim 1. The one end of each of the first via conductor and the second via conductor is led out to a lower surface of the multilayer body, and an external terminal is provided in the lead-out portion. The capacitor described. The first via conductors and the second via conductors are alternately arranged along the outer periphery of the multilayer body, and two blank portions arranged on both sides of each blank portion are the multilayer body. The capacitor according to claim 1, wherein the capacitor is disposed so as to partially overlap in the stacking direction.

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