JP2007123505A - Stacked capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked capacitor having low equivalent serial inductance and high reliability. <P>SOLUTION: In the stacked capacitor 10, a plurality first leading-out portions 5 whose number is 1/2 of the number of first terminal electrodes 7 are led and connected every one of an arrangement of the first terminal electrodes 7 around a laminate 1 so that they are not overlapped with one another in the laminate direction from first internal electrodes 3 opposite with a dielectric layer 2 interposed, and a plurality of second leading-out portions 6 whose number is 1/2 of the number of second terminal electrodes 8 are led and connected every one of an arrangement of the second terminal electrodes 8 around the laminate 1 so that they are not overlapped with one another in the laminate direction from second internal electrodes 4 opposite with the dielectric layer 2 interposed. Since this configuration prevents the narrowing of an area between adjacent leading portions, interlayer peeling hardly occurs, the shortest path of currents intputted and outputted into and from the leading-out portions is ensured, and thus, equivalent serial inductance can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multilayer capacitor suitably used in a decoupling circuit for stabilizing a power supply voltage at a power supply terminal of an IC.

  Conventionally, multilayer capacitors have been used favorably in decoupling circuits that connect to the power supply terminals of ICs and stabilize the power by charging or discharging when sudden fluctuations occur in the power supplied to the power supply terminals. Yes.

  As such a conventional multilayer capacitor, for example, a plurality of first internal electrodes and a plurality of first internal electrodes arranged alternately to be opposed to each other with a dielectric layer sandwiched in a multilayer body in which a plurality of dielectric layers are laminated. (2) A plurality of first lead portions and second lead portions are drawn out from the internal electrode at a plurality of locations around the laminate, and the first lead portions and the second lead portions positioned above and below in the stacking direction are electrically connected to each other. A device in which a first terminal electrode and a second terminal electrode are formed in the stacking direction around the stacked body while being connected is known (see, for example, Patent Document 1).

  The above-mentioned conventional multilayer capacitor is characterized in that a plurality of lead portions from each internal electrode are provided at a plurality of locations. With this configuration, there are a plurality of current paths flowing in one internal electrode. Since the current path is short, the equivalent series inductance of the entire multilayer capacitor can be reduced.

  Therefore, the conventional multilayer capacitor is a capacitor having a relatively high resonance frequency due to series resonance between the total capacitance obtained between the first terminal electrode and the second terminal electrode and the equivalent series inductance. . Since the effective frequency band with low impedance that can be charged and discharged is obtained near this resonance frequency, the conventional multilayer capacitor functions on the high frequency side of the entire effective frequency band of the decoupling circuit. It can be used as a capacitor.

The conventional multilayer capacitor flows to the first terminal electrode when the plurality of first terminal electrodes and the plurality of second terminal electrodes are alternately arranged around the multilayer body in a plan view. Since the direction of the current and the direction of the current flowing through the second terminal electrode are opposite to each other, the magnetic flux generated between the adjacent first terminal electrode and the second terminal electrode is weakened. The inductance can be made lower.
Special Table 2002-508114

  However, when trying to reduce the size of the conventional multilayer capacitor, a plurality of lead portions are arranged with high density, so that the area where the dielectric layers are joined to each other between adjacent lead portions becomes small. Since the bonding force between the dielectric layers is reduced and delamination is likely to occur, there is a problem that reliability is lowered.

  Further, when the number of lead portions is reduced to reduce the number of terminal electrodes in order to prevent delamination, the equivalent series inductance cannot be reduced so much.

  The present invention has been devised in view of the problems in the conventional multilayer capacitor as described above, and an object thereof is to provide a multilayer capacitor having a low equivalent series inductance and high reliability.

  The multilayer capacitor according to the present invention includes a multilayer body formed by laminating a plurality of dielectric layers, and a plurality of first internal electrodes arranged alternately so as to face each other with the dielectric layer sandwiched between the multilayer bodies. And a plurality of second internal electrodes, and a plurality of first extraction portions and a plurality of second extractions drawn from the first internal electrode and the second internal electrode to the periphery of the laminate at two or more locations, respectively. 4 parts or more, which are formed in the stacking direction around the stack and the stack, and electrically connect the first lead-out parts and the second lead-out parts positioned above and below in the stacking direction. In a multilayer capacitor comprising a plurality of first terminal electrodes and a plurality of second terminal electrodes arranged alternately at even locations and around the multilayer body, the plurality of first lead portions are the first 1/2 of the number of terminal electrodes Connected by being drawn out from the first internal electrodes facing each other across the dielectric layer so as not to overlap each other in the stacking direction with respect to every other row of the first terminal electrodes around the stack. The plurality of second lead portions are half the number of the second terminal electrodes, and overlap each other in the stacking direction from the second internal electrodes facing each other across the dielectric layer. In order to avoid this, it is drawn out and connected to every other row of the second terminal electrodes around the laminate.

  According to the multilayer capacitor of the present invention, the number of the plurality of first lead portions is ½ of the number of the first terminal electrodes, and the number of the plurality of second lead portions is 1 / number of the number of the second lead portions. 2 prevents the area between adjacent lead portions from becoming narrower, making it difficult for delamination to occur, and stacking from the first internal electrodes facing each other across the dielectric layer so that they do not overlap each other in the stacking direction. By being drawn out and connected to every other row of the first terminal electrodes around the body, the shortest current path among the currents input to and output from the first lead portion drawn from the first internal electrode is One is ensured for each of the two second internal electrodes positioned above and below in the stacking direction, and the shortest current path among the input and output currents is also secured for the second lead portion. Therefore, according to the multilayer capacitor of the present invention, a multilayer capacitor with high reliability and low equivalent series inductance can be obtained.

  Hereinafter, the multilayer capacitor of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is an external perspective view showing an example of an embodiment of the multilayer capacitor of the present invention, and FIGS. 2A to 2E are diagrams in which the first internal electrode or the second internal electrode of the multilayer capacitor of FIG. 1 is formed. FIG. 5 is a plan view of a part of the dielectric layers arranged in order from the top in the stacking direction and viewed from above. The multilayer capacitor of the present invention shown in these drawings includes a multilayer body 1, a plurality of first internal electrodes 3 and a second internal electrode 4, a plurality of first lead portions 5 and a second lead portion 6, and a plurality of first terminals. An electrode 7 and a second terminal electrode 8 are provided.

  The laminate 1 is a rectangular parallelepiped dielectric block configured by laminating, for example, 70 to 600 layers of a plurality of rectangular dielectric layers 2 having a thickness of 1 μm to 5 μm per layer. As a material of the dielectric layer 2, for example, a dielectric material mainly composed of barium titanate, calcium titanate, strontium titanate or the like is used.

  The first internal electrode 3 and the second internal electrode 4 are conductor patterns which are formed to have a thickness of 0.5 μm to 2 μm and are alternately arranged so as to face each other with the dielectric layer 2 sandwiched inside the multilayer body 1. is there. As the material of the first internal electrode 3 and the second internal electrode 4, for example, a conductive material whose main component is a metal such as nickel, copper, nickel-copper, silver-palladium is used.

  The first lead portion 5 and the second lead portion 6 are conductor patterns drawn from the first internal electrode 3 and the second internal electrode 4 to the periphery of the multilayer body 1 at two or more locations, respectively. Are electrically connected to a plurality of first terminal electrodes 7 and second terminal electrodes 8 formed around each of the first terminal electrode 7 and the second terminal electrode 8, respectively.

  The first terminal electrode 7 and the second terminal electrode 8 have a thickness of 2 μm to 70 μm and are formed in a strip shape around the laminated body 1 in the laminating direction. It is a thick film conductor pattern arranged at an even number of four or more places around the laminate 1 that electrically connects the two lead portions 6 to each other. As the material of the first terminal electrode 7 and the second terminal electrode 8, for example, a conductor material mainly composed of a metal such as nickel, copper, silver, or palladium is used. Note that the surfaces of the first terminal electrode 7 and the second terminal electrode 8 are made of tin, in order to improve the connection with the electrode pads of the external circuit board. The corrosion-resistant metal film is preferably formed of a conductor material such as solder or gold.

  In the multilayer capacitor 10 having such a configuration, when a predetermined potential difference is generated between the first terminal electrode 7 and the second terminal electrode 8, the first internal electrode passes through the first lead portion 5 from the first terminal electrode 7. 3, a current having the opposite polarity flows from the second terminal electrode 8 through the second lead portion 6 to the second internal electrode 4, and the first internal electrode 3 and the second internal electrode 4. A predetermined capacitance can be obtained between the two. Further, in the multilayer capacitor of the present invention, the first lead portion 5 and the second lead portion 6 are provided at even numbers of four or more places, respectively. Since there are a plurality of flowing current paths and the respective current paths are short, the equivalent series inductance of the entire multilayer capacitor can be reduced. For this reason, the multilayer capacitor of the present invention includes a multilayer capacitor having a relatively high resonance frequency due to series resonance between the total capacitance obtained between the first terminal electrode 7 and the second terminal electrode 8 and the equivalent series inductance. It has become. Since the effective frequency band with low impedance that can be charged and discharged is obtained near this resonance frequency, the multilayer capacitor 10 of the present invention functions on the high frequency side of the total effective frequency band of the decoupling circuit. It can be used as a capacitor. In addition, the plurality of first terminal electrodes 7 and the plurality of second terminal electrodes 8 are alternately arranged around the multilayer body 1 when the multilayer body 1 is viewed in plan, and the current flowing through the first terminal electrode 7 and Since the direction of the current flowing through the second terminal electrode 8 is generally reverse, the magnetic flux generated between the first terminal electrode 7 and the second terminal electrode 8 adjacent to each other is weakened, and the equivalent series inductance is further increased. It is low.

  In the multilayer capacitor 10 of the present invention, the number of the plurality of first lead portions is ½ of the number of the first terminal electrodes, and the number of the plurality of second lead portions is one of the number of the second lead portions. Since the area between the adjacent drawn portions is not narrowed by setting to / 2, delamination is hardly caused.

  Further, the plurality of first lead portions 5 are arranged for every other arrangement of the first terminal electrodes around the laminated body so as not to overlap each other in the laminating direction from the first internal electrodes facing each other across the dielectric layer. By being drawn out and connected, the shortest current path among the currents input to and output from the first lead portion drawn from the first internal electrode is connected to each of the two second internal electrodes located above and below in the stacking direction. One by one is secured. Further, the plurality of second lead portions 6 are one of the arrangements of the second terminal electrodes 8 around the multilayer body 1 so as not to overlap each other from the second internal electrodes 4 facing each other across the dielectric layer 2. The shortest current path among the currents input to and output from the first lead part drawn from the first internal electrode by being drawn and connected to every other is the two second internal parts located above and below in the stacking direction. One is reserved for each electrode. Therefore, according to the multilayer capacitor of the present invention, a multilayer capacitor with high reliability and low equivalent series inductance can be obtained.

  For example, in the example of the embodiment of the multilayer capacitor 10 of the present invention, when a current is input to the two first lead portions 5 drawn from the first internal electrode 3 on the dielectric layer 2 in FIG. Current paths A, B, C, and D are the shortest of the current paths generated in. At this time, in the second internal electrode 4 of the dielectric layer 2 in FIG. 2A located above the dielectric layer 2 in FIG. 2B, current paths A ′ and D corresponding to the current paths A and D are obtained. 'Is generated, and a current is output from the second extraction unit 6. Further, in the second internal electrode 4 of the dielectric layer 2 in FIG. 2C located below the dielectric layer 2 in FIG. 2B, current paths B ′ and C ′ corresponding to the current paths B and C are shown. Is generated, and a current is output from the second extraction unit 6.

  Similarly, the shortest path among the current paths generated when current is input to the two first lead portions 5 drawn from the first internal electrode 3 on the dielectric layer 2 in FIG. Are current paths E, F, G, H. At this time, in the second internal electrode 4 of the dielectric layer 2 in FIG. 2C located above the dielectric layer 2 in FIG. 2D, current paths F ′ and G corresponding to the current paths F and G are shown. 'Is generated, and a current is output from the second extraction unit 6. Further, in the second internal electrode 4 of the dielectric layer 2 in FIG. 2E located below the dielectric layer 2 in FIG. 2D, current paths E ′ and H ′ corresponding to the current paths E and H are shown. Is generated, and a current is output from the second extraction unit 6.

  As described above, in the example of the embodiment described above, two current paths corresponding to the four shortest current paths generated in the first internal electrode 3 are respectively provided in the second internal electrodes 4 positioned above and below. It is supposed to occur one by one.

  The multilayer capacitor 10 of the present invention is manufactured by, for example, the following method.

  First, a dielectric green sheet corresponding to the dielectric layer 2 is produced. For example, the dielectric green sheet is prepared by adding and mixing a suitable organic solvent, glass frit, organic binder, plasticizer, etc. to an inorganic powder mainly composed of barium titanate. It is formed in a predetermined shape and a predetermined thickness by a blade method or the like.

  For example, using a conductive paste prepared by adding and mixing an appropriate organic solvent, organic binder, etc. to nickel powder on the prepared dielectric green sheet, the first internal electrode 3 and the first internal electrode 3 and the first A conductor paste pattern corresponding to the lead portion 5 and a conductor paste pattern corresponding to the second internal electrode 4 and the second lead portion 6 are formed. The conductor paste pattern formed in the method for manufacturing the multilayer capacitor 10 of the present invention corresponds to that corresponding to FIG. 2 (b) and the one shown in FIG. There are two types of corresponding ones, and there are two types of ones corresponding to FIG. 2A and those corresponding to FIG. In the production of the multilayer capacitor of the present invention, a dielectric green sheet in which a plurality of dielectric layer regions corresponding to the dielectric layer 2 are arranged vertically and horizontally is used.

  Next, a plurality of ceramic green sheets are formed by laminating and pressing a predetermined number of the dielectric green sheets on which the respective conductor paste patterns are formed, so that the first internal electrodes 3 and the second internal electrodes 4 are alternated. A laminated sheet is formed, and this is cut and separated along the boundary line of each dielectric layer region to produce a plurality of individual laminated sheets. The individual laminated sheets are, for example, 1100 ° C. to 1400 ° C. The laminated body 1 is manufactured by firing at a temperature of, and the conductor paste is applied around the laminated body 1 in the form of a strip in the laminating direction by a screen printing method or the like. By forming the second terminal electrode 8, the multilayer capacitor 10 of the present invention is manufactured.

  The present invention is not limited to the embodiments described above, and various changes and improvements can be made without departing from the scope of the present invention.

  For example, in the example of the embodiment described above, the laminate 1 has a rectangular shape, but may have a trapezoidal shape, a rhombus shape, a triangular shape, other polygonal shapes, or a circular shape.

  Moreover, in the example of embodiment mentioned above, although the structure in which the 1st terminal electrode 7 and the 2nd terminal electrode 8 were each formed in four places is shown, it may be formed in the even number place of four places or more, respectively. It is possible to apply.

  For example, FIG. 3 is an external perspective view showing another example of the embodiment of the multilayer capacitor of the present invention, and FIGS. 4A to 4E are the first internal electrode or the second internal electrode of the multilayer capacitor of FIG. It is the top view which arranged a part dielectric layer in which the electrode was formed in order from the lamination direction, and was seen from the upper part. In addition, the description which overlaps using the same code | symbol to the location similar to FIG. 1 and FIG. 2 is abbreviate | omitted. In the multilayer capacitor 30, the first terminal electrode 7 and the second terminal electrode 8 are formed at six locations in FIG. 3, respectively. In FIGS. 4 (a) to 4 (e), the first internal electrode 3 and the second internal electrode The first drawing portion 5 and the second drawing portion 6 drawn from 4 are formed at three locations, respectively.

  In the multilayer capacitor 30 shown in FIG. 3 and FIGS. 4A to 4E, current is supplied to the two first lead portions 5 drawn from the first internal electrode 3 on the dielectric layer 2 in FIG. 4B. Current paths I, J, K, L, M, and N are the shortest of the current paths generated when input. At this time, in the second internal electrode 4 of the dielectric layer 2 in FIG. 4A located above the dielectric layer 2 in FIG. 4B, the current path I ′ corresponding to the current paths I, L, and M , L ′, M ′ are generated, and a current is output from the second extraction unit 6. Further, in the second internal electrode 4 of the dielectric layer 2 in FIG. 4C located below the dielectric layer 2 in FIG. 4B, current paths J ′, corresponding to the current paths J, K, N are shown. K ′ and N ′ are generated, and a current is output from the second extraction unit 6.

  Similarly, the shortest path among the current paths generated when current is input to the two first lead portions 5 drawn from the first internal electrode 3 on the dielectric layer 2 in FIG. Are current paths O, P, Q, R, S, T. At this time, in the second internal electrode 4 of the dielectric layer 2 in FIG. 4C located above the dielectric layer 2 in FIG. 4D, the current path P ′ corresponding to the current paths P, Q, and T , Q ′, T ′ are generated, and a current is output from the second extraction unit 6. Further, in the second internal electrode 4 of the dielectric layer 2 in FIG. 2 (e) located below the dielectric layer 2 in FIG. 2 (d), current paths O ′, R ′ and S ′ are generated, and a current is output from the second extraction unit 6.

  As described above, in the example of the embodiment described above, the current paths corresponding to the six shortest current paths generated in the first internal electrode 3 are three in each of the second internal electrodes 4 positioned above and below. It is supposed to occur.

  FIG. 5 is an external perspective view showing still another example of the embodiment of the multilayer capacitor according to the present invention. FIGS. 6A to 6E show the first internal electrode or the second electrode of the multilayer capacitor in FIG. It is the top view which arranged a part of dielectric layer in which the internal electrode was formed in order from the lamination direction, and was seen from the upper part. In addition, the description which overlaps using the same code | symbol to the location similar to FIG. 1 and FIG. 2 is abbreviate | omitted. In the multilayer capacitor 50, eight first terminal electrodes 7 and eight second terminal electrodes 8 are formed in FIG. 5 respectively. In FIGS. 6A to 6E, the first internal electrode 3 and the second internal electrode 8 are formed. Four first and second drawing portions 5 and 6 drawn from 4 are formed.

  In the multilayer capacitor 50 shown in FIG. 5 and FIGS. 6A to 6E, current is supplied to the two first lead portions 5 drawn from the first internal electrode 3 on the dielectric layer 2 in FIG. 6B. Current paths f, g, h, i, j, k, l, m are the shortest paths among the current paths generated when input. At this time, in the second internal electrode 4 of the dielectric layer 2 in FIG. 6A located above the dielectric layer 2 in FIG. 6B, current paths corresponding to the current paths f, i, j, m f ′, i ′, j ′, m ′ are generated, and a current is output from the second extraction unit 6. Further, in the second internal electrode 4 of the dielectric layer 2 in FIG. 6C located below the dielectric layer 2 in FIG. 6B, the current path g corresponding to the current paths g, h, k, l. ', H', k ', and l' are generated, and a current is output from the second extraction unit 6.

  Similarly, the shortest path among the current paths generated when current is input to the two first lead portions 5 drawn from the first internal electrode 3 on the dielectric layer 2 in FIG. 6D. Are current paths n, o, p, q, r, s, t, u. At this time, in the second internal electrode 4 of the dielectric layer 2 in FIG. 6C located above the dielectric layer 2 in FIG. 6D, current paths corresponding to the current paths o, p, s, and t. o ′, p ′, s ′, t ′ are generated, and a current is output from the second extraction unit 6. Further, in the second internal electrode 4 of the dielectric layer 2 in FIG. 6E located below the dielectric layer 2 in FIG. 6D, the current path n corresponding to the current paths n, q, r, u. ', Q', r ', u' are generated, and a current is output from the second extraction unit 6.

  As described above, in the example of the embodiment described above, the current paths corresponding to the eight shortest current paths generated in the first internal electrode 3 are four in each of the second internal electrodes 4 positioned above and below. It is supposed to occur.

  Specific examples of the multilayer capacitor of the present invention will be described.

  As samples 1, 2, and 3, multilayer capacitors of the present invention were produced. In these samples 1, 2, and 3, the shape of the laminate is a rectangular shape having a length of 2 mm and a width of 1.2 mm, and a plurality of first terminal electrodes and a plurality of second terminal electrodes are alternately formed around the periphery. A first internal electrode, a second internal electrode, and a plurality of first extraction portions and a plurality of second extraction portions that are extracted from the first internal electrode and the second internal electrode, respectively, are formed inside the laminate. As the material of the dielectric layer constituting the laminate, a material mainly composed of barium titanate is used, and as the material of the first internal electrode and the second internal electrode, a material mainly composed of nickel is used, and the first terminal electrode As the material for the second terminal electrode, a material mainly composed of copper was used. In addition, the plurality of first lead portions are arranged with respect to every other arrangement of the first terminal electrodes around the stacked body so as not to overlap each other in the stacking direction from the first internal electrodes facing each other across the dielectric layer. The plurality of second lead portions is ½ the number of the second terminal electrodes, and each of the plurality of second lead portions overlaps in the stacking direction from the second internal electrodes facing each other across the dielectric layer. In order to prevent this, it is assumed that every other row of the second terminal electrodes around the laminate is drawn out and connected.

  Sample 1 and sample 2 were in the shape of a rectangular parallelepiped with a laminate length of 2 mm and a width of 1.2 mm, and sample 3 was in the shape of a rectangular parallelepiped with a laminate length of 3.2 mm and a width of 1.6 mm. Further, the number of the first terminal electrodes and the second terminal electrodes is 4 for sample 1, 6 for sample 2, and 8 for sample 3, respectively. 2, Sample 2 is 3, Sample 3 is 4.

  Further, as samples 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13, conventional multilayer capacitors as comparative examples were fabricated. Samples 4 and 5 are conventional multilayer capacitors as comparative examples for sample 1, and samples 6, 7, 8, and 9 are conventional multilayer capacitors as comparative examples for sample 2. Samples 10, 11, 12, and 13 Is a conventional multilayer capacitor as a comparative example for the sample 3.

  In these conventional multilayer capacitors as comparative examples, the number of first lead portions and second lead portions is equal to the number of first terminal electrodes and the number of second terminal electrodes for samples 4, 6, and 10, respectively. Samples 5, 7, and 11 have 1/2 the number of first terminal electrodes and 1/2 the number of second terminal electrodes, respectively, and samples 8, 9, 12, and 13 have the number of first terminal electrodes, respectively. The number is one less than ½ of the number and one less than ½ of the number of second terminal electrodes.

  For Samples 9 and 13, as in Samples 1, 2 and 3, which are the multilayer capacitors of the present invention, a plurality of first lead portions are respectively formed in the stacking direction from the first internal electrodes facing each other across the dielectric layer. The plurality of second lead portions were drawn from the second internal electrodes facing each other across the dielectric layer so as not to overlap each other in the stacking direction.

Table 1 shows the measurement results of the delamination rate (parameter is 50) and inductance for each of Samples 1 to 13. Table 1 shows the reliability and characteristics of the multilayer capacitor. S / R is a plurality of first leads drawn from the first internal electrodes facing each other across the dielectric layer so as to overlap each other in the lamination direction. Or the presence or absence of a plurality of second lead portions drawn from the second internal electrodes facing each other across the dielectric layer so as to overlap each other in the stacking direction, and D / N is the rate of occurrence of delamination ( ESL represents the equivalent series inductance (unit: pH) of the multilayer capacitor.

  According to the results shown in Table 1, delamination does not occur in the multilayer capacitors of the present invention of Samples 1, 2, and 3 unlike the conventional multilayer capacitors of Samples 4, 6, and 10.

  In addition, the multilayer capacitors of the present invention of samples 1, 2, and 3 are first opposed to each other with a dielectric layer interposed therebetween, like the conventional multilayer capacitors of samples 5, 7, 8, 9, 11, 12, and 13. A plurality of first lead portions drawn out from the internal electrodes so as to overlap each other in the stacking direction, or a plurality of second leads drawn out so as to overlap each other in the stacking direction from the second internal electrodes facing each other across the dielectric layer The equivalent series inductance is low compared to the case where the part is present, and the value is equal to the number of terminal electrodes and lead parts as in the conventional multilayer capacitors of Samples 4, 6, and 10. The level was equivalent.

  As described above, according to the multilayer capacitor of the present invention, the number of the plurality of first lead portions is ½ of the number of the first terminal electrodes, and the number of the plurality of second lead portions is the number of the second lead portions. Since the area between adjacent lead portions is not reduced by reducing the number to 1/2, the delamination is less likely to occur, and the first internal electrodes facing each other across the dielectric layer do not overlap each other in the stacking direction. As described above, by being drawn out and connected to every other arrangement of the first terminal electrodes around the multilayer body, the shortest of the currents inputted to and outputted from the first lead part drawn from the first internal electrode One current path is ensured for each of the two second internal electrodes positioned above and below in the stacking direction, and the shortest current path among the input and output currents is also secured for the second lead portion in a reliable manner. Is high and equivalent series That can inductance is lower multilayer capacitor was confirmed.

It is an external appearance perspective view which shows an example of embodiment of the multilayer capacitor of this invention. (A)-(e) is the top view which arranged the one part dielectric layer in which the 1st internal electrode or 2nd internal electrode of the multilayer capacitor of FIG. 1 was formed in order from the lamination direction, and was seen from the upper direction. It is an external appearance perspective view which shows the other example of embodiment of the multilayer capacitor of this invention. (A)-(e) is the top view which arranged the one part dielectric layer in which the 1st internal electrode or 2nd internal electrode of the multilayer capacitor of FIG. 3 was formed in order from the lamination direction, and was seen from the upper direction. It is an external appearance perspective view which shows the further another example of embodiment of the multilayer capacitor of this invention. (A)-(e) is the top view which arranged the one part dielectric layer in which the 1st internal electrode or 2nd internal electrode of the multilayer capacitor of FIG. 5 was formed in order from the lamination direction, and was seen from the upper direction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Laminated body 2 ... Dielectric layer 3 ... 1st internal electrode 4 ... 2nd internal electrode 5 ... 1st extraction part 6 ... 2nd extraction part 7 ... 1st 1 terminal electrode 8 ... 2nd terminal electrode
10, 30, 50 ... multilayer capacitors

Claims (1)

A laminate formed by laminating a plurality of dielectric layers;
A plurality of first internal electrodes and a plurality of second internal electrodes alternately arranged so as to face each other across the dielectric layer in the laminated body;
A plurality of first lead portions and a plurality of second lead portions drawn from the first internal electrode and the second internal electrode to the periphery of the multilayer body at two or more locations, respectively;
Formed in the stacking direction around the laminate and electrically connecting the first lead portions and the second lead portions positioned above and below in the stack direction, respectively, at even four or more even locations. And a multilayer capacitor comprising a plurality of first terminal electrodes and a plurality of second terminal electrodes arranged alternately around the multilayer body,
The plurality of first lead portions are ½ of the number of the first terminal electrodes, and the first internal electrodes facing each other across the dielectric layer do not overlap each other in the stacking direction. Drawn out and connected to every other row of the first terminal electrodes around the laminate,
The plurality of second lead portions are ½ the number of the second terminal electrodes, and the second internal electrodes face each other across the dielectric layer so as not to overlap each other in the stacking direction. A multilayer capacitor characterized by being drawn out and connected to every other row of the second terminal electrodes around the multilayer body.

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