JP2005044889A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device by which a semiconductor device having excellent electrical characteristics can be manufactured by using a High-k film having good characteristics and combining the characteristics of the film with a realizable etching technique. <P>SOLUTION: The method of manufacturing the semiconductor device includes a step of forming an insulating film selected from among a group composed of an YAlO<SB>x</SB>film, GdAlO<SB>x</SB>film and DyAlO<SB>x</SB>film on a silicon substrate, a step of forming a gate electrode on the insulating film, and a step of wet-etching the insulating film by using a liquid chemical of 8-9 in pH. The liquid chemical can contain fluorine and amine. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a high dielectric constant insulating film.
[0002]
[Prior art]
2. Description of the Related Art In recent years, high integration in semiconductor integrated circuit devices has greatly advanced, and in a MOS (Metal Oxide Semiconductor) type semiconductor device, elements such as transistors and the like for achieving high integration have been miniaturized and improved in performance. Yes. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor.
[0003]
As a material constituting the gate insulating film, a silicon oxide film (SiO ₂ film) has been conventionally used. On the other hand, when the gate insulating film becomes thinner with the miniaturization of the gate electrode, the tunnel current generated by the carriers (electrons and holes) directly tunneling through the gate insulating film, that is, the gate leakage current increases. . For example, the thickness of the gate insulating film required for a 130 nm node device is about 2 nm for a SiO ₂ film, but this region is a region where a tunnel current starts to flow. Therefore, when the SiO ₂ film is used as the gate insulating film, the gate leakage current cannot be suppressed and the power consumption is increased.
[0004]
In view of this, research has been conducted in which a material having a higher dielectric constant is used as the gate insulating film instead of the SiO ₂ film.
[0005]
Conventionally, HfAlO _x films, HfSiO _x films, HfO ₂ films, and the like have been studied as high dielectric constant insulating films (hereinafter referred to as “High-k films”). However, these films require a SiO ₂ film having a film thickness of about 1 nm between the silicon substrate, and if such a film does not exist, the High-k film and the silicon during the heat treatment at a high temperature. There is a problem in that the characteristics as a gate insulating film deteriorate due to a reaction between the two. For this reason, when the HfAlO _x film, the HfSiO _x film, the HfO ₂ film, or the like is used as the high-k film, there is a limit to the reduction in the thickness of the gate insulating film.
[0006]
In contrast, La-based oxides such as Y, Gd, and Dy hardly react with silicon. Therefore, when a film made of these oxides is used as a high-k film, a gate insulating film having favorable characteristics can be formed directly on the silicon substrate.
[0007]
By the way, when putting a High-k film into practical use, a processing technique capable of realizing good characteristics as well as good characteristics is important.
[0008]
[Problems to be solved by the invention]
FIG. 5 is a cross-sectional view showing a manufacturing process of a field effect transistor according to a conventional method when a high-k film is used as a gate insulating film.
[0009]
After element isolation regions 502 and 503 are formed on the silicon substrate 501, an SiO ₂ film 504 is formed by a thermal oxidation method. Next, a high-k film 505, a polycrystalline silicon film 506 as a gate electrode, and a SiO ₂ film 507 as a mask material are grown in order. Thereafter, an antireflection film 508 is formed for the purpose of improving the dimensional uniformity of the gate electrode, and then a resist pattern 509 is formed using a photolithography method (FIG. 5A).
[0010]
Next, the antireflection film 508 and the SiO ₂ film 507 are dry-etched using the resist pattern 509 as a mask to form an SiO ₂ film pattern 510 (FIG. 5B).
[0011]
Next, the polycrystalline silicon film 506 is dry-etched using the SiO ₂ film pattern 510 as a mask to form a polycrystalline silicon film pattern 511 (FIG. 5C).
[0012]
Thereafter, the high-k film 505 and the SiO ₂ film 504 are etched to complete the gate electrode. At this time, however, there are the following problems.
[0013]
In the structure of FIG. 5B, when the high-k film 505 does not exist, the SiO ₂ film 504 is exposed because the selection ratio between the polycrystalline silicon film 506 and the underlying SiO ₂ film 504 is large. At this point, the etching stops. Then, the gate electrode can be formed by removing the SiO ₂ film 504 by wet etching using dilute hydrofluoric acid or the like.
[0014]
On the other hand, when there is the High-k film 505, after forming the polycrystalline silicon film pattern 511 as described above, the High-k film is formed using an etching gas such as BCl ₃ , HBr, O ₂ or fluorocarbon. 505 dry etching is performed.
[0015]
However, at this time, since the selection ratio between the High-k film 505 and the underlying SiO ₂ film 504 is small, there is a problem that the SiO ₂ film 504 and further the silicon substrate 501 under the SiO ₂ film 504 are etched. (FIG. 5D). This hinders the formation of the extension region and the source / drain regions.
[0016]
In order to avoid damage to the silicon substrate, it is preferable to reduce the amount of overetching when etching the High-k film. However, in this case, the cross-sectional shape of the High-k film is tapered, that is, the High-k film is processed to protrude from the polycrystalline silicon film pattern as viewed from above. For this reason, there is a problem that the electrical characteristics of the semiconductor device deteriorate due to the influence of the electric field generated by the protruding portion of the High-k film.
[0017]
In the manufacturing process of the semiconductor device, a relatively high temperature heat treatment is applied to the High-k film. However, there is a difference in how heat is transmitted between the high-k film formed on the silicon substrate and the high-k film formed on the element isolation region. In addition, there is a problem that a difference occurs in etching of the High-k film due to this.
[0018]
The present invention has been made in view of such problems. That is, an object of the present invention is to provide a semiconductor device manufacturing method capable of etching a high-k film without damaging a silicon substrate.
[0019]
Another object of the present invention is to provide a method of manufacturing a semiconductor device having excellent electrical characteristics by using a high-k film having favorable characteristics and combining it with an etching technique capable of realizing the favorable characteristics. There is.
[0020]
Other objects and advantages of the present invention will become apparent from the following description.
[0021]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming any one insulating film selected from the group consisting of a YAlO _x film, a GdAlO _x film, and a DyAlO _x film on a silicon substrate, and on the insulating film. The method includes a step of forming a gate electrode and a step of wet etching the insulating film using a chemical solution having a pH of 8 to 9.
[0022]
The method for manufacturing a semiconductor device of the present invention is selected from the group consisting of a step of forming a SiO ₂ film on a silicon substrate and a YAlO _x film, a GdAlO _x film, and a DyAlO _x film on the SiO ₂ film. A step of forming any one insulating film, a step of forming a gate electrode on the insulating film, and a step of wet-etching the insulating film using a chemical solution having a pH of 8 to 9. To do.
[0023]
In the method for manufacturing a semiconductor device of the present invention, the chemical liquid may contain fluorine and an amine. In this case, the chemical solution can be an aqueous ammonium fluoride solution.
[0024]
In the method for manufacturing a semiconductor device of the present invention, the chemical solution can contain hydrogen peroxide.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
High-k film to which the present invention is directed, Y (yttrium) and Al YAlO an oxide of (aluminum) _x, Gd (gadolinium) for GdAlO _x and Dy (dysprosium), and Al is an oxide of and Al It is a film made of DyAlO _x which is an oxide. YAlO _x , GdAlO _x and DyAlO _x are promising materials in the future because they hardly react with silicon and have high thermal stability. In the present specification, the High-k film refers to an insulating film having a dielectric constant larger than that of the SiO ₂ film.
[0026]
In general, an etching solution used when a metal oxide film is used as a High-k film is a hydrofluoric acid chemical solution. However, since the solubility characteristics of Y, Gd, and Dy in an aqueous solution and the solubility characteristics of Al in an aqueous solution are greatly different from each other, conventionally, the YAlO _x film, the GdAlO _x film, and the DyAlO _x film are etched uniformly with good control. It was difficult.
[0027]
FIG. 1 shows the pH dependence of the solubility of Y and Al obtained based on the pH-potential curves of Y and Al. As can be seen, the solubility of Y decreases linearly with increasing pH. That is, the solubility in the acidic to neutral region is high, but the solubility is reduced in the basic region. On the other hand, Al has a minimum value at about pH 5, and the solubility in strong acidity and weak alkalinity shows a large value.
[0028]
Further, it has been found that the solubility of Gd and Dy also shows substantially the same pH dependence as Y.
[0029]
Therefore, as a result of diligent research, the present inventor has found that the YAlO _x film can be etched in a controlled and uniform manner by etching the YAlO _x film using a chemical solution having a pH region in which the solubility of Y and Al is relatively close. It was. Similarly, by etching the GdAlO _x film or DyAlO _x film by using a chemical Gd and Al or Dy and Al relatively close pH region solubility is controlled and uniformly also GdAlO _x film or DyAlO _x film We found that it can be etched.
[0030]
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0031]
Embodiment 1
2 to 4 are cross-sectional views showing the manufacturing process of the semiconductor device according to the present embodiment. In these drawings, the same reference numerals indicate the same parts.
[0032]
First, element isolation regions 202 and 203 are formed on a silicon substrate 201 using a known method.
[0033]
Next, a high-k film 205 is formed as an insulating film on the silicon substrate 201 and the element isolation regions 202 and 203. As the High-k film 205, any one film selected from the group consisting of a YAlO _x film, a GdAlO _x film, and a DyAlO _x film is used. The film thickness of the High-k film 205 can be, for example, about 3 nm to 7 nm. Note that after the high-k film 205 is formed, it is preferable to perform heat treatment for densification of the film and reduction of the impurity concentration. The conditions for the heat treatment can be, for example, about 600 ° C. for about 2 minutes.
[0034]
Further, in the present embodiment, as shown in FIG. 4A, after forming the element isolation regions 202 and 203, the SiO ₂ film 204 is formed on the silicon substrate 201, and then the High-k film 205 is formed. It may be formed. By forming the SiO ₂ film 204 between the silicon substrate 201 and the high-k film 205, the reaction between the silicon substrate 201 and the high-k film 205 can be suppressed, and thus high-temperature heat treatment is required. It is suitable for the case. Further, with such a configuration, the equivalent silicon oxide film thickness of the high-k film 205 can be reduced. Note that the thickness of the SiO ₂ film 204 can be, for example, about 1 nm, and can be formed by a thermal oxidation method or the like.
[0035]
Next, as illustrated in FIG. 2A, a polycrystalline silicon film 206 to be a gate electrode is formed on the high-k film 205. Note that an amorphous silicon film or a polycrystalline silicon germanium film may be used instead of the polycrystalline silicon film.
[0036]
After the polycrystalline silicon film 206 is formed, this is patterned to form a gate electrode. The gate electrode can be formed, for example, by forming a resist film on the polycrystalline silicon film and etching the polycrystalline silicon film using a resist pattern formed by exposing and developing the resist film as a mask. . In addition, a silicon oxide film and a resist film are sequentially formed on the polycrystalline silicon film, a resist pattern is transferred to the silicon oxide film to form a hard mask, and the polycrystalline silicon film is etched using the hard mask. Can also be formed.
[0037]
FIG. 2 shows an example of etching a polycrystalline silicon film using a hard mask.
[0038]
As shown in FIG. 2A, an SiO ₂ film 207, an antireflection film 208, and a resist film 209 are formed in this order on the polycrystalline silicon film 206 as a hard mask. The antireflection film 208 plays a role of eliminating exposure light reflection at the interface between the resist film 209 and the antireflection film 208 by absorbing exposure light transmitted through the resist film 209 when patterning the resist film 209. . As the antireflection film 208, a film containing an organic substance as a main component can be used. For example, the antireflection film 208 can be formed by a spin coating method or the like. In the present embodiment, the antireflection film 208 may be omitted.
[0039]
Next, a resist pattern 210 having a desired line width is formed by a photolithography method to obtain the structure of FIG.
[0040]
Next, the antireflection film 208 and the SiO ₂ film 207 are sequentially etched using the resist pattern 210 as a mask. Thereafter, the resist pattern 210 that has become unnecessary is removed. It should be noted that the etching conditions may be set so that the resist pattern 210 disappears almost simultaneously with the etching of the antireflection film 208 and the SiO ₂ film 207 being exposed. In this case, the SiO ₂ film 207 is etched using an antireflection film pattern (not shown) as a mask. After the SiO ₂ film pattern 210 as the hard mask is formed, the antireflection film pattern can be removed by performing plasma treatment using oxygen gas, for example. FIG. 2C is a cross-sectional view showing a state after the SiO ₂ film pattern 211 is formed.
[0041]
Next, the polycrystalline silicon film 206 is etched using the SiO ₂ film pattern 211 as a mask to obtain the structure shown in FIG. In the figure, a polycrystalline silicon film pattern 212 is a gate electrode.
[0042]
On the other hand, when the gate electrode is formed using the resist pattern as a mask, only the resist film is formed on the polycrystalline silicon film 206 in FIG. Next, a resist pattern is formed by exposing and developing the resist film, and a gate electrode can be formed by etching the polycrystalline silicon film 206 using the resist pattern as a mask.
[0043]
Etching the polycrystalline silicon film using the resist pattern as a mask is simple because the number of steps is reduced. On the other hand, the method using a hard mask is suitable for forming a fine electrode pattern.
[0044]
Next, in FIG. 3A, the high-k film 205 is etched using the SiO ₂ film pattern 211 as a mask. In this embodiment mode, the high-k film 205 is wet-etched using a chemical solution having a pH of 8 to 9, preferably a pH of 8.3 to 9.0.
[0045]
As is apparent from FIG. 1, the solubility of Y, Gd, Dy and Al shows a similar value in the pH 8-9 region, particularly in the pH 8.3-9.0 region. Therefore, if the YAlO _x film, GdAlO _x film or DyAlO _x film is etched using a chemical solution having such a pH, Y, Gd, Dy and Al are uniformly dissolved in the solution (that is, the same degree). It is possible to perform uniform etching with good control.
[0046]
The chemical used for etching the high-k film 205 preferably contains fluorine and an amine. For example, a chemical solution obtained by adding H ₂ O ₂ (hydrogen peroxide) to an NH ₄ F (ammonium fluoride) aqueous solution can be used. In this case, if the pH of the chemical solution is 8.5 and the ratio of Y in the High-k film is 0.5, the etching rate is about 1 nm / min at room temperature. Therefore, for example, by etching the YAlO _x film having a thickness of 3 nm for about 5 to 6 minutes, these films including the stepped portion can be processed into a good shape. The same applies to the GdAlO _x film and the DyAlO _x film.
[0047]
In this manner, the high-k film 205 can be selectively processed while preventing damage to the silicon substrate 201 by wet etching using a chemical solution having a pH of 8 to 9. In this case, the silicon substrate 201 can be further prevented from being damaged by adding H ₂ O ₂ to the chemical solution.
[0048]
According to the present embodiment, the high-k film is not processed into a tapered cross section, and a semiconductor device having excellent electrical characteristics can be manufactured. Further, regardless of the ratio of Y, Gd, and Dy in the High-k film, the High-k film can be satisfactorily etched. Furthermore, the high-k film can be uniformly etched regardless of the high-k film formed on the silicon substrate and the high-k film formed on the element isolation region.
[0049]
Through the above steps, the structure shown in FIG. 3B can be obtained. In FIG. 3B, the SiO ₂ film pattern 211 is formed on the gate electrode. However, when the polycrystalline silicon film 206 is etched using the resist pattern as a mask, the SiO ₂ film pattern 211 is not formed. Needless to say.
[0050]
When the SiO ₂ film 204 shown in FIG. 4A is formed, the structure shown in FIG. 4B is obtained through the same process as described above. In FIG. 4B, on the SiO ₂ film 204, a high-k film 205, a polycrystalline silicon film pattern 212 as a gate electrode, and an SiO ₂ film pattern 211 are formed. In the case where the polycrystalline silicon film pattern 212 is formed using the resist pattern as a mask, the SiO ₂ film pattern 211 is not formed.
[0051]
After the structure shown in FIG. 3B or 4B is formed, the present invention is passed through known processes necessary for manufacturing a semiconductor device in addition to the formation of an interlayer insulating film, a contact, and a wiring layer. A semiconductor device can be manufactured.
[0052]
【The invention's effect】
According to the present invention, any one film selected from the group consisting of a YAlO _x film, a GdAlO _x film, and a DyAlO _x film is used as a High-k film, and the High-k film is wet-etched with a chemical solution having a pH of 8-9. Thus, a semiconductor device having good electrical characteristics can be manufactured.
[Brief description of the drawings]
FIG. 1 is a graph showing the pH dependence of the solubility of Y and Al.
FIGS. 2A to 2C are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the present embodiment.
FIGS. 3A and 3B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the present embodiment. FIGS.
4A and 4B are cross-sectional views showing the manufacturing steps of the semiconductor device according to the present embodiment.
FIGS. 5A to 5D are cross-sectional views showing a manufacturing process of a conventional semiconductor device. FIGS.
[Explanation of symbols]
201, 501 silicon substrate,
202, 203, 502, 503 element isolation region,
204, 504 SiO ₂ film 205, 505 High-k film,
206,506 polycrystalline silicon film,
207,507 SiO ₂ film,
208,508 Anti-reflective coating,
209 resist film,
210,509 resist pattern,
211, 510 SiO ₂ film pattern,
212,511 Polycrystalline silicon film pattern.

Claims (5)

Forming on the silicon substrate any one insulating film selected from the group consisting of a YAlO _x film, a GdAlO _x film, and a DyAlO _x film;
Forming a gate electrode on the insulating film;
And a wet etching process for the insulating film using a chemical solution having a pH of 8-9. Forming a SiO ₂ film on a silicon substrate;
Forming one insulating film selected from the group consisting of a YAlO _x film, a GdAlO _x film, and a DyAlO _x film on the SiO ₂ film;
Forming a gate electrode on the insulating film;
And a wet etching process for the insulating film using a chemical solution having a pH of 8-9. The method of manufacturing a semiconductor device according to claim 1, wherein the chemical solution contains fluorine and an amine. The method of manufacturing a semiconductor device according to claim 3, wherein the chemical solution is an aqueous ammonium fluoride solution. The method for manufacturing a semiconductor device according to claim 1, wherein the chemical solution includes hydrogen peroxide.

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