JP2005044460A - Memory control system and memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To save electric power consumption during the time from a system reset to initialization and electric power consumption during the time from the backup of the storage content of the memory due to abnormality in a power source to the restart thereof. <P>SOLUTION: The memory system has the memory 39 constituted of a DRAM, a memory control circuit 30 for controlling the memory 39, and a logic circuit 40 including a CPU. The memory control circuit 30 has a refresh circuit 31 which makes a CAS signal precedent to an RAS signal and instructs an ordinary refresh to the memory 39 and a flag 33 which is turned off by a reset signal and is turned on by the instruction of the logic circuit 40. When the flag 33 is turned off, the memory 39 is refreshed by the self-refresh to perform the refresh operation at specified intervals by its own control of the DRAM and when the flag 33 is turned on, the memory 39 is refreshed in the ordinary refresh by the refresh circuit 31. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory control system and a memory control circuit, and more particularly to a memory refresh control technique in the event of a system reset or power failure.

  In a memory constituted by a DRAM (dynamic random access memory), an operation called refresh is required to maintain information stored in the DRAM. The refresh is executed by controlling a RAS (row address strobe) signal and a CAS (column address strobe) signal at regular intervals by a memory control circuit that controls the memory.

  In normal access, the CAS signal is driven after the RAS signal is driven to perform read or write access to the DRAM. The refresh instruction is instructed to the DRAM by driving the CAS signal prior to the RAS signal. It has been known.

  Japanese Patent Application Laid-Open No. 5-28757 discloses a refresh control for a system reset for initializing and restarting a main unit while maintaining the contents of a memory device. In Japanese Patent Laid-Open No. 5-28757, in response to a system reset, the access circuit in the memory control device is reset, but the refresh circuit is not reset so that the refresh can be continued and the contents of the memory device can be maintained. Yes.

  A DRAM having a self-refresh function in which the DRAM itself performs refreshing at regular intervals has also been put into practical use. The self-refresh function is a function in which the DRAM itself performs refresh automatically without giving an external refresh instruction to the DRAM, and has a feature that power consumption is reduced.

JP-A-5-28757

  In the technique disclosed in Japanese Patent Laid-Open No. 5-28757, the refresh circuit is configured not to be reset at the time of system reset, so that refresh can be continued by an instruction from the memory control device even during reset. Until memory access is started after memory conversion (memory contents are retained), it is necessary to operate the memory control device and continue refreshing even though there is no memory access, and power is wasted.

  In addition, it is known that self-refreshing is performed when the power supply of the main unit is turned off and only the contents of the memory device are held for power saving, and particularly in a small device powered by a battery, power saving is known. The demand is big. When the battery is exhausted or accidentally dropped, and the battery suddenly breaks down, suddenly the voltage supply becomes abnormal. Using the secondary battery provided for backup, the memory contents are held and the main battery is restored. Even when refresh control is refreshed, initialization is performed when the main battery is restored, and power is wasted.

  An object of the present invention is to provide a memory control system and a memory capable of saving power consumption from system reset to initialization and power consumption from backup to restart of memory contents due to power failure. It is to provide a control device.

A first memory control system of the present invention is a memory control system having a memory constituted by a DRAM, a memory control circuit for controlling the memory, and a logic circuit including a CPU,
The memory control circuit starts a self-refresh instruction for refreshing the memory with DRAM itself by a system reset, and a normal refresh instruction for causing the CAS signal to precede the RAS signal at regular intervals after the initialization after the system reset. Start with memory.

A second memory control system of the present invention is a memory control system having a memory composed of DRAM, a memory control circuit for controlling the memory, and a logic circuit including a CPU,
The memory control circuit includes a refresh circuit that instructs the memory to perform normal refresh by causing the CAS signal to precede the RAS signal, and a flag that is turned off by a reset signal and turned on by an instruction from a logic circuit, and the flag is turned off. The memory is refreshed by self-refresh that performs refresh operations at regular intervals under the control of the memory itself, and when the flag is turned on, the memory is refreshed by normal refresh by a refresh circuit.

The third memory control system of the present invention supplies power only to the memory when there is an abnormality in the memory composed of DRAM, the memory control circuit for controlling the memory, the logic circuit including the CPU, the main battery, and the main battery. A memory control system having a secondary battery and a power supply monitoring circuit for monitoring an abnormality of the main battery,
The power monitoring circuit monitors the voltage of the main battery and outputs a reset signal when the voltage falls below a specified value.The memory control circuit precedes the RAS signal with the CAS signal to instruct the memory to perform normal refreshing; and And a flag indicating that the memory can be accessed. When a reset signal is output from the power supply monitoring circuit, the flag is turned off, and the memory is controlled by self-refresh that performs refresh operations at regular intervals under the control of the memory itself. After refreshing and the power supply of the main battery is stopped, the self-refresh of the memory is continued by the power supply by the sub battery. Features.

  According to a fourth memory control system of the present invention, in the second or third memory control system of the present invention, the logic circuit notifies the memory control circuit of the completion of initialization when the initialization process after resetting is completed. The memory control circuit that has received the notification of completion of initialization turns on the flag.

  The first memory control circuit according to the present invention includes a refresh circuit for instructing normal refresh to a memory constituted by a DRAM by causing a CAS signal to precede a RAS signal, and an on-state by a logic circuit including a CPU that is turned off by a reset signal. When the flag is turned off, the memory is instructed to execute a self-refresh that performs a refresh operation at regular intervals under the control of the memory. When the flag is turned on, normal refresh by the refresh circuit is sent to the memory. It is characterized by instructing.

  In the second memory control circuit of the present invention, in the first memory control circuit of the present invention, the flag is turned on by an initialization end notification notified from the logic circuit when the initialization process after reset is completed. It is characterized by that.

  There is an effect that power consumption at the time of system reset or power supply restoration that must retain the stored contents of the memory can be saved.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a memory control system according to the present invention. The memory 39 is a DRAM, a memory control circuit 30 for controlling the memory 39, a CPU other than the memory 39 and the memory control circuit 30 of the main unit, and an input circuit. A logic circuit 40 including an output device, a main battery 10 that supplies power, a sub-battery 11 for power backup, a power supply circuit 12, a power monitoring circuit 21 that monitors power, a reset circuit 23, and the like are included.

  The power supply circuit 12 converts the DC power supply voltage supplied from the main battery 10 and the sub-battery 11 into a DC voltage used in the logic circuit 40 or the like according to the signal received from the power switch 25 and the power control signal X68 received from the logic circuit 40. The normal power source X51 generated by the main battery 10 is supplied to the logic circuit 40 and the memory control circuit 30, and the back-up power source X52 generated from the main battery 10 and the sub battery 11 is supplied to the memory 39. To do. Although not shown, power generated from the main battery 10 and the sub battery 11 is supplied to the power supply monitoring circuit 21, reset circuit 23, and OR gate 22 regardless of the on / off state of the power supply.

  The power supply monitoring circuit 21 monitors the output voltage of the main power supply 10, and outputs a power supply abnormality signal X <b> 65 to the OR gate 22 and the power supply circuit 12 assuming that an abnormality has occurred in the main battery 10 when the voltage drops below a predetermined voltage. . For example, the main power supply abnormality may be the case where the device of FIG. 1 is a battery-powered device that is accidentally dropped and the battery is removed from the case and the power supply is lost, or the battery is broken or Life expectancy is considered.

  The reset circuit 23 is determined in advance when the reset switch 24 is operated to instruct system reset, when the power switch 25 is operated to turn on the power, or when the logic circuit 40 instructs system reset. A system reset signal X67 having a pulse width greater than the generated pulse width is generated and output. The OR gate 22 outputs the logical sum of the power supply abnormality signal X65 and the system reset signal X66 as the reset signal X67. The reset signal X67 is connected to the memory control circuit 30 and the logic circuit 40.

  The power switch 25 is a switch for turning on / off the power supply. When the power is turned on, the power supply circuit 12 is instructed to start output of the normal power supply X51 and the power supply X52 with backup, and the reset circuit 23 is instructed to perform power-on reset. When the power is turned off, the power supply circuit 12 is instructed to stop the output of the normal power source X51 and the backup power source X52 and the reset circuit 23 is instructed to be reset. In this case, the reset circuit 23 notifies that the reset factor is a power-on reset when the reset is released, and the logic circuit 40 executes initialization of all hardware resources. At the time of power-on reset, it is not necessary to hold the memory contents at the time of initialization. Therefore, normal refresh may be started when memory access is started.

  FIG. 2 is a block diagram showing a configuration example of the memory control circuit 30. As shown in FIG. The memory control circuit 30 is a circuit for controlling access and refresh of the memory 39 composed of DRAM, and one configuration example is shown in FIG. Referring to FIG. 2, the flag 33 is a flag indicating that the memory access is possible. The flag 33 is turned on by an instruction from the logic circuit 40 to enter an access permission state, and is turned off by the reset signal X67 to enter an access inhibition state. . When the flag 33 is off, the outputs of the AND gate 35 and the AND gate 36 are set to the low level, and the RAS signal X61 and the CAS signal X62 are set to the low level. That is, when the flag 33 is turned off, a self-refresh state is established.

  When the flag 33 is ON, the refresh circuit 31 is a circuit for controlling the refresh of the memory 39 by giving a normal refresh instruction at a regular interval that causes the CAS signal X62 to precede the RAS signal X61. When the flag 33 is on, the access circuit 32 receives a memory access request from the logic circuit 40, outputs an address and a control signal to the address / control line X63 in accordance with the RAS signal X61 and the CAS signal X62, and the data line X64. Read data or output write data to the data line X64. The access circuit 32 turns on the flag 33 when receiving an initialization end notification from the logic circuit 40, and instructs the selector 34 to input a RAS / CAS signal when receiving a normal refresh request from the refresh circuit 31. Switch to 31.

  Next, the operation of the memory control system of the present invention will be described with reference to the drawings. FIG. 3 is a timing chart showing the refresh operation at the time of system reset. Referring to FIG. 3, when the memory 39 is accessible and normal refresh is being executed, that is, when the flag 33 is on, the refresh circuit 31 requests the access circuit 32 to control the RAS / CAS under the control of the selector 34. At the timing T71, the CAS signal X62 is set to the active low level, the RAS signal X61 is set to the active low level, and the CAS signal X62 is returned to the high level at the timing T72 after a specified time, and then the RAS signal X61. Return to high level.

  When the DRAM of the memory 39 receives the CAS signal X62 and the RAS signal X61 from timing T71 to T72, it detects that it is a normal refresh instruction and executes refresh. In the normal refresh state, the refresh circuit 31 interrupts the access operation of the access circuit 32 at regular intervals, controls the CAS signal X62 and the RAS signal X61 as described above, and gives a normal refresh instruction to the memory 39.

  When a system reset is instructed from the reset switch 24 or the logic circuit 40 at timing T73, the reset circuit 23 outputs a system reset signal X66 having a predetermined pulse width or more to the OR gate 22. The OR gate 22 outputs a reset signal X67 to the logic circuit 40 and the memory control circuit 30, and the logic circuit 40 and the memory control circuit 30 reset a hardware circuit invisible to software to a predetermined value by the reset signal X67. .

  The operation during the reset between the timings T73 and T74 will be described. The flag 33 is turned off by the reset signal X67, the RAS signal X61 and the CAS signal X62 both become low level, and illegal memory access is suppressed. Self-refreshing is started by detecting that X61 and CAS signal X62 are at a low level for a predetermined time or more. The access circuit 32 resets the access request to the memory 39 being reset and the hardware resource for controlling access to a state in which no access is made, and the refresh circuit 31 stops the operation by the reset and continues to stop until the flag 33 is turned on. .

  When the reset is released at timing T74, the logic circuit 40 starts initialization that is predetermined as processing at the time of system reset. In initialization, resetting of control information necessary for resuming processing with the memory contents held is executed, but initialization hereinafter does not include an operation of writing data in the memory 39 to an initial value. To do. Usually, initialization is executed by a microprogram or the like that executes hardware processing, and may take several tens of seconds depending on the apparatus.

  Until the timing T75, the memory 39 continues the self-refresh and holds the stored information, and the memory control circuit 30 rejects acceptance of the memory access request. When the initialization is completed at timing T75, the logic circuit 40 sends an initialization end notification to the memory control circuit 30, and the access circuit 32 receives the initialization end notification and turns on the flag 33. When the flag 33 is turned on, the refresh circuit 31 and the access circuit 32 start operating. Thereafter, the refresh circuit 31 starts a normal refresh instruction at regular intervals, and the access circuit 32 also resumes accepting a memory access request.

  As described above, when a system reset is issued, the memory control circuit 30 stops operating from the reset to the end of initialization, and the memory 39 holds the stored contents by self-refreshing with low power consumption. Therefore, power consumption can be saved.

  Next, the operation when the power supply of the main battery 10 suddenly stops will be described with reference to FIG. When the power supply from the main battery 10 is normal, the refresh circuit 31 issues a normal refresh instruction at regular intervals at timings T81 and T82.

  Thereafter, at timing T83, when the main battery 10 becomes abnormal for some reason and the voltage becomes equal to or lower than the specified value, the power monitoring circuit 21 detects the abnormality and outputs a power abnormality signal X65 to the OR gate 22. The OR gate 22 outputs a reset signal X67 to the logic circuit 40 and the memory control circuit 30. The power monitoring circuit 21 sends a power stop signal X69 to the power supply circuit 12.

  The power supply circuit 12 receives the power supply stop signal X69 from the power supply monitoring circuit 21 and receives the power supply stop signal X69 from the power supply monitoring circuit 21 in order to prevent the supply of the normal power supply from stopping or becoming unstable when the main battery 10 is abnormal. The output is stopped and only the power source with backup X52 continues to be supplied normally using the power of the sub battery 11. Accordingly, power supply to the logic circuit 40 and the memory control circuit 30 is stopped, and power is normally supplied only to the memory 39.

  When the memory control circuit 30 receives the reset signal X67, the flag 33 is turned off and the RAS signal X61 and the CAS signal X62 are set to low level to instruct the memory 39 to perform self-refresh. After that, even if the power is turned off, the RAS signal X61 and the CAS signal X62 are kept at the low level, so that the self-refresh instruction is continued. As a result, the apparatus is turned off and the memory 39 shifts to self refresh.

  After that, when the abnormality of the main battery 10 is recovered at timing T84, the power supply monitoring circuit 21 detects that the voltage has become normal, stops outputting the power supply stop signal X69, and delays only the time necessary for resetting. The output of the power supply abnormality signal X65 is stopped. As a result, the supply of the normal power supply X51 from the power supply circuit 12 is started, and the reset signal X67 continues to be in a reset state. In this state, the refresh circuit 31 continues to instruct self-refresh.

  When the reset signal X67 is released at timing T85, the logic circuit 40 starts initialization, initializes the hardware according to a predetermined procedure, and when initialization is completed at timing T86, notifies the initialization end notification to the memory control circuit. Send to 30. When the memory control circuit 30 receives the initialization end notification, the access circuit 32 turns on the flag 33 and the refresh circuit 31 starts its operation. As a result, the RAS signal X61 and the CAS signal X62 become high level, and become low level by the normal refresh instruction at timing T87, and are restored to high level.

  As described above, even if the power supply from the main battery 10 stops without notice, it is detected and stored in the memory 39 by supplying power from the sub battery 11 only to the memory 39 and performing self-refresh. The stored information can be retained, and can be reused without losing the information stored in the memory 39 by returning to normal refresh after power recovery. In addition, since the self-refresh is performed during the initialization, the power saving efficiency is further increased.

  The present invention can also be applied to an information processing apparatus that is not battery-driven, and similar effects can be obtained.

It is a block diagram which shows the structure of this invention. 3 is a block diagram showing a configuration of a memory control circuit 30. FIG. It is a timing chart which shows the operation | movement of a system reset. It is a timing chart which shows operation at the time of power failure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Main battery 11 Sub battery 12 Power supply circuit 21 Power supply monitoring circuit 22 OR gate 23 Reset circuit 24 Reset switch 25 Power switch 30 Memory control circuit 31 Refresh circuit 32 Access circuit 33 Flag 39 Memory 40 Logic circuit

Claims (6)

A memory control system having a memory composed of DRAM, a memory control circuit for controlling the memory, and a logic circuit including a CPU,
The memory control circuit starts a self-refresh instruction for refreshing the memory with DRAM itself by a system reset, and a normal refresh instruction for causing the CAS signal to precede the RAS signal at regular intervals after the initialization after the system reset. Memory control system characterized by starting with memory. A memory control system having a memory composed of DRAM, a memory control circuit for controlling the memory, and a logic circuit including a CPU,
The memory control circuit includes a refresh circuit that instructs the memory to perform normal refresh by causing the CAS signal to precede the RAS signal, and a flag that is turned off by a reset signal and turned on by an instruction from a logic circuit, and the flag is turned off. And a memory control system, wherein the memory is refreshed by self-refresh that performs refresh operations at regular intervals under the control of the memory itself, and when the flag is turned on, the memory is refreshed by normal refresh by a refresh circuit. A memory composed of DRAM, a memory control circuit that controls the memory, a logic circuit including a CPU, a main battery, and an abnormality in the main battery and the sub battery that supplies power only to the memory when there is an abnormality are monitored. A memory control system having a power monitoring circuit,
The power monitoring circuit monitors the voltage of the main battery and outputs a reset signal when the voltage falls below a specified value.The memory control circuit precedes the RAS signal with the CAS signal to instruct the memory to perform normal refreshing; and And a flag indicating that the memory can be accessed. When a reset signal is output from the power supply monitoring circuit, the flag is turned off, and the memory is controlled by self-refresh that performs refresh operations at regular intervals under the control of the memory itself. After refreshing and the power supply of the main battery is stopped, the self-refresh of the memory is continued by the power supply by the sub battery. A featured memory control system. The logic circuit sends an initialization end notification to the memory control circuit when the initialization process after reset is completed, and the memory control circuit that has received the initialization end notification turns on the flag. 2 or 3 memory control methods. It has a refresh circuit for instructing normal refresh to the memory composed of DRAM by making the CAS signal precede the RAS signal, and a flag that is turned off by the reset signal and turned on by the instruction of the logic circuit including the CPU. And a memory control circuit for instructing the memory to execute self-refresh that performs refresh operations at regular intervals under the control of the memory itself, and for instructing the memory to perform normal refresh by the refresh circuit when the flag is turned on. 6. The memory control circuit according to claim 5, wherein the flag is turned on by an initialization end notification notified from the logic circuit when the initialization process after reset is completed.

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