JP2005044412A - Nonvolatile memory device and electronic apparatus using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory device capable of realizing an improvement of yield, the extension of service life, and an increase of the degree of freedom of a data processing or the like. <P>SOLUTION: A ferrodielectric memory 2 comprises one ferrodielectric capacitor, input data DIN is stored in the capacitor. A comparator 3 performs binarization of the input data DIN or read-out data from the ferrodielectric memory 2. A clocked inverter 4 reverses an input from the comparator 3 at the time of its operation and outputs it. A latch circuit 5 latches output data of the clocked inverter 4. In MOS transistors M1, M2 included in the ferroelectric memory 2 and MOS transistors M3-M6 constituting the clocked inverter 4, the prescribed ON-OFF operation is controlled by a control circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory device including a ferroelectric capacitor and a latch circuit, and an electronic apparatus using the nonvolatile memory device.
[0002]
[Prior art]
Conventionally, as this type of nonvolatile memory device, for example, the one shown in FIG. 22 is known (see, for example, Non-Patent Document 1).
As shown in FIG. 22, this nonvolatile memory device includes an inverter INV11 and MOS transistors M11 and M12 in addition to a normal latch circuit including inverters INV12 and INV13 and two ferroelectric capacitors C11 and C12. And an electronic switch composed of MOS transistors M13 and M14.
[0003]
MOS transistors M15 and M16 are connected to the inverters INV12 and INV13, and the MOS transistors M15 and M16 are controlled to be turned on / off by power supply on / off signals PWRL and PWRH, thereby controlling the supply of the power supply voltage VDD to the inverters INV12 and INV13. I am doing so.
A pump signal PUMP signal is supplied to the ferroelectric capacitors C11 and C12. Input data DIN is supplied to the inverter INV11. The MOS transistors M11 and M14 are on / off controlled by the clock signal CLK, and the MOS transistors M12 and M13 are on / off controlled by the clock signal CLKX.
[0004]
Next, an operation example of the conventional nonvolatile memory device having such a configuration will be described with reference to FIGS.
First, the normal operation of this conventional apparatus will be described with reference to FIGS. Prior to this normal operation, since the power on / off signal PWRL is at the L level and the power on / off signal PWRH is at the H level, the MOS transistors M15 and M16 are in the on state. For this reason, the power supply voltage VDD is supplied to the inverters INV12 and INV13. This state is maintained thereafter.
[0005]
In the initial state of the normal operation, the output data DOUT and the polarization directions of the ferroelectric capacitors C11 and C12 are indefinite.
A period T1 in FIG. 23 indicates an input state of the input data DIN.
In this period T1, the input data DIN is at the H level. In this period T1, since the clock signal CLK is at the H level and the clock signal CLKX is at the L level, the MOS transistors M11 and M12 are turned on and the MOS transistors M13 and M14 are turned off. Further, the pump signal PUMP is at L level.
[0006]
At this time, the H level of the input data DIN is inverted to the L level by the inverter INV11 and becomes the L level, and the input data Q2 of the inverter INV13 becomes the L level. Accordingly, the L level input data Q2 is inverted by the inverter INV13, and the output data DOUT becomes H level.
At this time, the L level output data DOUT is inverted by the inverter INV12, and the output data Q1 of the inverter INV12 becomes L level. At this time, the L level of the output data Q1 and the L level of the pump signal PUMP are applied to both ends of the ferroelectric capacitor C11, and there is no potential difference between both ends, so the polarization direction remains indefinite. On the other hand, the H level of the output data DOUT and the L level of the pump signal PUMP are applied to both ends of the ferroelectric capacitor C12. The polarization direction of the ferroelectric capacitor C12 at this time is downward (shown as “↓” in FIG. 23) as shown in FIG.
[0007]
As is clear from the above description, in the period T1 in FIG. 23, the input data DIN is at the H level, and the H level state appears as it is as the output data DOUT.
A period T2 in FIG. 23 shows a state in which the input data DIN is latched into the latch circuit and the polarization directions of the ferroelectric capacitors C11 and C12 are written.
[0008]
During this period T2, the input data DIN is at the H level. In this period T2, since the clock signal CLK is at the L level and the clock signal CLKX is at the H level, the MOS transistors M11 and M12 are turned off and the MOS transistors M13 and M14 are turned on. Further, the pump signal PUMP is at the H level.
Thus, in the period T2, the MOS transistors M11 and M12 are turned off and the MOS transistors M13 and M14 are turned on, so that the H level of the input data DIN is latched. Therefore, in the period T2, the output data DOUT is maintained at the H level, and the levels of Q1 and Q2 remain at the L level.
[0009]
As a result, since the L level of Q1 and the H level of the pump signal PUMP are applied to both ends of the ferroelectric capacitor C11, the polarization direction is upward (referred to as “↑” in FIG. 23). On the other hand, the H level of the output data DOUT and the H level of the pump signal PUMP are applied to both ends of the ferroelectric capacitor C12, and there is no potential difference between both ends of the ferroelectric capacitor C12. To maintain. That is, the polarization direction is downward.
[0010]
As is clear from the above description, in the period T2 in FIG. 23, the input data DIN is at the H level, the input data DIN is latched into the latch circuit, and the polarization state of the ferroelectric capacitors C11 and C12 is written. It becomes.
A period T3 in FIG. 23 shows the latch state of the input data DIN in the latch circuit and the ferroelectric capacitors C11 and C12, and the level of the pump signal PUMP is different in the waveforms of the respective parts in the period T3 and the period T2.
[0011]
Each operation described above is for the case where the input data DIN is at the H level, but the operation waveform of each part when the input data DIN is at the L level is as shown in the periods T4 to T6 in FIG.
Here, each operation in the period T4 to the period T6 corresponds to each operation in the period T1 to the period T3, and thus description thereof is omitted here. In this case, since the input data DIN is at the L level, as can be seen from the period T5 in FIG. 23, the polarization directions written in the ferroelectric capacitors C11 and C12 are reversed compared to the period T2. You can see that
[0012]
Next, a method for reading data held in the ferroelectric capacitors C11 and C12 as described above will be described with reference to FIGS. 22, 24, and 25. FIG.
Here, FIG. 24 shows an operation waveform of each part at the time of reading data “1”. FIG. 25 shows an example of the operation waveform of each part at the time of reading data “0”.
[0013]
When reading this data, it is necessary to set as follows. That is, the input data DIN is L level, the clock signal CLK is L level, and the clock signal CLKX is H level. For this reason, the MOS transistors M11 and M12 are turned off and the MOS transistors M13 and M14 are turned on.
In the period T1 in FIG. 24, the pump signal PUMP is at the H level, the power on / off signal PWRL is at the H level, and the power on / off signal PWRH is at the L level in the above state. For this reason, the inverters INV12 and INV13 are not supplied with the power supply voltage VDD, which is also a setting necessary for reading data.
[0014]
At this time, since it is assumed that the data “1” is held in the ferroelectric capacitors C11 and C12, the polarization direction is as shown in the period T1 in FIG.
In the period T2 in FIG. 24, the pump signal PUMP is set to the H level. As a result, the ferroelectric capacitors C11 and C12 output charges according to their polarization directions, and the levels of the output data DOUT and Q1 (Q2) change as shown in the period T2. The output data DOUT becomes a high voltage because there is a change in the polarization direction of the ferroelectric capacitor C12, and the level of Q1 (Q2) is lower than the output data DOUT because there is no change in the polarization direction of the ferroelectric capacitor C11. Become potential.
[0015]
As can be seen from the above, data is read during the period T2.
In the period T3 in FIG. 24, the power on / off signal PWRL is at the L level and the power on / off signal PWRH is at the H level. Therefore, the inverters INV12 and INV13 are in a state where the power supply voltage VDD is supplied. As a result, the voltage difference between the output data DOUT and Q1 is widened, so that the output data DOUT becomes H level and Q1 (Q2) becomes L level.
[0016]
As can be seen from the above, it is understood that data is being restored in the period T3.
In the period T4 in FIG. 24, the read data is written. In the period T3 in FIG. 24, the polarization of the ferroelectric capacitor C11 does not actually change in the polarization direction as shown by a circle in the figure, but the polarization amount (conservation amount of electric charge) changes and remains as it is. Then, there is a possibility that data cannot be normally read at the next reading. Therefore, data is written in a period T4 in FIG.
[0017]
A period T5 in FIG. 24 is a data latch state, and the waveform of each part at this time is as shown in the figure.
FIG. 25 shows an example of the operation waveform of each part at the time of reading data “0”.
In this case, the data “0” is held in the ferroelectric capacitors C11 and C12. Unlike the above case, the readout control is basically the same as the above case. The explanation of the operation is omitted. Note that the periods T1 to T5 in FIG. 25 correspond to the periods T1 to T5 in FIG.
[0018]
[Non-Patent Document 1]
Nikkei Microdevice December 2002 issue P140
[0019]
[Problems to be solved by the invention]
However, the conventional nonvolatile memory device shown in FIG. 22 has the following problems.
(1) Since two ferroelectric capacitors are used, the manufacturing yield is reduced.
(2) Since the voltage is always applied to the two ferroelectric capacitors at the time of data latching, the life of the ferroelectric capacitor is shortened, and as a result, the life of the device is shortened.
(3) Due to the configuration of the device, data other than the latched data cannot be held in the ferroelectric capacitor, so there is no degree of freedom in the output after the power is turned on.
[0020]
For this reason, the advent of a non-volatile storage device that can solve the above-mentioned problems and the advent of electronic devices using the same are desired.
SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device that can improve yield, extend the life, increase the degree of freedom of data processing, and the like.
Another object of the present invention is to provide an electronic apparatus using the nonvolatile memory device as described above.
[0021]
[Means for Solving the Problems]
In order to solve the above-mentioned problems and achieve the object of the present invention, each invention is configured as follows.
That is, the first invention includes a ferroelectric capacitor that includes one ferroelectric capacitor and that can store 1-bit input data and can store the input data or read data from the ferroelectric memory. A latch circuit; and a switch that is openable and closable interposed between the ferroelectric memory and the latch circuit. The switch receives the input data or read data from the ferroelectric memory in the latch circuit. It closes when memorizing and opens after memorizing.
[0022]
According to a second aspect of the present invention, there is provided a first switch that can be turned on / off to take in one-bit input data, one ferroelectric capacitor, and a second switch that can be turned on / off to connect one end of the ferroelectric capacitor to the ground. A ferroelectric memory for storing the input data, a latch circuit capable of storing the input data or read data from the ferroelectric memory, and between the ferroelectric memory and the latch circuit A third switch that can be turned on and off interposed between the first switch and the second switch according to the contents of the data read / write operation of the ferroelectric memory and the data latch operation of the latch circuit. And a control circuit for controlling a predetermined on / off operation of the third switch.
[0023]
According to a third aspect of the present invention, there is provided a first switch that can be turned on / off to take in 1-bit input data, one ferroelectric capacitor, and a second switch that can be turned on / off to connect one end of the ferroelectric capacitor to the ground. A ferroelectric memory that applies a control signal to the other end of the ferroelectric capacitor and stores the input data in the ferroelectric capacitor; and from the input data or the ferroelectric memory A latch circuit capable of storing read data; a clocked inverter which is interposed between the ferroelectric memory and the latch circuit and which can be controlled on and off and can invert data when turned on; and the ferroelectric In the data read / write operation of the memory and the data latch operation of the latch circuit, the first switch is selected according to the contents of the operation. And a, and a control circuit for controlling the predetermined on-off operation of the second switch and the clocked inverter.
[0024]
According to a fourth invention, in any one of the first to third inventions, a comparator is further provided that binarizes the input data or the read data from the ferroelectric memory.
In a fifth aspect based on the third or fourth aspect, the control circuit performs an OR operation of an on / off signal for turning on / off the second switch and a control signal applied to the other end of the ferroelectric capacitor. And a inverter circuit that inverts the on / off signal. The on / off control of the first switch is performed by the output signal of the NOR circuit, and the clock signal is output by the on / off signal and the output signal of the inverter circuit. The inverter was controlled on and off.
[0025]
According to a sixth invention, in any one of the first to fifth inventions, the circuit further comprises a feedback circuit that feeds back output data of the latch circuit to the ferroelectric memory, and outputs the output data of the latch circuit to the strong data. Rewriting is performed on the dielectric memory.
According to a seventh invention, in any one of the third to sixth inventions, the clocked inverter is replaced with a CMOS inverter and an electronic switch.
[0026]
An eighth invention includes a plurality of nonvolatile memory devices according to the third or fourth invention, an on / off signal for turning on and off the second switch of the nonvolatile memory device, and the nonvolatile memory device A NOR circuit that performs a logical OR operation with a control signal applied to each of the other ends of the ferroelectric capacitor, and an inverter circuit that inverts the on / off signal. On / off control of the first switch included in the volatile memory device is performed, and on / off control of the clocked inverter included in the nonvolatile memory device is performed based on the on / off signal and the output signal of the inverter circuit.
[0027]
According to a ninth aspect of the present invention, there is provided a first switch that can be turned on / off to take in 1-bit input data, one ferroelectric capacitor, and a second switch that can be turned on / off to connect one end of the ferroelectric capacitor to the ground. A ferroelectric memory for storing the input data, a flip-flop in which two inverters are connected to each other, and an electronic switch inserted in a loop of the flip-flop, and the input data or the A latch circuit capable of storing read data from a ferroelectric memory, and a clocked inverter that is interposed between the ferroelectric memory and the latch circuit, can be turned on / off freely, and can invert data when turned on In the data read / write operation of the ferroelectric memory and the data latch operation of the latch circuit, Depending on the contents of work, the first switch, the second switch, and the like and a control circuit for controlling the clocked inverter, and a predetermined on-off operation of the electronic switch.
[0028]
According to a tenth aspect, in the ninth aspect, the circuit further comprises a feedback circuit that feeds back output data of the latch circuit to the ferroelectric memory, and rewrites the output data of the latch circuit to the ferroelectric memory. It has become.
According to an eleventh aspect, in the ninth or tenth aspect, the clocked inverter is replaced with a CMOS inverter and an electronic switch.
[0029]
According to a twelfth aspect of the present invention, there is provided an electronic device that includes a nonvolatile memory that can freely read and write data, and that can read and write various types of data to and from the nonvolatile memory. The nonvolatile memory device according to any one of the eleventh aspects is configured.
According to the nonvolatile memory device of the present invention having the above-described configuration, it is possible to improve yield, prolong life, increase flexibility in data processing, and the like.
[0030]
Moreover, according to the electronic apparatus of the present invention having the above-described configuration, the nonvolatile memory device can exhibit the above-described effects.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a nonvolatile memory device according to the present invention.
As shown in FIG. 1, the nonvolatile memory device 1 according to the first embodiment includes one ferroelectric capacitor C, a ferroelectric memory 2 that stores 1-bit input data DIN, and input data. A latch circuit 5 capable of storing (latching) read data from the DIN or ferroelectric memory 2, a comparator 3 for binarizing data, and a comparator 3 between the ferroelectric memory 2 and the latch circuit 5. And a control circuit (not shown) for generating various control signals for controlling the ferroelectric memory 2 and controlling on / off of the clocked inverter 4.
[0032]
In the first embodiment, as shown in FIG. 1, the input terminal 6 to which the input data DIN is supplied, the output terminal 7 for taking out the output data DOUT, and the MOS transistors M4 and M5 of the clocked inverter 4 are turned on / off. Control terminals 8 and 9 to which ON / OFF signals LTH and LTX are supplied, control terminals 10 and 11 to which ON / OFF signals DS and SP for turning ON / OFF the N-type MOS transistors M1 and M2 are supplied, and a ferroelectric capacitor C A control terminal 12 to which a pump signal PUMP to be supplied is supplied and a reference voltage supply terminal 13 to which a reference voltage (reference voltage) supplied to the comparator 3 is supplied are provided.
[0033]
The ferroelectric memory 2 includes a MOS transistor M1 as a switch for taking in 1-bit input data DIN, one ferroelectric capacitor C, and a switch for connecting one end of the ferroelectric capacitor C to the ground GND. And a MOS transistor M2.
More specifically, MOS transistors M1 and M2 are connected in series between the input terminal 6 and the ground. An ON / OFF signal DS supplied to the control terminal 10 is applied to the gate of the MOS transistor M1, whereby the MOS transistor M1 is controlled to be turned on / off. An ON / OFF signal SP supplied to the control terminal 11 is applied to the gate of the MOS transistor M2, so that the MOS transistor M2 is ON / OFF controlled. The nodes of the MOS transistor M1 and the MOS transistor M2 are connected to one terminal of the ferroelectric capacitor C and the positive input terminal of the comparator 3, respectively. A pump signal PUMP supplied to the control terminal 12 is applied to the other terminal of the ferroelectric capacitor C.
[0034]
The comparator 3 compares the input data DIN or the read data from the ferroelectric memory 2 with the reference voltage VREF supplied to the reference voltage supply terminal 13, and if the data is equal to or higher than the reference voltage VREF, the comparator 3 sets the H level. When the data is lower than the reference voltage VREF, the L level is output. The output of the comparator 3 is input to the clocked inverter 4.
[0035]
The clocked inverter 4 includes a CMOS inverter composed of an N-type MOS transistor M3 and a P-type MOS transistor M6, a P-type MOS transistor M5 for controlling power supply to the inverter on both sides of the inverter, and an N-type MOS transistor. A transistor M4 is provided.
That is, the ON / OFF signal LTH supplied to the control terminal 8 is applied to the gate of the MOS transistor M4, whereby the MOS transistor M4 is controlled to be turned on / off. The gate of the MOS transistor M5 is applied with an on / off signal LT XX supplied to the control terminal 9, whereby the MOS transistor M5 is on / off controlled.
[0036]
Therefore, the clocked inverter 4 has a data inversion function and a switch function for controlling the passage of data.
The latch circuit 5 temporarily stores the input data DIN supplied to the input terminal 6 or the read data of the ferroelectric memory 2 via the comparator 3 and the clocked inverter 4. For this purpose, the latch circuit 5 comprises a flip-flop in which two inverters INV1 and INV2 are connected to each other as shown in FIG. The output of the latch circuit 5 is taken out from the output terminal 7 as output data DOUT.
[0037]
The control circuit (not shown) generates the on / off signals LTH and LTX, the on / off signals DS and SP, the pump signal PUMP, and the like as described above, and supplies the generated signals to the respective units as described above. On-off control is performed.
Next, the operation of the first embodiment having such a configuration will be described with reference to FIGS.
[0038]
Here, FIG. 2 is a waveform diagram of each part during normal operation. FIG. 3 is a waveform diagram of each part during a read operation of data held in the ferroelectric capacitor C.
First, the normal operation of the first embodiment will be described with reference to FIG.
In FIG. 2, an operation of writing polarization into the ferroelectric capacitor C is performed in the period T1, writing and outputting of the input data DIN are performed in the periods T2 and T3, and the written data is held in the period T4. Each of these operations will be described in turn.
[0039]
In the period T1 in FIG. 2, since the on / off signal DS is at the L level, the MOS transistor M1 is in the off state, and the input data DIN is not input to the ferroelectric memory 2. At this time, the pump signal PUMP becomes H level. At this time, since the on / off signal SP is at the H level, the MOS transistor M2 is in the on state, and the node Q of the MOS transistor M1 and the MOS transistor M2 is connected to the ground GND and is at the L level.
[0040]
At this time, since the on / off signal LTH is at the L level and the on / off signal LTHS is at the H level, the MOS transistors M4 and M5 are both turned off, and the power supply voltage VDD is not supplied to the clocked inverter 4. At this time, the output data DOUT is indefinite as shown because the previous state is not defined.
[0041]
Under such conditions, the ferroelectric capacitor C has a terminal connected to the control terminal 12 to which an H level voltage is applied by the pump signal PUMP, and a terminal connected to the node Q is connected to the ground. An L level voltage is applied by connection. The polarization direction of the ferroelectric capacitor C at this time is represented by an upward arrow “↑” as shown in FIG.
[0042]
As described above, in the period T1 in FIG. 2, the operation of writing the polarization in the direction of “↑” to the ferroelectric capacitor C is performed. At this time, since the MOS transistor M1 is off, the input data DIN may be either H level or L level as shown in FIG.
Next, in the periods T2 and T3 in FIG. 2, since the on / off signal DS is at the H level, the MOS transistor M1 is in the on state, and the input data DIN is input to the ferroelectric memory 2. At this time, the pump signal PUMP becomes L level. At this time, since the on / off signal SP is at the L level, the MOS transistor M2 is turned off. As a result, the level of the node Q becomes a level corresponding to the input data DIN.
[0043]
At this time, since the on / off signal LTH is at the H level and the on / off signal LTX is at the L level, the MOS transistors M4 and M5 are both turned on. For this reason, the clocked inverter 4 is supplied with the power supply voltage VDD and is in an operable state.
Here, in the period T2, since the input data DIN is at the H level, the node Q is at the H level. In the period T3, since the input data DIN is at L level, the node Q is at L level.
[0044]
Now, when the input data DIN is at H level, the output data DOUT corresponding to this is as follows.
At this time, the input data DIN of the H level is input to the comparator 3, which is equal to or higher than the reference voltage VREF, so that the output Q1 of the comparator 3 becomes the H level. The output Q1 of the comparator 3 is inverted by the clocked inverter 4, and the output Q2 becomes L level.
[0045]
Here, the drive capability of the output Q2 of the clocked inverter 4 is set higher than the drive capability of the inverter INV2 constituting the latch circuit 5. That is, the output impedance value of the clocked inverter 4 is smaller than the output impedance value of the inverter INV1. For this reason, the input of the latch circuit 5 follows the output Q2 of the clocked inverter 4 and the output Q2 is an L label. Therefore, the output data DOUT that is the output of the latch circuit 5 is at the H level.
[0046]
Note that when the input data DIN is at the L level (in the case of the period T3), the output data DOUT corresponding to the input data DIN becomes the L level as illustrated.
Next, the polarization direction of the ferroelectric capacitor C at this time will be examined.
When the input data DIN is at the H level as in the period T2, the level of the node Q is at the H level and the pump signal PUMP is at the L level, so that the polarization direction of the ferroelectric capacitor C is downward as shown in the figure. Become.
[0047]
On the other hand, when the input data DIN is at the L level as in the period T3, since the level of the node Q is at the L level and the pump signal PUMP is at the L level, no potential difference occurs between both ends of the ferroelectric capacitor C. The polarization direction remains upward without changing from the state of the period T1.
As is clear from the above description, in the period T2 in FIG. 2, the H level is input as the input data DIN, the output data DOUT is at the H level, and the ferroelectric capacitor C has the H level data. Charges with a downward polarization direction are retained.
[0048]
On the other hand, during the period T3 in FIG. 2, the L level is input as the input data DIN, the output data DOUT is at the L level, and the ferroelectric capacitor C has an electric charge whose polarization direction is upward as the L level data. Retained.
Next, the data latch function of the first embodiment will be described.
The latch circuit 5 holds the output data DOUT after the output data Q2 from the clocked inverter 4 is output, the MOS transistors M4 and M5 are turned off by the on / off signals LTH and LTX, and the power supply voltage VDD is supplied to the clocked inverter 4 It can be realized by stopping.
[0049]
That is, after the period T2 or the period T3 in FIG. 2, the MOS transistors M4 and M5 are turned off by the on / off signals LTH and LTHS, and the output data DOUT of the latch circuit 5 can be latched.
Here, the output data DOUT can be latched even in the state of the period T1 in FIG. 2, but there is no potential difference between both ends of the ferroelectric capacitor C in order to extend the life of the ferroelectric capacitor C. Therefore, in the first embodiment, the state of the period T4 in FIG. 2 is set to the latch state of the output data DOUT.
[0050]
2 will be described. In this period T4, since the on / off signal DS is at the L level, the MOS transistor M1 is in an off state, and the input data DIN is not input to the ferroelectric memory 2. At this time, the pump signal PUMP becomes L level. At this time, since the on / off signal SP is at the H level, the MOS transistor M2 is turned on, and the node Q of the MOS transistors M1 and M2 is connected to the ground GND and at the L level.
[0051]
At this time, since the on / off signal LTH is at the L level and the on / off signal LTHS is at the H level, the MOS transistors M4 and M5 are both turned off, and the power supply voltage VDD is not supplied to the clocked inverter 4.
Under such conditions, in the ferroelectric capacitor C, the voltages at both ends of the ferroelectric capacitor C are both at the L level and there is no potential difference between the both ends. At this time, the node Q is at the L level, the output Q1 of the comparator 3 is at the L level, and the clocked inverter 4 is in an operation stop state, so that the output Q1 is not reflected on the output Q2 of the clocked inverter 4. Therefore, the data held in the latch circuit 5 does not change.
[0052]
Further, the output data DOUT of the latch circuit 5 is held in a state where there is no potential difference between both ends of the ferroelectric capacitor C. Of course, at this time, since there is no potential difference between both ends of the ferroelectric capacitor C, the polarization direction does not change.
In the example of FIG. 2, the latch operation in the period T4 is performed only after the period T2 in FIG. 2, but the latch operation in the period T4 may be performed after the period T3 in FIG. In this case, the latch is performed without changing the L level of the output data DOUT and the polarization direction of the ferroelectric capacitor C with the upward direction.
[0053]
Next, with reference to FIG. 3, a description will be given of the operation of reading the data held in the ferroelectric capacitor C.
FIG. 3A shows the waveform of each part during the read operation when the retained data of the ferroelectric capacitor C is “1”, and FIG. 3B shows the read operation when the retained data is “0”. The waveform of each part at the time is shown.
[0054]
In FIG. 3, a power supply is off in a period T1.
The period T2 is preparation (corresponding to the state of the period T4 in FIG. 2) before reading the data held in the ferroelectric capacitor C. However, if the on / off signal LTH is at the H level and the on / off signal LTX is at the L level, the stored data can be read. However, in this example, in order to reduce the combination of signal settings (the same setting as the latch operation in the period T4 in FIG. 2 is performed).
[0055]
A period T3 indicates a read state of the retained data.
Next, each operation in the periods T1, T2, and T3 in FIG. 3 will be described in detail below.
First, in the period T1 in FIG. 3, since the power is off, the signals of the respective parts are all at the L level as shown in FIG. In this state, the polarization direction of the ferroelectric capacitor C is downward according to the description of FIG. 2 when the data “1” is held, and upward when the data “0” is held.
[0056]
Next, in the period T2 in FIG. 3, the on / off signal SP is at the H level and the on / off signal LTX is at the L level except for the L level, which is the same as the state in the period T4 in FIG.
Therefore, in the period T2, both ends of the ferroelectric capacitor C are at the L level. The output data DOUT is in an indefinite state. Further, since both ends of the ferroelectric capacitor C are at the L level, no change occurs in the direction of polarization. The polarization direction remains downward when data “1” is retained, and remains upward when data “0” is retained.
[0057]
Here, the reason why both ends of the ferroelectric capacitor C are set to the L level in the period T2 is to set the fixed data (in this case, the L level voltage) for the same read condition of the retained data. This is because the polarization of the ferroelectric capacitor C is not destroyed.
Next, in the period T3 in FIG. 3, the ON / OFF signal SP is set to L level to turn off the MOS transistor M2, and the pump signal PUMP applied to the ferroelectric capacitor C is set to H level. As a result, the voltage at the node Q changes, and data is read based on the change.
[0058]
Next, the data output operation from the ferroelectric capacitor C will be described with reference to FIG.
As shown in FIG. 4A, the stray capacitance C1 exists between the wiring pattern and the MOS transistors M1, M2 and the ground at the node Q in FIG. The stray capacitance C1 is controlled and designed to have a value optimized for circuit operation.
[0059]
3, the ferroelectric capacitor C is in the state shown in FIG. 4A, the pump signal PUMP applied to the ferroelectric capacitor C is at the H level, and data is transmitted from the node Q. Output. Here, the level (voltage value) of the node Q is a value obtained by dividing the voltage of the pump signal PUMP by the capacitance values of the ferroelectric capacitor C and the capacitor C1.
[0060]
The change ΔV in the level of the node Q at this time depends on the change in the polarization direction of the ferroelectric capacitor C. This is because there is a difference in the amount of charge output from the ferroelectric capacitor C when there is a change in the polarization direction and when there is no change in the polarization direction. That is, the amount of charge output from the ferroelectric capacitor C is large when there is a large change in the polarization direction, and small when there is no change. For this reason, the voltage level of the node Q is as follows.
[0061]
FIG. 4B shows a case where the ferroelectric capacitor C has no change in the polarization direction. This is the case where there is no change in the polarization direction in the period T2 and the polarization direction in the period T3 in FIG. Equivalent to The relationship between the time at this time and the voltage at the node Q is as shown in FIG.
FIG. 4D shows the case where the ferroelectric capacitor C has a change in the polarization direction. This is the case where there is a change in the polarization direction in the period T2 and the polarization direction in the period T3 in FIG. Equivalent to The relationship between the time at this time and the voltage at the node Q is as shown in FIG.
[0062]
As can be seen from FIGS. 4C and 4E, the voltage difference at the node Q is ΔV when the polarization direction of the ferroelectric capacitor C is not changed. That is, the potential difference of the node Q is ΔV between the case where the retained data of the ferroelectric capacitor C is “1” and the case where it is “0”.
Therefore, as shown in FIGS. 4C and 4E, for example, if the reference voltage VREF is set in the middle of the potential difference ΔV, the voltage of the node Q can be binarized using the comparator 3.
[0063]
Here, if conditions such as the magnitude of the potential difference ΔV are satisfied, an inverter of a MOS transistor may be used instead of the comparator 3.
Next, based on the above description, the output of the node Q will be described with reference to FIG.
First, reading when the retained data is “1” will be described with reference to FIG.
[0064]
In this case, the transition is from the period T2 to the period T3 in FIG. 3, and the polarization direction is changed, so that the state shown in FIG. 4E is obtained, and the voltage of the node Q becomes a high potential. The voltage at the node Q is compared with the reference voltage VREF by the comparator 3, and the output Q1 becomes H level. At this time, since the clocked inverter 4 is in an operating state, its output Q2 becomes L level, and the output data DOUT output from the latch circuit 5 becomes H level.
[0065]
Next, reading when the retained data is “0” will be described with reference to FIG.
In this case, it is a transition from the period T2 to the period T3 in FIG. 3 and there is no change in the polarization direction, so that the state shown in FIG. 4C is obtained, and the voltage at the node Q becomes a low potential. The voltage at the node Q is compared with the reference voltage VREF by the comparator 3, and the output Q1 becomes L level. At this time, since the clocked inverter 4 is in an operating state, its output Q2 becomes H level, and the output data DOUT output from the latch circuit 5 becomes L level.
[0066]
The data read out from the ferroelectric capacitor C in this way is stored in the latch circuit 5, and then the data is held in the latch circuit 5 if the latch state is set.
Next, another operation example of the first embodiment will be described with reference to FIG.
[0067]
In this other operation example, two data are held by changing control by a control circuit (not shown).
In this case, the waveform of each part in the periods T1 to T4 in FIG. 10 is the same as the waveform of each part in the periods T1 to T4 in FIG. 2, and the operation of each part in the periods T1 to T4 is the period T1 to T4 in FIG. This is the same as the operation of each unit at T4.
[0068]
In the period T5 in FIG. 10, the on / off signals LTH and LTX in the period T2 in FIG. 2 are changed. That is, in this period T5, the on / off signal LTH is at the L level and the on / off signal LTHX is at the H level as shown in the figure.
Therefore, the MOS transistors M4 and M5 are off and the clocked inverter 4 is in an inoperative state, so that the output Q1 of the comparator 3 is not reflected on the output Q2 of the clocked inverter 4. As a result, the output data DOUT of the latch circuit 5 does not change. Therefore, in FIG. 2, the output data DOUT is at the H level, but in FIG. 10, it is not at the H level but remains at the L level.
[0069]
As apparent from the above, in the period T5 in FIG. 10, the ferroelectric memory 2 (ferroelectric capacitor C) holds the H level data, and the latch circuit 5 holds the L level as the output data DOUT. Thus, two data can be held simultaneously.
Such an operation is strong before the power is turned off when the power-off and power-on settings are different (for example, when the circuit power-on sequence or the initial state after power-on is specified). Writing data to the dielectric capacitor C has an advantage that the data can be reflected when the power is turned on.
[0070]
In addition, when the next data is known, the data of the ferroelectric capacitor C can be held to control other circuits, and the internal operation sequence can be rearranged. The effect of increasing the degree of freedom (for example, shortening the time, equalizing the load on the CPU, improving the use efficiency of the circuit) can be expected.
As described above, according to the first embodiment, the number of ferroelectric capacitors can be reduced, so that the yield in the manufacturing is improved.
[0071]
Further, according to the first embodiment, it is not necessary to apply a voltage to the ferroelectric capacitor after data is written, so that the lifetime of the ferroelectric capacitor can be extended.
Furthermore, according to the first embodiment, since the ferroelectric memory 2 and the latch circuit 5 can be physically separated, the degree of freedom in data processing can be increased.
[0072]
Next, a second embodiment of the present invention will be described with reference to FIG.
The nonvolatile memory device 1A according to the second embodiment is based on the first embodiment shown in FIG. 1, and a NOR circuit 21 and an inverter 22 as shown in FIG. 5 are added to this, and an on / off signal shown in FIG. DS and ON / OFF signals LTH and LTX are omitted, and control of a control circuit (not shown) is reduced.
[0073]
Here, according to FIGS. 2 and 3 showing the waveforms of the respective parts of the first embodiment, the on / off signal DS for controlling the on / off of the MOS transistor M1 can be obtained by negating the logical sum of the on / off signal SP and the pump signal PUMP. it can. An on / off signal LTH for controlling on / off of the MOS transistor M4 can be obtained by inverting the on / off signal SP. Further, an on / off signal LTX for controlling on / off of the MOS transistor M5 is the same as the on / off signal SP and can be used.
Therefore, in the second embodiment, as shown in FIG. 5, the on / off signal SP and the pump signal PUMP are supplied to the input side of the NOR circuit 21, and the output ds of the NOR circuit 21 is applied to the gate of the MOS transistor M1. I tried to do it. Further, the on / off signal SP is applied to the gate of the MOS transistor M2 and to the MOS transistor M5. Further, the on / off signal SP is inverted by the inverter 22 and the inverted signal lth is applied to the gate of the MOS transistor M4.
[0074]
Since the configuration of other parts of the second embodiment is the same as the configuration of the circuit of FIG. 1, the same components are denoted by the same reference numerals and description thereof is omitted.
Next, the operation of the second embodiment having such a configuration will be described with reference to FIGS.
FIG. 6 is a waveform diagram of each part during the normal operation of the second embodiment.
[0075]
In FIG. 6, an operation for writing polarization into the ferroelectric capacitor C is performed in a period T1, writing and outputting operations of input data DIN are performed in periods T2 and T3, and the written data is held in a period T4. Since these operations are the same as the operations in the periods T1 to T4 in FIG. 2 in the first embodiment, description of the operations is omitted.
[0076]
FIG. 7 is a waveform diagram of each part during the read operation of data held in the ferroelectric capacitor C in the second embodiment.
FIG. 7A shows the waveform of each part during the read operation when the retained data of the ferroelectric capacitor C is “1”, and FIG. 7B shows the read operation when the retained data is “0”. The waveform of each part at the time is shown.
[0077]
In FIG. 7, the power supply is turned off in a period T1, preparation is performed before reading the held data of the ferroelectric capacitor C in the period T2, and reading of the held data is performed in the period T3. Since these operations are the same as the operations in the periods T1 to T3 in FIG. 3 in the first embodiment, the description of the operations is omitted.
As described above, according to the second embodiment, since the control signal can be omitted as compared with the first embodiment, control of a control circuit (not shown) is reduced.
[0078]
By the way, in the first and second embodiments described above, data is held in the ferroelectric capacitor C, but instead, it may be operated as a simple latch circuit. In this case, the polarization write operation of the ferroelectric capacitor C may be excluded, such as “data latch”, “data input”, “data latch”, “data input”.
[0079]
In the first and second embodiments described above, the polarization write operation may be performed only when it is necessary to retain data in the ferroelectric capacitor C. In this case, the operation may be performed as “data latch”, “data input”, “data latch”, “polarization write”, “data input”, “data latch”.
[0080]
Next, a third embodiment of the present invention will be described with reference to FIG.
The nonvolatile memory device 1 according to the first embodiment shown in FIG. 1 can store 1-bit input data DIN, but cannot store multi-bit input data. On the other hand, in the nonvolatile memory device 1A according to the second embodiment shown in FIG. 5, a NOR circuit 21 and an inverter 22 are added in order to facilitate control.
[0081]
Therefore, the nonvolatile memory device according to the third embodiment enables storage processing of input data of a plurality of bits (in this example, 8 bits) and facilitates control in the same manner as in the second embodiment. It was made to realize.
Therefore, as shown in FIG. 8, the third embodiment includes eight nonvolatile storage devices 1 shown in FIG. 1 to store 8-bit input data DIN0, DIN1,. The NOR circuit 31 and the inverter 32 that are commonly used for the eight nonvolatile memory devices 1 are provided.
[0082]
In the third embodiment, various control signals supplied to the eight nonvolatile storage devices 1 are obtained using the on / off signal SP and the pump signal PUMP as they are, or using the NOR circuit 31 and the inverter 32. I did it.
More specifically, the on / off signal SP and the pump signal PUMP are used as they are as the on / off signal SP and the pump signal PUMP of the eight nonvolatile storage devices 1. Further, the NOR circuit 31 performs an operation of negating the logical sum of the ON / OFF signal SP and the pump signal PUMP, and the output of the NOR circuit 31 is used as each ON / OFF signal DS of the eight nonvolatile storage devices 1. . Further, the on / off signal SP is used as it is as the on / off signals LTX of the eight nonvolatile storage devices 1. Further, the on / off signal SP is inverted by the inverter 32, and this inverted signal is used as the on / off signal LTH of the eight nonvolatile memory devices 1.
[0083]
In the third embodiment having such a configuration, four operations as shown in FIG. 9 are realized by a combination of the on / off signal SP and the pump signal PUMP, which will be described.
According to FIG. 9, in the case of “data input operation”, the on / off signal SP is “0” and the pump signal PUMP is “0”, and in the case of “data latch operation”, “1” and “ “0”, “0” and “1” in the case of “data read operation”, and “1” and “1” in the case of “polarization write operation”.
[0084]
In the third embodiment, when each operation corresponding to each operation shown in FIG. 6 in the second embodiment is realized, the corresponding operation may be selected from the operations shown in FIG.
In the third embodiment, when realizing each operation corresponding to each operation shown in FIG. 7 in the second embodiment, the corresponding operation may be selected from the operations shown in FIG.
[0085]
Next, the structure of 4th Embodiment of this invention is demonstrated with reference to FIG.
The nonvolatile memory device 1B according to the fourth embodiment is based on the first embodiment shown in FIG. 1, and a MOS transistor M7 as a switch element that can be turned on and off as shown in FIG. A feedback circuit capable of feeding back the output data DOUT of 5 to the ferroelectric memory 2 is provided so that the output data DOUT can be rewritten to the ferroelectric memory 2.
[0086]
That is, the MOS transistor M7 is connected between the output terminal of the latch circuit 5 and the node Q of the ferroelectric memory 2. Further, an on / off signal DSR supplied to the control terminal 14 is applied to the gate of the MOS transistor M7, whereby the on / off control of the MOS transistor M7 is performed. Further, the comparator 3 includes N-type MOS transistors M21 and M22 formed of a differential pair, and P-type MOS transistors M23 and M24 forming a current mirror.
[0087]
In addition, since the structure of the other part of this 4th Embodiment is the same as that of the circuit of FIG. 1, the same code | symbol is attached | subjected about the same component, and the description is abbreviate | omitted.
Further, a feedback circuit for performing such rewriting may be added to the second embodiment shown in FIG.
Next, the operation of the fourth embodiment having such a configuration will be described with reference to FIGS.
[0088]
FIG. 12 is a waveform diagram of each part during normal operation of the fourth embodiment. During this normal operation, the on / off signal DSR is at L level, and the MOS transistor M7 is in the off state.
Accordingly, since the waveform diagram of each part in FIG. 12 is the same as the waveform diagram of each part during the normal operation in the first embodiment of FIG. 2, the normal operation of the fourth embodiment is the same as that of the first embodiment described above. It becomes the same as normal operation.
[0089]
FIG. 13 is a waveform diagram of each part at the time of reading data held in the ferroelectric capacitor C in the fourth embodiment. FIGS. 13A and 13B correspond to FIGS. 3A and 3B in which the first embodiment shows waveforms of respective parts at the time of reading data held in the ferroelectric capacitor C. FIG.
In the period T3 of FIG. 3, when data is read from the ferroelectric capacitor C, the polarization direction changes and remains changed thereafter. This means destructive readout, and the data “1” held in the ferroelectric capacitor C has disappeared. Therefore, in the fourth embodiment, as will be described later, the erased data is written once again in the ferroelectric capacitor C by using the MOS transistor M7.
[0090]
A period T1 in FIG. 13 is in a power-off state, a period T2 in FIG. 13 is a preparation state before reading data from the ferroelectric capacitor C (same as the latch state in the period T4 in FIG. 2), The data is being read. Further, as shown in FIG. 13, in the period T1 to T3, the on / off signal DSR is at the L level, and the MOS transistor M7 is in the off state.
[0091]
Therefore, since the waveforms of the respective parts in the periods T1 to T3 in FIG. 13 are the same as the waveforms of the respective parts in the periods T1 to T3 in FIG. 3, the operations of the respective parts in the periods T1 to T3 in the fourth embodiment This is the same as the operation of each part in the period T1 to T3 in the embodiment.
In the period T4 in FIG. 13, the polarization direction of the ferroelectric capacitor C is written. In the period T5 in FIG. 13, data is written into the ferroelectric capacitor C. In the period T6 in FIG. 13, the written data is written. Performs a latch operation.
[0092]
Here, in the period T5 in FIG. 13, as shown in the figure, the on / off signal DS is L level, the MOS transistor M1 is off, the on / off signal DSR is H level, and the MOS transistor M2 is on. For this reason, the output data DOUT latched by the latch circuit 5 is input as data held in the ferroelectric capacitor C.
[0093]
At this time, since the on / off signal LTH is at the L level and the on / off signal LTHS is at the H level, the power supply voltage VDD is not supplied to the clocked inverter 4 and the clocked inverter 4 is in a stopped state.
Since the output data DOUT is data read in the period T3 in FIG. 13 (data “1” held in the ferroelectric capacitor C), it can be seen that the erased data is rewritten.
[0094]
As described above, according to the fourth embodiment, when the data of the ferroelectric capacitor C is read, the read data can be rewritten (rewritten). Data can be retained.
Next, the structure of 5th Embodiment of this invention is demonstrated with reference to FIG.
The nonvolatile memory device 1C according to the fifth embodiment is based on the fourth embodiment shown in FIG. 11, and as shown in FIG. 14, the comparator 3 in FIG. 11 is omitted, and the latch circuit 5 includes MOS transistors M8, An electronic switch 15 made of M9 is included.
[0095]
As shown in FIG. 14, the latch circuit 5 includes a flip-flop in which inverters INV1 and INV2 are connected to each other, and an electronic switch 15 inserted in the loop of the flip-flop.
The electronic switch 15 is a combination of an N-type MOS transistor M8 and a P-type MOS transistor M9 as illustrated. The on / off signal LTX is applied to the gate of the MOS transistor M8, whereby the on / off control of the MOS transistor M8 is performed. Further, an on / off signal LTH is applied to the gate of the MOS transistor M9, whereby the on / off control of the MOS transistor M9 is performed.
[0096]
In the fifth embodiment, since the comparator 3 shown in FIG. 11 is omitted, the clocked inverter 4 directly performs the function of binarizing the voltage level of the node Q (determination of H level / L level). It is like that. Therefore, in this case, the reference voltage VREF at the time of the binarization is the threshold voltage of the clock driver 4.
[0097]
Next, the operation of the fifth embodiment having such a configuration will be described with reference to the drawings.
In the fifth embodiment, the circuit configuration differs from the fourth embodiment shown in FIG. 11 as described above, but the control signals supplied to the respective parts are the same as those in the fourth embodiment. For this reason, the signal waveform of each part at the time of normal operation of the fifth embodiment is as shown in FIG. 12, and the signal waveform of each part at the time of reading the retained data is as shown in FIG. Therefore, the following description of the operation is performed with reference to FIGS.
[0098]
First, the normal operation of the fifth embodiment will be described with reference to FIG.
In FIG. 12, in period T1, an operation of writing polarization into the ferroelectric capacitor C is performed, and an equivalent circuit thereof is as shown in FIG. In periods T2 and T3, input data DIN is written and output, and the equivalent circuit is as shown in FIG. Further, during the period T4, the written data is held, and an equivalent circuit thereof is as shown in FIG. Each of these operations will be described in turn below.
[0099]
First, in the period T1 in FIG. 12, since the on / off signal DS is at the L level, the MOS transistor M1 is in the off state, and the input data DIN is not input to the ferroelectric memory 2. At this time, since the on / off signal SP is at the H level, the MOS transistor M2 is in the on state, and the node Q is connected to the ground GND and becomes the L level. At this time, the pump signal PUMP is at the H level.
[0100]
In the period T1, the on / off signal LTH is at the L level and the on / off signal LTHS is at the H level. Therefore, the MOS transistors M4 and M5 are both turned off, the power supply voltage VDD is not supplied to the clocked inverter 4, and the MOS transistors M8 and M9 are both turned on, and the electronic switch 15 is turned on. Turn on. At this time, since the on / off signal DSR is at the L level, the MOS transistor M7 is off.
[0101]
Further, in the period T1, the output data DOUT is indefinite as illustrated because the previous state is not defined.
As described above, in the ferroelectric capacitor C, the terminal connected to the control terminal 12 is applied with the H level voltage by the pump signal PUMP, the terminal connected to the node Q is connected to the ground, and is set to the L level. Is applied. The polarization direction of the ferroelectric capacitor C at this time is indicated by an upward arrow “↑” as shown in FIG.
[0102]
As described above, in the period T1 in FIG. 12, the operation of writing the polarization in the direction of “↑” to the ferroelectric capacitor C is performed. At this time, since the MOS transistor M1 is off, the input data DIN may be either H level or L level as shown in FIG.
Next, in the periods T2 and T3 in FIG. 12, since the on / off signal DS is at the H level, the MOS transistor M1 is turned on, and the input data DIN is input to the ferroelectric memory 2. At this time, since the on / off signal SP becomes L level, the MOS transistor M2 is turned off. As a result, the level of the node Q becomes a level corresponding to the input data DIN. At this time, the pump signal PUMP is at the L level.
[0103]
In the periods T2 and T3, the on / off signal LTH is at the H level and the on / off signal LTHS is at the L level. Therefore, both the MOS transistors M4 and M5 are turned on, the power supply voltage VDD is supplied to the clocked inverter 4, and the MOS transistors M8 and M9 are both turned off. Is turned off. At this time, since the on / off signal DSR is at the L level, the MOS transistor M7 is off.
[0104]
An equivalent circuit in the periods T2 and T3 is as shown in FIG.
Here, in the period T2, since the input data DIN is at the H level, the node Q is at the H level. In the period T3, since the input data DIN is at L level, the node Q is at L level.
Now, when the input data DIN is at H level, the output data DOUT corresponding to this is as follows.
[0105]
At this time, since the clocked inverter 4 is in an operating state, it operates as an inverter. Therefore, the potential of the node Q is at the H level, and this potential exceeds the reference voltage VREF (the threshold voltage of the clocked inverter 4), so that the H level potential is inverted by the clocked inverter 4, and the clock The output Q1 of the inverter 4 becomes L level.
[0106]
Here, as shown in FIG. 16, the output Q1 of the clocked inverter 4 is supplied only to the inverter INV1 of the latch circuit 5, and since the output Q1 is at the L level, the output data DOUT which is the output of the latch circuit 5 Becomes H level.
Note that when the input data DIN is at the L level (in the case of the period T3), the output data DOUT corresponding to the input data DIN becomes the L level as illustrated.
[0107]
Next, the polarization direction of the ferroelectric capacitor C at this time will be examined.
When the input data DIN is at the H level as in the period T2, since the node Q is at the H level and the pump signal PUMP is at the L level, the polarization direction of the ferroelectric capacitor C is downward as illustrated.
On the other hand, when the input data DIN is at the L level as in the period T3, since the node Q is at the L level and the pump signal PUMP is at the L level, no potential difference occurs between both ends of the ferroelectric capacitor C. The polarization direction does not change from the state of the period T1 and remains upward.
[0108]
As is clear from the above description, in the period T2 in FIG. 12, the H level is input as the input data DIN, the output data DOUT is at the H level, and the ferroelectric capacitor C has the H level data. Charges with a downward polarization direction are retained.
On the other hand, in the period T3 in FIG. 12, the L level is input as the input data DIN, the output data DOUT is at the L level, and the ferroelectric capacitor C has an electric charge whose polarization direction is upward as the L level data. Retained.
[0109]
Thus, the data held in the ferroelectric capacitor C is stored without being erased even when the power is turned off.
Next, in the period T4 of FIG. 12, since the on / off signal DS is at the L level, the MOS transistor M1 is off and the input data DIN is not input to the ferroelectric memory 2. At this time, since the on / off signal SP is at the H level, the MOS transistor M2 is in the on state, and the node Q is connected to the ground GND and becomes the L level. At this time, the pump signal PUMP is at the L level.
[0110]
In the period T4, the on / off signal LTH is at the L level and the on / off signal LTHS is at the H level. Therefore, both the MOS transistors M4 and M5 are turned off, the clocked inverter 4 is inactive, the MOS transistors M8 and M9 are both turned on, and the electronic switch 15 is turned on. At this time, since the on / off signal DSR is at the L level, the MOS transistor M7 is turned off.
[0111]
An equivalent circuit in the period T4 is as shown in FIG.
As described above, since the pump signal PUMP is at the L level and the potential of the node Q is at the L level, both ends of the ferroelectric capacitor C are in a state where the voltage is at the L level and there is no potential difference. At this time, the node Q is at the L level, but the clocked inverter 4 is in an operation stop state, so that the potential of the node Q is not reflected in the output Q1 of the clocked inverter 4. Therefore, the data held in the latch circuit 5 does not change.
[0112]
Further, the output data DOUT of the latch circuit 5 is held in a state where there is no potential difference between both ends of the ferroelectric capacitor C. Of course, at this time, since there is no potential difference between both ends of the ferroelectric capacitor C, the polarization direction does not change.
In the example of FIG. 12, the latch operation of the period T4 is performed only after the period T2 of FIG. 12, but the latch operation of the period T4 may be performed after the period T3 of FIG. In this case, the latch is performed without changing the L level of the output data DOUT and the polarization direction of the ferroelectric capacitor C with the upward direction.
[0113]
Next, with reference to FIG. 13, a description will be given of the operation of reading the data held in the ferroelectric capacitor C.
Here, FIG. 13A is a waveform diagram of each part during the read operation when the retained data is “1”, and FIG. 13B is a waveform diagram of each part during the read operation when the retained data is “0”. It is a waveform diagram.
[0114]
In FIG. 13, a power supply is off in a period T1.
The period T2 is preparation before reading of the data held in the ferroelectric capacitor C (corresponding to the latch state in the period T4 in FIG. 12). However, if the on / off signal LTH is at the H level and the on / off signal LTX is at the L level, the stored data can be read. However, in this example, in order to reduce the number of combinations of signal settings, the same setting as the latch operation in the period T4 in FIG. 12 is performed.
[0115]
A period T3 indicates a read state of the retained data.
Next, each operation in the periods T1, T2, and T3 in FIG. 13 will be described in detail below.
First, in the period T1 in FIG. 13, since the power is off, the signals of the respective parts are all at the L level as shown in FIG. In this state, the polarization direction of the ferroelectric capacitor C is downward according to the description of FIG. 12 when data “1” is held, and upward when data “0” is held.
[0116]
Next, an operation in the period T2 in FIG. 13 will be described. An equivalent circuit at this time is as shown in FIG.
In this period T2, the on / off signal SP is at the H level, the on / off signal LTX is at the L level, and the other signals are at the L level. This is the same as the state of the period T4 in FIG.
[0117]
Therefore, in the period T2, both ends of the ferroelectric capacitor C are at the L level. The output data DOUT is in an indefinite state. Further, since both ends of the ferroelectric capacitor C are at the L level, the polarization direction does not change. The polarization direction remains downward when data “1” is held, and remains upward when data “0” is held.
[0118]
Here, the reason why both ends of the ferroelectric capacitor C are set to the L level in the period T2 is to set the fixed data (in this case, the L level voltage) for the same read condition of the retained data. This is because the polarization of the ferroelectric capacitor C is not destroyed.
Next, the operation in the period T3 in FIG. 13 will be described. An equivalent circuit at this time is as shown in FIG.
[0119]
In this period T3, since the on / off signal DS is at the L level, the MOS transistor M1 is off, and the input data DIN is not input to the ferroelectric memory 2. At this time, since the on / off signal SP is at the L level, the MOS transistor M2 is turned off. At this time, the pump signal PUMP is at the H level.
[0120]
In the period T3, the on / off signal LTH is at the H level and the on / off signal LTHS is at the L level. Therefore, both the MOS transistors M4 and M5 are turned on, the clocked inverter 4 is in an operating state, the MOS transistors M8 and M9 are both turned off, and the electronic switch 15 is turned off. At this time, since the on / off signal DSR is at the L level, the MOS transistor M7 is turned off.
[0121]
Accordingly, an equivalent circuit in the period T3 is as shown in FIG.
As described above, in the period T3 in FIG. 13, the pump signal PUMP is set to the H level, this is applied to the ferroelectric capacitor C, and data is read from the change in the potential of the node Q.
Next, the data output operation from the ferroelectric capacitor C will be described with reference to FIGS.
[0122]
First, a read operation in the case where retained data is “1” will be described with reference to FIG.
In the transition from the period T2 to the period 3 in FIG. 13A, since the polarization direction is changed, the state shown in FIG. 4E is obtained, and the level of the node Q becomes a high voltage. At this time, since the clocked inverter 4 is in an operating state, the high voltage is inverted by the clocked inverter 4 and its output Q1 becomes L level, and the output data DOUT of the latch circuit 5 becomes H level.
[0123]
Next, a read operation in the case where the retained data is “0” will be described with reference to FIG.
In the transition from the period T2 to the period 3 in FIG. 13B, since the polarization direction does not change, the state shown in FIG. 4C is obtained, and the level of the node Q becomes a low voltage. At this time, the low voltage is inverted by the clocked inverter 4, the output Q1 thereof becomes H level, and the output data DOUT of the latch circuit 5 becomes L level.
[0124]
Next, in the period T4 in FIG. 13, writing in the polarization direction of the ferroelectric capacitor C is performed. This is because the polarization direction data written in the ferroelectric capacitor C is destroyed during the period T3 in FIG. It is.
Next, in a period T5 in FIG. 13, data is written to the ferroelectric capacitor C. At this time, an equivalent circuit is as shown in FIG.
[0125]
In the period T5, since the on / off signal DS is at the L level, the MOS transistor M1 is off, and the input data DIN is not input to the ferroelectric memory 2. At this time, since the on / off signal SP is at the L level, the MOS transistor M2 is turned off. At this time, the pump signal PUMP is at the L level.
In the period T5, the on / off signal LTH is at the L level and the on / off signal LTHS is at the H level. Therefore, both the MOS transistors M4 and M5 are turned off, the clocked inverter 4 is inactive, the MOS transistors M8 and M9 are both turned on, and the electronic switch 15 is turned on. At this time, since the on / off signal DSR is at the H level, the MOS transistor M7 is turned on.
[0126]
Accordingly, an equivalent circuit in the period T5 is as shown in FIG.
Therefore, in the period T5, the output data DOUT latched by the latch circuit 5 is written into the ferroelectric capacitor C. That is, in the case of FIG. 13A, the H level voltage of the output data DOUT is applied to the ferroelectric capacitor C, and the downward polarization direction data is input. In the case of FIG. 13B, the L level voltage of the output data DOUT is applied to the ferroelectric capacitor C, and the upward polarization direction data remains as it is. As a result, the ferroelectric capacitor C is in a state before data is read.
[0127]
As described above, according to the fifth embodiment, when reading the data of the ferroelectric capacitor C, the read data can be rewritten (re-lit), and the data can be read any number of times. Data can be retained. Therefore, this fifth embodiment has the same functions as those of the fourth embodiment shown in FIG.
[0128]
Next, advantages of the fifth embodiment shown in FIG. 14 will be described in comparison with the fourth embodiment shown in FIG.
(1) The fifth embodiment consumes less power than the fourth embodiment.
In the fourth embodiment shown in FIG. 11, the driving is performed by the difference in driving ability between the clocked inverter 4 and the inverter INV <b> 2 of the latch circuit 5. However, in the fourth embodiment, as apparent from FIGS. 16 and 18, the clocked inverter 4 and the inverter INV <b> 2 are not electrically connected when the clocked inverter 4 is operated. For this reason, in the fourth embodiment, a current for driving the inverter INV2 becomes unnecessary, which can contribute to a reduction in power consumption.
(2) In the fifth embodiment, the comparator (see FIG. 11) used in the fourth embodiment is not necessary.
[0129]
In the fourth embodiment circuit shown in FIG. 11, the driving is performed by the difference in drive capability between the clocked inverter 4 and the inverter INV2 of the latch circuit 5, so that the MOS transistors M3- It is necessary to increase the transistor size of M6. When the transistor size is increased, the parasitic capacitance of the MOS transistors M3 to M6 increases, so that the stray capacitance C1 at the time of data reading increases (see FIG. 4).
[0130]
When the stray capacitance C1 increases, the output voltage of the node Q decreases when data is read, and the potential difference ΔV of the output voltage at the H level or L level decreases. For this reason, it becomes difficult to binarize the output voltage of the node Q with an inverter without using a comparator.
As can be seen, the output voltage can also be detected (binarized) by the inverter in the fourth embodiment, but the detection by the inverter is more stable in the fifth embodiment. For this reason, the comparator can be omitted in the fifth embodiment.
[0131]
Next, the structure of 6th Embodiment of this invention is demonstrated with reference to FIG.
The nonvolatile memory device 1D according to the sixth embodiment is based on the fifth embodiment shown in FIG. 14, and the clocked inverter 4 in FIG. 14 is replaced with an inverter 4A and an electronic switch 4B as shown in FIG. These are provided between the ferroelectric memory 2 and the latch circuit 5.
[0132]
As shown in the figure, the clocked inverter 4 shown in FIG. 14 has a CMOS inverter composed of MOS transistors M3 and M6. The MOS transistors M4 and M5 provided at both ends of the CMOS inverter are controlled to be turned on and off, and the power supply voltage VDD is set. By performing the supply control, the operation of the CMOS inverter can be controlled.
[0133]
Therefore, in the nonvolatile memory device 1D according to the sixth embodiment, the clocked inverter 4 shown in FIG. 14 is replaced with an inverter 4A composed of MOS transistors M3 and M6 and MOS transistors M4 and M5 as shown in FIG. The electronic switch 4B is replaced with a function substantially the same as that of the clocked inverter 4.
[0134]
That is, the inverter 4A is composed of a CMOS inverter in which an N-type MOS transistor M3 and a P-type MOS transistor M6 are combined, the power supply voltage VDD is applied to one end side thereof, and the other end side is connected to the ground GND. The input side of the inverter 4A is connected to the output side of the ferroelectric memory 2 shown in FIG. 14, and the output side of the inverter 4A is connected to one end side of the electronic switch 4B.
[0135]
The electronic switch 4B is configured by paralleling an N-type MOS transistor M4 and a P-type MOS transistor M5, one end of which is connected to the output side of the inverter 4A, and the other end is connected to the input side of the latch circuit 5. ing. An ON / OFF signal LTH is applied to the gate of the MOS transistor M4, so that the MOS transistor M4 is controlled to be turned on / off. Further, an on / off signal LTX is applied to the gate of the MOS transistor M5 to control the on / off of the MOS transistor M5.
[0136]
The remaining configuration of the sixth embodiment is not depicted in FIG. 20, but is the same as the configuration of the fifth embodiment shown in FIG.
Next, the structure of 7th Embodiment of this invention is demonstrated with reference to FIG.
The nonvolatile memory device 1E according to the seventh embodiment is based on the first embodiment shown in FIG. 1, and the clocked inverter 4 in FIG. 1 is replaced with an inverter 4A and an electronic switch 4B as shown in FIG. These are provided in series between the comparator 3 and the latch circuit 5.
[0137]
The basic concept of the configuration of the seventh embodiment is based on the same concept as that of the sixth embodiment shown in FIG.
As shown in FIG. 21, the inverter 4A is configured similarly to the inverter 4A shown in FIG. The input side of the inverter 4A is connected to the output side of the comparator 3 shown in FIG. 1, and the output side of the inverter 4A is connected to one end side of the electronic switch 4B. Furthermore, the electronic switch 4B shown in FIG. 21 is configured in the same manner as the electronic switch 4B shown in FIG.
[0138]
The remaining configuration of the seventh embodiment is not depicted in FIG. 21, but is the same as the configuration of the first embodiment shown in FIG.
The configuration in which the clocked inverter 4 is replaced with the inverter 4A and the electronic switch 4B is not only applied to the first embodiment as described above, but also applied to each embodiment shown in FIG. 5 and FIG. Also good.
[0139]
The first to seventh embodiments of the nonvolatile memory device of the present invention described above can be used as a nonvolatile memory in which data can be freely read and written. For this reason, said 1st Embodiment-7th Embodiment are applicable to the electronic device of this invention.
Then, the case where said 1st Embodiment-7th Embodiment is applied to the electronic device of this invention is demonstrated.
[0140]
In this case, the electronic device includes a nonvolatile memory in which data can be read and written, and various types of data can be rewritten in the nonvolatile memory. As the nonvolatile memory, the first to seventh embodiments of the nonvolatile memory device of the present invention are applied. According to such a configuration, it is possible to provide an electronic device that can exhibit the effects of the respective embodiments.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a nonvolatile memory device according to the present invention;
FIG. 2 is a waveform diagram showing a signal waveform example of each part during normal operation of the first embodiment.
FIG. 3 is a waveform diagram showing a signal waveform example of each part at the time of reading held data according to the first embodiment;
4 is an explanatory diagram for explaining reading of data from the ferroelectric capacitor of FIG. 1; FIG.
FIG. 5 is a circuit diagram showing a configuration of a second embodiment of a nonvolatile memory device according to the present invention;
FIG. 6 is a waveform diagram showing a signal waveform example of each part during normal operation of the second embodiment.
FIG. 7 is a waveform diagram showing a signal waveform example of each part at the time of reading held data according to the second embodiment.
FIG. 8 is a circuit diagram showing a configuration of a third embodiment of a nonvolatile memory device according to the present invention;
FIG. 9 is an explanatory diagram for explaining the operation of the third embodiment;
10 is a waveform diagram showing an example of a signal waveform of each part when explaining an operation for holding two data in the first embodiment of FIG. 1; FIG.
FIG. 11 is a circuit diagram showing a configuration of a fourth embodiment of a nonvolatile memory device according to the present invention;
FIG. 12 is a waveform diagram showing a signal waveform example of each part during normal operation of the fourth embodiment.
FIG. 13 is a waveform diagram showing an example of a signal waveform of each part at the time of reading held data according to the fourth embodiment.
FIG. 14 is a circuit diagram showing a configuration of a fifth embodiment of a nonvolatile memory device according to the present invention;
FIG. 15 is an equivalent circuit during normal operation of the fifth embodiment.
FIG. 16 is another equivalent circuit during normal operation of the fifth embodiment.
FIG. 17 is still another equivalent circuit during normal operation of the fifth embodiment.
FIG. 18 is an equivalent circuit when reading data according to the fifth embodiment;
FIG. 19 is an equivalent circuit when data is rewritten according to the fifth embodiment.
FIG. 20 is a circuit diagram showing a configuration of a sixth embodiment of a nonvolatile memory device according to the present invention;
FIG. 21 is a circuit diagram showing a configuration of a seventh embodiment of a nonvolatile memory device according to the present invention;
FIG. 22 is a circuit diagram showing a configuration of a conventional apparatus.
FIG. 23 is a waveform diagram showing a signal waveform example of each part during normal operation of the conventional apparatus.
FIG. 24 is a waveform diagram showing a signal waveform example of each part at the time of reading held data of the conventional apparatus.
FIG. 25 is a waveform diagram showing another signal waveform example of each part at the time of reading held data of the conventional apparatus.
[Explanation of symbols]
C ... Ferroelectric capacitors, M1-M9 ... MOS transistors, INV1, INV2, ... Inverters, DIN ... Input data, DOUT ... Output data, PUP ... Non-volatile memory device, 2 ... Ferroelectric memory, 3 ... Comparator, 4 ... Clocked inverter, 4A ... inverter, 4B ··· electronic switch, 5 ··· latch circuit, 6 ··· input terminal, 7 ··· output terminal, 15 ··· electronic switch.

Claims (12)

A ferroelectric memory including one ferroelectric capacitor and storing 1-bit input data;
A latch circuit capable of storing read data from the input data or the ferroelectric memory;
A switch that is openable and closable interposed between the ferroelectric memory and the latch circuit;
The switch is closed when storing the input data or read data from the ferroelectric memory in the latch circuit, and is opened after the storage is completed. A first switch that can be turned on and off to capture 1-bit input data; one ferroelectric capacitor; and a second switch that can be turned on and off to connect one end of the ferroelectric capacitor to the ground. A ferroelectric memory for storing
A latch circuit capable of storing read data from the input data or the ferroelectric memory;
A third switch which is interposed between the ferroelectric memory and the latch circuit and which can be turned on and off;
Predetermined on / off operations of the first switch, the second switch, and the third switch in accordance with the operation contents during the data read / write operation of the ferroelectric memory and the data latch operation of the latch circuit And a control circuit for controlling the non-volatile memory device. A ferroelectric switch including a first switch that can be turned on and off that captures 1-bit input data, one ferroelectric capacitor, and a second switch that can be turned on and off to connect one end of the ferroelectric capacitor to a ground; A ferroelectric memory that applies a control signal to the other end of the body capacitor and stores the input data in the ferroelectric capacitor;
A latch circuit capable of storing read data from the input data or the ferroelectric memory;
A clocked inverter that is interposed between the ferroelectric memory and the latch circuit and is capable of on / off control and capable of inverting data when turned on;
In the data read / write operation of the ferroelectric memory and the data latch operation of the latch circuit, the first switch, the second switch, and the clocked inverter are turned on and off according to the contents of the operation. And a control circuit for controlling the operation. 4. The nonvolatile memory device according to claim 1, further comprising a comparator that binarizes the input data or read data from the ferroelectric memory. 5. The control circuit includes:
A NOR circuit that performs an OR operation between an on / off signal for turning on and off the second switch and a control signal applied to the other end of the ferroelectric capacitor;
An inverter circuit for inverting the on / off signal,
4. The on / off control of the first switch is performed by an output signal of the NOR circuit, and the on / off control of the clocked inverter is performed by the on / off signal and an output signal of the inverter circuit. Item 5. The nonvolatile memory device according to Item 4. 2. The feedback circuit according to claim 1, further comprising a feedback circuit that feeds back output data of the latch circuit to the ferroelectric memory, wherein the output data of the latch circuit is rewritten to the ferroelectric memory. The non-volatile memory device according to claim 5. The nonvolatile memory device according to claim 3, wherein the clocked inverter is replaced with a CMOS inverter and an electronic switch. A plurality of the nonvolatile memory devices according to claim 3 or claim 4 are provided,
A NOR circuit that performs an OR operation between an on / off signal for turning on and off the second switch of the nonvolatile memory device and a control signal applied to the other end of the ferroelectric capacitor of the nonvolatile memory device. When,
An inverter circuit for inverting the on / off signal,
The on / off control of the first switch of the nonvolatile memory device is performed by the output signal of the NOR circuit, and the on / off of the clocked inverter of the nonvolatile memory device is controlled by the on / off signal and the output signal of the inverter circuit. A non-volatile memory device characterized in that each control is performed. A first switch that can be turned on and off to capture 1-bit input data; one ferroelectric capacitor; and a second switch that can be turned on and off to connect one end of the ferroelectric capacitor to the ground. A ferroelectric memory for storing
A latch circuit including a flip-flop in which two inverters are connected to each other and an electronic switch inserted in a loop of the flip-flop and capable of storing the input data or the read data from the ferroelectric memory; ,
A clocked inverter that is interposed between the ferroelectric memory and the latch circuit and is capable of on / off control and capable of inverting data when turned on;
In the data read / write operation of the ferroelectric memory and the data latch operation of the latch circuit, the first switch, the second switch, the clocked inverter, and the electronic switch according to the contents of the operation And a control circuit that controls a predetermined on / off operation of the non-volatile memory device. 10. A feedback circuit for feeding back output data of the latch circuit to the ferroelectric memory is further provided, and the output data of the latch circuit is rewritten to the ferroelectric memory. The non-volatile memory device described in 1. 11. The nonvolatile memory device according to claim 9, wherein the clocked inverter is replaced with a CMOS inverter and an electronic switch. In an electronic device that includes a nonvolatile memory that can freely read and write data, and that can read and write various data to and from the nonvolatile memory,
The electronic device comprising the nonvolatile memory device according to any one of claims 1 to 11.

Images