JP5724368B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device provided with a data holding circuit.

  The data holding circuit is a logic circuit that can temporarily store 1-bit information. For example, a flip-flop circuit or the like is known. In recent years, in a semiconductor device provided with a data holding circuit, a technique has been known in which a nonvolatile storage element (eg, a ferroelectric memory) is connected to a storage node in the circuit and data can be held even after power is turned off. (For example, refer to Patent Document 1).

JP 2004-87003 A

  In a semiconductor device, a nonvolatile memory element (ferroelectric memory) is provided in a data holding circuit. At this time, since the dummy memory cell corresponding to the ferroelectric memory cell and the peripheral circuit (write circuit, read circuit) of the ferroelectric memory are also formed in the data holding circuit, the circuit area increases, and the device May increase in size. Further, since the circuit area increases, the length of the wiring that connects the data holding circuits also increases, so that the signal transmission speed may decrease and the circuit operation speed may decrease.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce a circuit area and improve an operation speed in a semiconductor device including a data holding circuit.

The semiconductor device includes at least one or more nonvolatile memory cells and a latch circuit that stores write data to the memory cells or read data from the memory cells, and the memory cells and the latch circuits are arranged in an array. A plurality of nonvolatile memory circuits, a plurality of data holding circuits connected to each of the latch circuits in the plurality of nonvolatile memory circuits, and temporarily holding data, and the plurality of nonvolatile memory circuits And a dummy cell of the memory cell, which is disposed outside the memory cell .

  According to the semiconductor device, in the semiconductor device including the data holding circuit, the circuit area can be reduced and the operation speed can be improved.

FIG. 1 is a diagram illustrating a circuit configuration of a semiconductor device according to a comparative example. FIG. 2 is a timing chart showing the operation of the semiconductor device according to the comparative example. FIG. 3 is a diagram illustrating a layout of a semiconductor device according to a comparative example. FIG. 4 is a diagram illustrating a circuit configuration of the semiconductor device according to the first embodiment. FIG. 5 is a timing chart illustrating the data write operation of the semiconductor device according to the first embodiment. FIG. 6 is a timing chart (part 1) illustrating the data read operation of the semiconductor device according to the first embodiment. FIG. 7 is a timing chart (part 2) illustrating the data read operation of the semiconductor device according to the first embodiment. FIG. 8 is a diagram illustrating the layout of the semiconductor device according to the first embodiment. FIG. 9 is a diagram illustrating a comparison of the configuration of the semiconductor device according to the comparative example and the first embodiment.

(Comparative example)

  FIG. 1 is a diagram illustrating a circuit configuration of the semiconductor device 70, which is an example of a data holding circuit having a backup function. The semiconductor device 70 includes a D-type flip-flop circuit (corresponding to the data holding circuit described above) including a master latch circuit 72 and a slave latch circuit 82. The semiconductor device 70 also includes nonvolatile ferroelectric memories FC1 to FC4.

  The master latch circuit 72 includes a pair of inverters 74 and 76 connected in a ring shape. The input node of the master latch circuit 72 is connected to the data input terminal D via the inverter 78. A P-type transistor T1 is connected to the high power supply side of the inverter 78, an N-type transistor T2 is connected to the low power supply side, and clock signals CK and XCK are input to the gate terminals of the transistors. The output node of the master latch circuit 72 is connected to the input node of the subsequent slave latch circuit 82 via the transfer gate 80.

  Slave latch circuit 82 includes a pair of inverters 84 and 86 connected in a ring. A P-type transistor T3 is connected to the high power supply side of the inverter 84, an N-type transistor T4 is connected to the low power supply side, and activation signals XE and E are input to the gate terminals of the respective transistors. A P-type transistor T5 is connected to the high power supply side of the inverter 86, an N-type transistor T6 is connected to the low power supply side, and activation signals XE and E are input to the gate terminals of the respective transistors. The output node of the slave latch circuit 82 is connected to the data output terminal Q of the flip-flop circuit via the inverter 88.

  The ferroelectric memories FC1 to FC4 are variable capacitors including a ferroelectric sandwiched between a pair of electrodes, and are nonvolatile memories that store data according to the polarization state of the ferroelectric. One ends of the ferroelectric memories FC1 and FC3 are connected to the first plate line PL1, and one ends of the ferroelectric memories FC2 and FC4 are connected to the second plate line PL2. The first plate line PL1 and the second plate line PL2 supply a data write voltage and a read voltage to the ferroelectric memories FC1 to FC4.

  The other ends of the ferroelectric memories FC1 and FC2 are connected to each other, and the other connected end is connected to an input node of the slave latch circuit 82 (hereinafter referred to as a first storage node N1) via the transfer gate 90. . An N-type transistor T7 driven by the reset signal R is disposed between the input of the transfer gate 90 and the ground. With this configuration, the ferroelectric memories FC1 and FC2 store the signal of the first storage node N1.

  The other ends of the ferroelectric memories FC3 and FC4 are connected to each other, and the other connected end is connected to an output node of the slave latch circuit 82 (hereinafter referred to as a second storage node N2) via a transfer gate 92. . An N-type transistor T8 driven by the reset signal R is disposed between the input of the transfer gate 90 and the ground. With this configuration, the ferroelectric memories FC3 and FC4 store the signal of the second storage node N2.

  FIG. 2 is a timing chart showing the operation of the semiconductor device. The timing chart shown in FIG. 2 may be a timing chart of the semiconductor device shown in FIG. When the power supply is turned on and the power supply voltage rises to a predetermined value (Vdd), the operation mode shifts to the data read mode. At this time, the data stored in the ferroelectric memories FC1 to FC4 is read to the first storage node N1 and the second storage node N2 (slave latch circuit 82), and the state of the flip-flop circuit is before the previous power-off. Return to the state. Thereafter, the semiconductor device 70 performs a normal operation until the power is turned off again. Thereafter, when the power is turned off and the power supply voltage starts to drop, the operation mode shifts to the data write mode. At this time, the signals of the first storage node N1 and the second storage node N2 (slave latch circuit 82) are written into the ferroelectric memories FC1 to FC4. The ferroelectric memories FC1 to FC4 store the state of the flip-flop circuit until the next power-on.

  For example, consider the case in FIG. 1 where the signal at the first storage node N1 is at L (low) level and the signal at the second storage node N2 is at H (high) level. At the time of data writing, the signal level of the first plate line PL1 and the second plate line PL2 temporarily changes from L level to H level, and then becomes L level again. The polarization state of the ferroelectric memories FC1 to FC4 changes in a direction along the direction of the current flowing through the ferroelectric substance. For this reason, the ferroelectric memories FC1 to FC4 are in the polarization state indicated by the arrows in the drawing.

  At the time of data reading, the first plate line PL1 changes to H level, and the second plate line PL2 maintains L level. Here, as viewed from the first plate line PL1 on the high power supply side, the potential of the node connected to the ferroelectric in the inverted state rises quickly, and the potential of the node connected to the ferroelectric in the non-inverted state is Ascend late. In the polarization state shown in FIG. 1, the potential of the second storage node N2 rises faster than the potential of the first storage node N1. In this state, when the activation signal E is driven to activate the slave latch circuit 82, the signal levels of the first storage node N1 are amplified to the L level and the second storage node N2 is set to the H level. Return to. Even when the signals of the first storage node N1 and the second storage node N2 are opposite to those in FIG. 1, data can be written and read in the same manner as described above.

  Here, since the flip-flop circuit of the semiconductor device 70 includes the ferroelectric memories FC1 to FC4, the circuit area may be increased.

  FIG. 3 is a diagram showing a layout of the semiconductor device 70. A ferroelectric memory portion 96 in which the ferroelectric memories FC1 to FC4 are formed is provided outside the transistor circuit portion 94 where the transistors are formed. In the ferroelectric memory unit 96, a plurality of dummy cells DC made in the same manner as the ferroelectric memory cell FC are arranged so as to surround the ferroelectric memory cells FC constituting the ferroelectric memories FC1 to FC4. The dummy cell DC is formed in the same process as the ferroelectric memory cell FC in order to obtain a ferroelectric memory cell FC with stable characteristics. Therefore, the size of the ferroelectric memory unit 96 is obtained by adding the formation region of the dummy cell DC to the formation region of the ferroelectric memory cell FC.

  When the ferroelectric memory for backup is provided inside the flip-flop circuit, the circuit area increases as compared with the flip-flop circuit having no backup function. For example, as shown in FIGS. 1 and 3, four ferroelectric memory cells FC and twelve dummy cells DC are provided for a 1-bit flip-flop circuit. This increases the area of the flip-flop circuit and increases the size of the device. Further, when the area of the flip-flop circuit is increased, the length of the wiring connecting the flip-flop circuits is also increased, and the transmission speed of the signal is lowered, so that the operation speed is lowered.

  FIG. 4 is a diagram illustrating a circuit configuration of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a flip-flop circuit 10 and a nonvolatile memory circuit 20.

  The flip-flop circuit 10 has a clock terminal, a data input terminal D, a data output terminal Q, a preset terminal PR, and a clear terminal CL. The preset terminal PR is an example of an asynchronous first initialization terminal for initializing the flip-flop circuit 10 to the first state. The clear terminal CL is an example of an asynchronous second initialization terminal for initializing the flip-flop circuit 10 to a second state different from the first state. The output of the data output terminal Q is output to the logic circuit at the next stage and also input to the input side of the nonvolatile memory circuit 20. Output signals from the nonvolatile memory circuit 20 are input to the preset terminal PR and the clear terminal CL.

  The nonvolatile memory circuit 20 includes an inverter 22, a latch circuit 30, and ferroelectric memories F1 to F4 as examples of nonvolatile memory cells. The latch circuit 30 includes a pair of inverters 32 and 34 connected in a ring and two storage nodes (a first storage node N1 and a second storage node N2). The first storage node N1 is the first storage node N1. The second storage node N2 functions as the second terminal F1 of the latch circuit 30. The inverter 32 has a P-type transistor T1 on the high power supply side and an N-type transistor T2 on the low power supply side. Activation signals XE and E are input to the gate terminals of the transistors, respectively, and a P-type transistor T3 is connected to the high power supply side of the inverter 34, and an N-type transistor T4 is connected to the low power supply side. The activation signals XE and E are input to the gate terminals of the transistors, where the activation signals X and XE are both connected to the latch circuit 30. It is a control signal for causing the activatable.

  The first terminal F0 is connected to the input terminal IN of the nonvolatile memory circuit 20 via the inverter 22. The input terminal IN is connected to the data output terminal Q of the flip-flop circuit 10. A P-type transistor T5 is connected to the high power supply side of the inverter 22, an N-type transistor T6 is connected to the low power supply side, and activation signals XC and C are input to the gate terminals of the respective transistors. Here, the activation signals C and XC are both control signals for activating the inverter 22.

  The first terminal F0 is connected to the preset terminal PR of the flip-flop circuit 10. An N-type transistor T7 activated by the reset signal R is disposed between the first storage node N1 and the ground. The second terminal F1 is connected to the clear terminal CL of the flip-flop circuit 10. An N-type transistor T8 activated by the reset signal R is disposed between the second storage node N2 and the ground.

  The ferroelectric memories FC1 to FC4 may be substantially the same as or similar to the nonvolatile memory shown in FIG. One ends of the ferroelectric memories FC1 and FC3 are connected to the first plate line PL1, and one ends of the ferroelectric memories FC2 and FC4 are connected to the second plate line PL2. The other ends of the ferroelectric memories FC1 and FC2 are connected to each other, and the connection node is connected to the first storage node N1 of the latch circuit 30. Similarly, the other ends of the ferroelectric memories FC3 and FC4 are connected to each other, and the connection node is connected to the second storage node N2 of the latch circuit 30. The ferroelectric memories FC1 and FC2 store the signal of the first storage node N1, and the ferroelectric memories FC3 and FC4 store the signal of the second storage node N2.

  The basic operation of the semiconductor device 100 according to the first embodiment may be substantially the same as or similar to the operation illustrated in FIG. When the power is turned off, the state of the flip-flop circuit 10 is written into the ferroelectric memories FC1 to FC4 via the latch circuit 30. Until the power is next turned on, the state of the flip-flop circuit 10 is stored in the ferroelectric memories FC1 to FC4. When the power is turned on, data stored in the ferroelectric memories FC1 to FC4 is read to the latch circuit 30, and the flip-flop circuit 10 is reset to a predetermined state based on the read data.

  FIG. 5 is a timing chart showing the data write operation. In the initial state, the activation signal C of the inverter 22 is at L level, and the nonvolatile memory circuit 20 does not accept input. Further, since the reset signal R is at the H level and the transistors T7 and T8 connected to the ground potential are in the on state, the signals at the first storage node N1 and the second storage node N2 are at the L level. Further, the activation signal E, the first plate signal PL1, and the second plate signal PL2 of the latch circuit 30 are also at the L level. This suppresses unscheduled data writing to the ferroelectric memories FC1 to FC4 in the initial state.

  When shifting to the data write mode, the reset signal R becomes L level, and the first storage node N1 and the second storage node N2 are in a floating state. Subsequently, the activation signal C of the inverter 22 becomes H level, and the output data from the flip-flop circuit 10 is inverted by the inverter 22 and input to the latch circuit 30. Subsequently, the activation signal E of the latch circuit 30 also becomes H level, and the latch circuit 30 is activated. Thereby, the first storage node N1 becomes a signal of either H level or L level, and the second storage node N2 becomes a signal opposite to the first storage node N1. Hereinafter, a state in which the first storage node N1 (first terminal F0) is at the H level and the second storage node N2 (second terminal F1) is at the L level is referred to as a “0” state. A state in which the first storage node N1 (first terminal F0) is at the L level and the second storage node N2 (second terminal F1) is at the H level is referred to as a “1” state.

  After the latch circuit 30 is activated by the activation signal E of the latch circuit 30, the first plate signal PL1 and the second plate signal PL2 become H level, and become L level again after a predetermined time. As a result, the polarization states of the ferroelectric memories FC1 to FC4 change according to the signals of the first storage node N1 and the second storage node N2, and data is written. For example, when the latch circuit 30 is in the “0” state, the ferroelectric memories FC1 to FC4 are in a polarization state as shown in FIG. When the latch circuit 30 is in the “1” state, the polarization states of the ferroelectric memories FC1 to FC4 are opposite to those in FIG. 4 (not shown).

  FIG. 6 is a timing chart showing the read operation in the “0” state. In the initial state, as in the write operation, the reset signal is at the H level and the other signals are at the L level. At the time of data reading, activation signal C of inverter 22 is not activated and is maintained at the L level. First, after the reset signal R changes to L level, the first plate signal PL1 changes to H level for a certain time. Then, the activation signal E of the latch circuit 30 changes to the H level while the first plate signal PL1 is at the H level.

  When the first plate signal PL1 rises to the H level, a current is supplied to the first storage node N1 and the second storage node N2 via the ferroelectric memories FC1 and FC3. When viewed from the first plate line PL1 of the high power supply, the potential of the node connected to the ferroelectric in the inversion state rises quickly, and the potential of the node connected to the ferroelectric in the non-inversion state rises late. Therefore, in the polarization state shown in FIG. 4, the potential of the first storage node N1 rises faster than the potential of the second storage node N2. When the activation signal E is driven in this state to activate the latch circuit 30, the signal level is amplified to the H level for the first storage node N1 and the L level for the second storage node N2. Therefore, as shown in FIG. 6, the signal level of the first terminal F0 is H, the signal level of the second terminal F1 is L, and the “0” state is read out.

  Next, when the first plate signal PL1 changes to L level, the second plate signal PL2 rises to H level in response thereto. As a result, a voltage in the same direction as the previous data write is applied to the ferroelectric memories FC1 to FC4, and if there is data destroyed at the time of data read, it is overwritten (rewritten) as before.

  FIG. 7 is a timing chart showing the read operation in the “1” state. The operation waveforms of the activation signal C, the reset signal R of the inverter 22, the activation signal E of the latch circuit 30, the first plate signal PL1, and the second plate signal PL2 are the same as in the case of “0” reading (FIG. 6). It is.

  In the case of “1” reading, since the ferroelectric memories FC1 to FC4 are in a state opposite to the polarization state shown in FIG. 4, the potential of the second storage node N2 rises earlier than the potential of the first storage node N1. . When the activation signal E is driven in this state to activate the latch circuit 30, the signal level is amplified to the L level for the first storage node N1 and to the H level for the second storage node N2. Therefore, as shown in FIG. 7, the signal level of the first terminal F0 is L, the signal level of the second terminal F1 is H, and the “1” state is read out. Next, when the first plate signal PL1 changes to the L level, the second plate signal PL2 rises to the H level in response thereto, and the data is rewritten.

  Data (either “0” state or “1” state) read from the ferroelectric memories FC 1 to FC 4 to the latch circuit 30 is supplied to the reset terminal of the flip-flop circuit 10. In the “0” state, an H level signal is supplied to the preset terminal PR of the flip-flop circuit 10 and an L level signal is supplied to the clear terminal CL, and the preset terminal PR is activated. Thus, the flip-flop circuit 10 outputs an L level signal “0”. On the other hand, in the “1” state, an L level signal is supplied to the preset terminal PR of the flip-flop circuit 10 and an H level signal is supplied to the clear terminal CL, and the clear terminal CL is activated. As a result, the flip-flop circuit 10 outputs an H level signal “1”.

  As described above, the semiconductor device 100 according to the first embodiment includes the flip-flop circuit 10 having a nonvolatile memory function. The semiconductor device 100 includes a plurality of 1-bit data storage circuits each including a flip-flop circuit 10 and a nonvolatile memory circuit 20 as a set.

  FIG. 8 is a diagram showing a layout of the nonvolatile memory circuit 20. A plurality of ferroelectric memory cells FC are formed in each of the plurality of ferroelectric formation regions 40. Between the two ferroelectric formation regions 40, either an N-channel transistor formation region (Nch-TR portion 42) or a P-channel transistor formation region (Pch-TR portion 44) is alternately formed. ing. The transistors formed in the Nch-TR unit 42 and the Pch-TR unit 44 are transistors that constitute the latch circuit 30. That is, as illustrated, a plurality of nonvolatile memory circuits 20 including ferroelectric memory cells FC and latch circuits 30 are arranged in an array. A dummy cell DC is formed outside the region (reference numeral 45 in the figure) where the ferroelectric memory cells FC and the latch circuits 30 are arranged in an array so as to surround the area (reference numeral 46 in the figure).

  In the first embodiment, the ferroelectric memory cells FC and the latch circuits 30 included in the nonvolatile memory circuit 20 for a plurality of bits (for example, several kilobytes to several megabytes) are arranged in an array so that the entire circuit area is obtained. As reduced. Also, unlike the example shown in FIG. 3, since the dummy cells DC are shared by the plurality of nonvolatile memory circuits 20, the number of dummy cells per the same number of bits is reduced.

  FIG. 9 is a diagram illustrating a comparison of the configuration of the semiconductor device according to the first embodiment. FIG. 9A schematically shows the configuration of the comparative example, and FIG. 9B schematically shows the configuration of the first embodiment. As shown in FIG. 9A, in the semiconductor device 70 according to the comparative example, a logic region 52 in which various logic circuits including the flip-flop circuit 10 are connected to each other is provided in the semiconductor chip 50. Yes. Further, as shown in FIG. 9B, in the semiconductor device 100 according to the first embodiment, the nonvolatile memory area 54 in which the plurality of nonvolatile memory circuits 20 are arranged outside the logic area 52 in the semiconductor chip 50. Is provided. The nonvolatile memory circuit 20 is not included in the logic circuit in the logic area 52.

  In FIG. 9A, since the ferroelectric memory cell FC is provided in the flip-flop circuit 0, the circuit area of the flip-flop circuit 10 becomes large. In addition, the area of the logic region 52 in which the flip-flop circuit 10 is arranged is increased, and the wiring 60 connecting the plurality of flip-flop circuits 10 is also increased, so that the operation speed is reduced.

  On the other hand, in the first embodiment, the flip-flop circuit 10 does not include the ferroelectric memory cell FC (the nonvolatile memory circuit 20 including the ferroelectric memory cell FC is provided around the flip-flop circuit 10. ). For this reason, the circuit area of the flip-flop circuit 10 is smaller than that of the comparative example. Therefore, the area of the logic region 52 is also smaller than that of the comparative example. In the nonvolatile memory area 54, since the dummy cells DC are shared by the plurality of nonvolatile memory circuits 20 as described above, the number of dummy cells DC is smaller than that in the comparative example. From the above, in the semiconductor device 100 according to the first embodiment, the circuit area as a whole can be reduced as compared with the comparative example.

  Further, according to the semiconductor device 100 according to the first embodiment, since the circuit area of the flip-flop circuit 10 is smaller than that of the comparative example, the length of the wiring 60 that connects a plurality of logic circuits including the flip-flop circuit 10 is It can be made shorter than the comparative example. Therefore, compared with the comparative example, it is possible to suppress the influence of a decrease in signal transmission speed due to wiring delay and improve the operation speed. As described above, according to the semiconductor device according to the first embodiment, the circuit area can be reduced and the operation speed can be improved.

  The configuration of the first embodiment is particularly suitable when the logic circuit in the logic region 52 is formed of standard cells and the semiconductor device 100 is formed using automatic placement and routing. This is because in automatic placement and routing, the layout of the wiring is automatically determined, and therefore it is preferable to reduce the circuit area of each logic circuit in order to shorten the length of the wiring between the logic circuits. The nonvolatile storage area 54 may not be formed by a standard cell but may be formed by a hard macro or the like.

  In the first embodiment, the flip-flop circuit 10 is an example of a volatile data holding circuit capable of temporarily storing 1-bit information. The data holding circuit is not limited to the specific configuration of this embodiment as long as it has the above function.

  In the first embodiment, the latch circuit 30 included in the nonvolatile memory circuit 20 has two roles of a writing circuit and a reading circuit for the nonvolatile memories FC1 to FC4. The latch circuit 30 as the writing circuit writes the data output from the flip-flop circuit 10 as the data holding circuit to the ferroelectric memory cells FC1 to FC4 in accordance with the potential change of the plate lines (PL1, PL2). The latch circuit 30 as a read circuit reads data from the ferroelectric memory cells FC1 to FC4 according to the potential change of the plate lines (PL1, PL2), and outputs it to the flip-flop circuit 10 as a data holding circuit. At this time, the latch circuit 30 amplifies the potential change of the storage node based on the data stored in the nonvolatile memories FC1 to FC4 to either an H level signal or an L level signal and outputs the amplified signal. Thereby, it is possible to suppress the influence of noise and the like based on the wiring capacity at the time of signal transmission from the nonvolatile memory circuit 20 to the flip-flop circuit 10, and to form the nonvolatile storage area 54 outside the logic area 52. Becomes easy. In this embodiment, an example in which ferroelectric memories are used as the nonvolatile memories FC1 to FC4 has been described. However, other nonvolatile memories may be used.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Flip-flop circuit 20 Nonvolatile memory circuit 30 Latch circuit 50 Semiconductor chip 52 Logic area 54 Nonvolatile memory area 100 Semiconductor device FC Ferroelectric memory cell DC Dummy cell

Claims (5)

A plurality of nonvolatile memory cells, and a plurality of latch circuits that store write data to the memory cells or read data from the memory cells, the memory cells and the latch circuits being arranged in an array A non-volatile memory circuit of
A plurality of data holding circuits connected to each of the latch circuits in the plurality of nonvolatile memory circuits and temporarily holding data;
A dummy cell of the memory cell disposed outside the plurality of nonvolatile memory circuits;
A semiconductor device comprising: A plurality of nonvolatile memory cells, and a plurality of latch circuits that store write data to the memory cells or read data from the memory cells, the memory cells and the latch circuits being arranged in an array A non-volatile memory circuit of
A plurality of data holding circuits connected to each of the latch circuits in the plurality of nonvolatile memory circuits and temporarily holding data;
A logic region including a plurality of logic circuits including the data holding circuit and not including the nonvolatile memory circuit;
A non-volatile area located around the logic area and including the non-volatile memory circuits;
A semiconductor device comprising: a. A plurality of nonvolatile memory cells, and a plurality of latch circuits that store write data to the memory cells or read data from the memory cells, the memory cells and the latch circuits being arranged in an array A non-volatile memory circuit of
A plurality of data holding circuits connected to each of the latch circuits in the plurality of nonvolatile memory circuits and temporarily holding data;
With
The latch circuit includes a first terminal connected to the first nonvolatile memory cell, and a second terminal connected to the second nonvolatile memory cell,
The data holding circuit includes a data output terminal for outputting data held by the data holding circuit, an asynchronous first initialization terminal for initializing the data holding circuit to a first state, and a second data holding circuit. An asynchronous second initialization terminal that initializes to the state of
The data output terminal is connected to the first terminal of the latch circuit through an inverter, the first initialization terminal is connected to the first terminal of the latch circuit, and the second initialization terminal is connected to the latch circuit. A semiconductor device connected to the second terminal . A logic region including a plurality of logic circuits including the data holding circuit and not including the nonvolatile memory circuit;
A non-volatile region located around the logic region and including the plurality of non-volatile memory circuits and the dummy cells ;
The semiconductor device according to claim 1 , comprising: The latch circuit includes a first terminal connected to the first nonvolatile memory cell, and a second terminal connected to the second nonvolatile memory cell,
The data holding circuit includes a data output terminal for outputting data held by the data holding circuit, an asynchronous first initialization terminal for initializing the data holding circuit to a first state, and a second data holding circuit. An asynchronous second initialization terminal that initializes to the state of
The data output terminal is connected to the first terminal of the latch circuit through an inverter, the first initialization terminal is connected to the first terminal of the latch circuit, and the second initialization terminal is connected to the latch circuit. The semiconductor device according to claim 1 , wherein the semiconductor device is connected to the second terminal.

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