JP2005039590A

JP2005039590A - Power supply control circuit, mobile communication device, and power supply control method therefor

Info

Publication number: JP2005039590A
Application number: JP2003275279A
Authority: JP
Inventors: Makoto Akitani; 誠秋谷
Original assignee: NEC Saitama Ltd
Current assignee: NEC Saitama Ltd
Priority date: 2003-07-16
Filing date: 2003-07-16
Publication date: 2005-02-10
Anticipated expiration: 2023-07-16
Also published as: JP3896102B2

Abstract

<P>PROBLEM TO BE SOLVED: To minimize the current consumption even in the case of abnormality in a power supply control circuit and realize automatic restoration to a normal operation in the case that a normal current is restored after flow of an abnormal current. <P>SOLUTION: A Pch FET 3 performs switching such that a voltage is applied to a power amplifier 1 only when transmission of a communication device having the power amplifier 1 is performed. A source voltage detection part 4 monitors a source voltage of the Pch FET 3. A differential amplifier 5 detects a potential difference between a drain voltage of the Pch FET 3 and the source voltage monitored by the source voltage detection part 4. A gate voltage adjustment circuit 6 adjusts a gate voltage of the Pch FET 3 on the basis of the source voltage obtained from the source voltage detection part 4, the gate-source voltage of the Pch FET, and characteristics of a resistance between the drain and the source in the case that a voltage obtained from the differential amplifier 5 exceeds a preliminarily determined voltage, and thus the resistance between the drain and the source is varied so as not to cause a certain current or more to flow to the power amplifier 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は電源制御回路に関し、特に移動通信機器等に用いられる電源制御回路に関する。 The present invention relates to a power supply control circuit, and more particularly to a power supply control circuit used for a mobile communication device or the like.

図３は従来の移動通信機器における電源制御回路の一例を示すブロック図である。図３を参照すると、電源制御回路は、高周波信号を増幅する電力増幅器１と、電池２と、電池２から電力増幅器１への電圧供給をスイッチングするＰチャネル電界効果トランジスタ(ＰｃｈＦｉｅｌｄＥｆｆｅｃｔＴｒａｎｓｉｓｔｏｒ、以下、ＰｃｈＦＥＴと呼称)３と、ＰｃｈＦＥＴ３のソース電圧とドレイン電圧の電位差を検出する差動増幅器５と、ソース電圧とドレイン電圧の電位差と予め決められた閾値電圧とを比較し比較結果を出力する比較器７と、電力増幅器１に送信時のみ電圧が印加されるような制御信号と比較器７の出力信号とを入力しＰｃｈＦＥＴ３のゲート端子へ入力に応じた信号を出力するＯＲ回路８とを備える。 FIG. 3 is a block diagram showing an example of a power supply control circuit in a conventional mobile communication device. Referring to FIG. 3, the power supply control circuit includes a power amplifier 1 that amplifies a high-frequency signal, a battery 2, and a P-channel field effect transistor (Pch Field Effect Transistor) that switches voltage supply from the battery 2 to the power amplifier 1. 3), a differential amplifier 5 that detects the potential difference between the source voltage and the drain voltage of the PchFET 3, and a comparison that compares the potential difference between the source voltage and the drain voltage with a predetermined threshold voltage and outputs a comparison result. And an OR circuit 8 for inputting a control signal for applying a voltage to the power amplifier 1 only during transmission and an output signal of the comparator 7 and outputting a signal corresponding to the input to the gate terminal of the PchFET 3. .

以下に、図３に示す電源制御回路の動作を説明する。電力増幅器１に異常に大きい電流が流れていない場合は、（以下、正常な場合と呼称）ＰｃｈＦＥＴ３のソース−ドレイン間の抵抗値は十分に低いため、ＰｃｈＦＥＴ３のソース−ドレイン間の電位差は小さくなる。よって差動増幅器５より出力される電圧も小さい電圧となり、比較器７の＋入力端子に入力される。比較器７の−入力端子には、予め電力増幅器１が異常となった場合のＰｃｈＦＥＴ３のソース−ドレイン間の電位差から決められた閾値電圧が入力されている。比較器７の−入力端子に入力される電圧が閾値電圧より低いため、比較器７の出力端子にはＬレベル電圧が出力される。電力増幅器制御信号は送信時Ｌレベル電圧が出力されるため、ＯＲ回路８の出力はＬレベル電圧（＝０Ｖ）となり、ＰｃｈＦＥＴ３のソース−ドレイン間の抵抗値は最小となる。 The operation of the power supply control circuit shown in FIG. 3 will be described below. When an abnormally large current does not flow through the power amplifier 1 (hereinafter referred to as normal), the resistance value between the source and drain of the PchFET 3 is sufficiently low, so that the potential difference between the source and drain of the PchFET 3 becomes small. . Therefore, the voltage output from the differential amplifier 5 is also a small voltage and is input to the + input terminal of the comparator 7. A threshold voltage determined in advance from the potential difference between the source and drain of the PchFET 3 when the power amplifier 1 becomes abnormal is input to the negative input terminal of the comparator 7. Since the voltage input to the negative input terminal of the comparator 7 is lower than the threshold voltage, an L level voltage is output to the output terminal of the comparator 7. Since the L level voltage is output during transmission of the power amplifier control signal, the output of the OR circuit 8 becomes the L level voltage (= 0 V), and the resistance value between the source and drain of the PchFET 3 is minimized.

一方、電力増幅器１に異常に大きい電流が流れている場合は、（以下、異常な場合と呼称）差動増幅器５の出力電圧は、大きくなるため、比較器７の出力はＨレベルとなり、かつＯＲ回路８の出力電圧もＨレベル電圧（＝ＯＲ回路８の電源電圧）となるため、ＰｃｈＦＥＴ３のソース−ドレイン間の抵抗値は最大となり電力増幅器１へは電圧供給されなくなる。 On the other hand, when an abnormally large current flows through the power amplifier 1 (hereinafter referred to as an abnormal case), the output voltage of the differential amplifier 5 increases, so that the output of the comparator 7 becomes H level, and Since the output voltage of the OR circuit 8 is also the H level voltage (= the power supply voltage of the OR circuit 8), the resistance value between the source and the drain of the PchFET 3 becomes maximum, and no voltage is supplied to the power amplifier 1.

本発明に関連する従来の技術として、ＦＥＴのオフ状態のときに入力抵抗，入力コンデンサにより突入電流を制限し、その後ＦＥＴをオンさせて所要の電流を確保し、且つ過電流時にはＦＥＴのソース−ドレイン間電圧に基づく電圧検出・制御回路の作用により、ゲート電圧制御トランジスタを介してＦＥＴを抑制方向に動作させて、過電流を制限する技術が開示されている(例えば、特許文献１参照)。 As a conventional technique related to the present invention, an inrush current is limited by an input resistance and an input capacitor when the FET is in an OFF state, and then the FET is turned on to secure a required current. A technique is disclosed in which an overcurrent is limited by operating a FET in a suppression direction via a gate voltage control transistor by the action of a voltage detection / control circuit based on a drain-to-drain voltage (see, for example, Patent Document 1).

特開平２−１１１２２３号公報（第２頁、作用）JP-A-2-111223 (page 2, action)

上述した従来の電源制御回路では、異常時に、電力増幅器の電圧供給を止める手段を用いていたが、電力増幅器の電流が正常復帰した場合にも電圧供給が止まっており、システム復帰のためには一度電源を切る等の手段が必要であった。このような問題を解決するために正常復帰した場合には自動的に電力増幅器へ電圧供給が開始出来るような電源制御回路の発明が求められている。 In the conventional power supply control circuit described above, means for stopping the voltage supply of the power amplifier at the time of abnormality is used. However, the voltage supply is stopped even when the current of the power amplifier returns to the normal state. A means to turn off the power once was necessary. In order to solve such a problem, there is a need for an invention of a power supply control circuit that can automatically start voltage supply to a power amplifier when normal operation is restored.

本発明は上述した課題に鑑み成されたもので、その目的は、異常時でも消費電流が最小限に抑えられ、また、異常電流が流れた場合でものちに正常電流に復帰した場合には、正常動作に自動的に復旧できる電源制御回路および移動通信機器ならびにその電源制御方法を提供することにある。 The present invention has been made in view of the above-described problems, and its purpose is to minimize current consumption even in the event of an abnormality, and when returning to normal current after an abnormal current flows, It is an object of the present invention to provide a power supply control circuit, a mobile communication device, and a power supply control method thereof that can automatically restore normal operation.

請求項１に記載の本発明は、高周波信号を増幅する電力増幅器を有する通信機器の送信時のみ前記電力増幅器へ電圧を印加するようにスイッチングを行うＰチャネル電界効果トランジスタと、前記Ｐチャネル電界効果トランジスタのドレイン電圧とソース電圧との電位差を検出する電位差検出手段と、前記電位差検出手段より得られた電圧が予め決められた電圧を超えた場合に前記Ｐチャネル電界効果トランジスタのソース電圧と前記Ｐチャネル電界効果トランジスタのゲート−ソース電圧およびドレイン−ソース間抵抗の特性に基づき前記Ｐチャネル電界効果トランジスタのゲート電圧を調整し前記ドレイン−ソース間抵抗を可変することにより高周波信号を増幅する電力増幅器に一定以上の電流が流れないようにするゲート電圧調整手段とを備える。 The present invention described in claim 1 is a P-channel field effect transistor that performs switching so that a voltage is applied to the power amplifier only during transmission of a communication device having a power amplifier that amplifies a high-frequency signal, and the P-channel field effect A potential difference detecting means for detecting a potential difference between a drain voltage and a source voltage of the transistor; and a source voltage of the P-channel field effect transistor and the P when the voltage obtained from the potential difference detecting means exceeds a predetermined voltage. A power amplifier that amplifies a high-frequency signal by adjusting a gate voltage of the P-channel field-effect transistor based on characteristics of a gate-source voltage and a drain-source resistance of the channel field-effect transistor and varying the drain-source resistance Gate voltage adjustment means to prevent current above a certain level from flowing Equipped with a.

請求項２に記載の本発明は、請求項１において、前記ゲート電圧調整手段は、前記電位差検出手段の出力と予め設定された閾値とを比較し正常／異常を判断し異常時には前記Ｐチャネル電界効果トランジスタのゲート端子に前記ドレイン−ソース間抵抗が大きくなるような電圧を出力する比較器と、前記ソース電圧を入力すると共に前記電位差検出手段から出力されるドレイン電圧とソース電圧との電位差により決められた電圧を出力する電圧発生器と、前記電位差検出手段の出力電圧が閾値より大きくなればこの電位差検出手段の出力に応じた電圧を前記電圧発生器から出力させるために切り替える切替部とを備える。 According to a second aspect of the present invention, in the first aspect, the gate voltage adjusting unit compares the output of the potential difference detecting unit with a preset threshold value to determine normality / abnormality. A comparator that outputs a voltage that increases the drain-source resistance to the gate terminal of the effect transistor, and a source voltage that is input and that is determined by a potential difference between the drain voltage and the source voltage that is output from the potential difference detection means. A voltage generator for outputting the generated voltage, and a switching unit that switches to output a voltage corresponding to the output of the potential difference detection means from the voltage generator when the output voltage of the potential difference detection means exceeds a threshold value. .

請求項３に記載の本発明は、請求項１または２において、前記電位差検出手段は差動増幅器である。 According to a third aspect of the present invention, in the first or second aspect, the potential difference detecting means is a differential amplifier.

請求項４に記載の本発明は、高周波信号を増幅する電力増幅器と、前記電力増幅器を有する通信機器の送信時のみ前記電力増幅器へ電圧を印加するようにスイッチングを行うＰチャネル電界効果トランジスタと、前記Ｐチャネル電界効果トランジスタのソース端子に接続し前記電力増幅器へ電圧を供給する電池と、前記Ｐチャネル電界効果トランジスタのソース電圧をモニターするソース電圧検出部と、前記Ｐチャネル電界効果トランジスタのドレイン電圧と前記ソース電圧検出部でモニターしたソース電圧との電位差を検出する差動増幅器と、前記差動増幅器から得た電圧が予め決められた電圧を超えた場合に前記ソース電圧検出部から得たソース電圧と前記Ｐチャネル電界効果トランジスタのゲート−ソース電圧およびドレイン−ソース間抵抗の特性に基づき前記Ｐチャネル電界効果トランジスタのゲート電圧を調整し前記ドレイン−ソース間抵抗を可変して前記電力増幅器に一定以上の電流が流れないようにするゲート電圧調整回路とを備える。 The present invention according to claim 4 is a power amplifier that amplifies a high-frequency signal, a P-channel field effect transistor that performs switching so as to apply a voltage to the power amplifier only during transmission of a communication device having the power amplifier, A battery connected to the source terminal of the P-channel field effect transistor to supply a voltage to the power amplifier, a source voltage detector for monitoring a source voltage of the P-channel field effect transistor, and a drain voltage of the P-channel field effect transistor A differential amplifier that detects a potential difference between the source voltage monitored by the source voltage detector and a source obtained from the source voltage detector when the voltage obtained from the differential amplifier exceeds a predetermined voltage Voltage and gate-source voltage and drain-source of the P-channel field effect transistor Adjusting said drain gate voltage of the P-channel field effect transistor based on the characteristic of the resistance - and a gate voltage adjustment circuit to prevent certain level of current flows through the by varying the source resistance power amplifier.

請求項５に記載の本発明は、請求項１〜４いずれか１項に記載の電源制御回路を有する。 The present invention according to claim 5 has the power supply control circuit according to any one of claims 1 to 4.

請求項６に記載の本発明は、移動通信機器における電源制御方法であって、高周波信号を増幅する電力増幅器への電圧供給をスイッチングするＰチャネル電界効果トランジスタのドレイン電圧とソース電圧との電位差を検出し、この電位差が予め決められた電圧を超えた場合、前記Ｐチャネル電界効果トランジスタのソース電圧と前記Ｐチャネル電界効果トランジスタのゲート−ソース電圧およびドレイン−ソース間抵抗の特性に基づき前記Ｐチャネル電界効果トランジスタのゲート電圧を調整し、前記Ｐチャネル電界効果トランジスタのドレイン−ソース間抵抗を可変し、前記電力増幅器に一定以上の電流が流れないように制限する。 The present invention according to claim 6 is a power supply control method in a mobile communication device, wherein a potential difference between a drain voltage and a source voltage of a P-channel field effect transistor that switches voltage supply to a power amplifier that amplifies a high-frequency signal is calculated. If this potential difference exceeds a predetermined voltage, the P channel is determined based on the characteristics of the source voltage of the P channel field effect transistor and the gate-source voltage and drain-source resistance of the P channel field effect transistor. The gate voltage of the field effect transistor is adjusted, the resistance between the drain and the source of the P-channel field effect transistor is varied, and the current amplifier is limited so that a current exceeding a certain level does not flow.

請求項７に記載の本発明は、請求項６において、前記Ｐチャネル電界効果トランジスタのソース電圧とドレイン電圧との電位差を検出し、前記電力増幅器に流れる電流値のモニターを繰り返し行う。 According to a seventh aspect of the present invention, in the sixth aspect, the potential difference between the source voltage and the drain voltage of the P-channel field effect transistor is detected, and the current value flowing through the power amplifier is repeatedly monitored.

本発明によれば、高周波信号を増幅する電力増幅器における消費電流の検出を行うゲート電圧調整回路を設け、異常な消費電流を検出した場合には、電圧供給をスイッチングするＰｃｈＦＥＴのゲート電圧を調整し、このＰｃｈＦＥＴのソース−ドレイン間の抵抗を可変することによって電力増幅器に対し一定以上の電流制限を行っているため、異常時でも消費電流が最小限に抑えることができる。 According to the present invention, a gate voltage adjustment circuit that detects current consumption in a power amplifier that amplifies a high-frequency signal is provided, and when abnormal current consumption is detected, the gate voltage of the PchFET that switches voltage supply is adjusted. Since the power amplifier limits the current more than a certain level by changing the resistance between the source and the drain of the PchFET, the current consumption can be minimized even in an abnormal state.

また、常時電圧供給をスイッチングするＰｃｈＦＥＴのソース電圧とドレイン電圧の電位差をモニターし、この電力増幅器に流れる電流値をモニターしているため、異常電流が流れた場合でも後に正常電流に復帰した場合には、正常動作に自動的に復旧できる。 In addition, since the potential difference between the source voltage and drain voltage of the PchFET that constantly switches the voltage supply is monitored and the current value flowing through this power amplifier is monitored, even if an abnormal current flows, it returns to normal current later. Can automatically recover to normal operation.

次に、本発明の実施の形態について図面を参照して説明する。図１を参照すると、移動通信機器などに用いられる電源制御回路が示され、電力増幅器１と、電池２と、ＰｃｈＦＥＴ３と、ソース電圧検出部４と、差動増幅器５と、ゲート電圧調整回路６とを備える。電力増幅器１は高周波信号を増幅する。ＰｃｈＦＥＴ３は、電力増幅器１の電源端子にドレイン端子が接続され、移動通信機器の送信時のみ電力増幅器１へ電圧を供給するようスイッチングを行う。電池２は、ＰｃｈＦＥＴ３のソース端子が接続され、電力増幅器１へ電圧を供給する。ソース電圧検出部４はＰｃｈＦＥＴ３のソース電圧をモニターする。差動増幅器５は、ＰｃｈＦＥＴ３のドレイン端子とソース電圧検出部４に接続され、ドレイン−ソースの電位差を出力する。ゲート電圧調整回路６は、差動増幅器５の出力端子が接続され、電力増幅器１に流れている電流の正常／異常を検出し、異常時にはＰｃｈＦＥＴ３のゲート電圧を調整する機能を有する。ゲート電圧調整回路６の出力はＰｃｈＦＥＴ３のゲート端子に接続される。またＰｃｈＦＥＴ３のソース電圧はソース電圧検出部４を介しゲート電圧調整回路６にも入力される。 Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1, a power supply control circuit used for a mobile communication device or the like is shown. A power amplifier 1, a battery 2, a PchFET 3, a source voltage detection unit 4, a differential amplifier 5, and a gate voltage adjustment circuit 6 are shown. With. The power amplifier 1 amplifies the high frequency signal. The PchFET 3 has a drain terminal connected to the power supply terminal of the power amplifier 1 and performs switching so as to supply a voltage to the power amplifier 1 only during transmission of the mobile communication device. The battery 2 is connected to the source terminal of the PchFET 3 and supplies a voltage to the power amplifier 1. The source voltage detector 4 monitors the source voltage of the PchFET 3. The differential amplifier 5 is connected to the drain terminal of the PchFET 3 and the source voltage detection unit 4 and outputs a drain-source potential difference. The gate voltage adjusting circuit 6 is connected to the output terminal of the differential amplifier 5 and has a function of detecting normality / abnormality of the current flowing through the power amplifier 1 and adjusting the gate voltage of the PchFET 3 when abnormal. The output of the gate voltage adjustment circuit 6 is connected to the gate terminal of the PchFET 3. The source voltage of the PchFET 3 is also input to the gate voltage adjustment circuit 6 through the source voltage detection unit 4.

ゲート電圧調整回路６は、比較器６１と、電圧発生器６２と、切替部６３とを備える。比較器６１は、差動増幅器５の出力と予め設定された閾値とを比較し正常／異常を判断し異常時にはＰｃｈＦＥＴ３のゲート端子にドレイン−ソース間抵抗が大きくなるような電圧を出力する。電圧発生器６２は、ソース電圧を入力すると共に差動増幅器５から出力されるドレイン電圧とソース電圧との電位差により決められた電圧を出力する。切替部６３は、差動増幅器５の出力電圧が閾値より大きくなればこの差動増幅器５の出力に応じた電圧を電圧発生器６２から出力させるために切り替える。 The gate voltage adjustment circuit 6 includes a comparator 61, a voltage generator 62, and a switching unit 63. The comparator 61 compares the output of the differential amplifier 5 with a preset threshold value to determine normality / abnormality, and outputs a voltage that increases the drain-source resistance to the gate terminal of the PchFET 3 when abnormal. The voltage generator 62 inputs the source voltage and outputs a voltage determined by the potential difference between the drain voltage and the source voltage output from the differential amplifier 5. When the output voltage of the differential amplifier 5 becomes larger than the threshold value, the switching unit 63 switches the voltage generator 62 to output a voltage corresponding to the output of the differential amplifier 5.

以下に、図１および図２を参照して動作を説明する。送信開始時はＰｃｈＦＥＴ３のソース−ドレイン間の送信時の抵抗値は最小となるようゲート電圧調整回路６の出力電圧はＬレベル電圧（＝０Ｖ）に設定される。電力増幅器１に異常に大きい電流が流れていない場合は、（以下正常な場合）ＰｃｈＦＥＴ３のソース−ドレイン間の抵抗値は十分に低いため、ＰｃｈＦＥＴ３のソース−ドレイン間の電位差は小さくなる。よって差動増幅器５より出力される電圧も小さい電圧となり、ゲート電圧調整回路６に入力される。ゲート電圧調整回路６の内部には、予め電力増幅器１が異常となった場合のＰｃｈＦＥＴ３のソース−ドレイン間の電位差から決められた閾値電圧が入力されている。ゲート電圧調整回路６の入力端子に入力される電圧が閾値電圧より低いため、ゲート電圧調整回路６の内部では正常動作と判断される。正常時は、ゲート電圧調整回路６の出力は、送信時Ｌレベル電圧（＝０Ｖ＝ソース−ゲート間電圧大）となり、ＰｃｈＦＥＴ３のソース−ドレイン間の抵抗値は最小となる。 The operation will be described below with reference to FIGS. At the start of transmission, the output voltage of the gate voltage adjusting circuit 6 is set to the L level voltage (= 0 V) so that the resistance value during transmission between the source and drain of the PchFET 3 is minimized. When an abnormally large current does not flow through the power amplifier 1, the resistance value between the source and drain of the PchFET 3 is sufficiently low (hereinafter normal), and the potential difference between the source and drain of the PchFET 3 becomes small. Therefore, the voltage output from the differential amplifier 5 is also a small voltage and is input to the gate voltage adjustment circuit 6. A threshold voltage determined in advance from the potential difference between the source and drain of the PchFET 3 when the power amplifier 1 becomes abnormal is inputted into the gate voltage adjustment circuit 6. Since the voltage input to the input terminal of the gate voltage adjusting circuit 6 is lower than the threshold voltage, it is determined that the gate voltage adjusting circuit 6 is operating normally. Under normal conditions, the output of the gate voltage adjustment circuit 6 is an L level voltage (= 0 V = source-gate voltage is large) during transmission, and the resistance value between the source and drain of the PchFET 3 is minimum.

電力増幅器１に異常に大きい電流が流れている場合は、（以下異常な場合）ＰｃｈＦＥＴ３のソース−ドレイン間の電位差は大きくなる。差動増幅器５の出力電圧は大きくなり、ゲート電圧調整回路６の入力端子に入力される電圧が閾値電圧より高いため、ゲート電圧調整回路６の内部では異常動作と判断される。異常動作と判断された場合、ＰｃｈＦＥＴ３のソース電圧よりある一定電圧降下した電圧をゲート電圧調整回路６より出力し、ＰｃｈＦＥＴ３のゲート端子へ印加する。この一定電圧は、図２に示すＰｃｈＦＥＴ３のＶｇｓ（ソース−ゲート間電圧）−Ｒｄｓ（ソース−ドレイン間抵抗）特性から決められる。例えば、１Ａを異常時最大電流値と設定している場合には、ＰｃｈＦＥＴ３のソース電圧が３Ｖの時Ｒｄｓは３オームとすれば良い。よって、図２よりＶｇｓを１Ｖとすれば良く、ゲート電圧を２ＶにすればＲｄｓは３オームとなる。このようにゲート電圧調整回路６から２Ｖを出力すれば異常時電流１Ａをキープすることができる。 When an abnormally large current flows through the power amplifier 1, the potential difference between the source and the drain of the PchFET 3 becomes large (hereinafter, when abnormal). Since the output voltage of the differential amplifier 5 increases and the voltage input to the input terminal of the gate voltage adjustment circuit 6 is higher than the threshold voltage, it is determined that the gate voltage adjustment circuit 6 is operating abnormally. If it is determined that the operation is abnormal, a voltage that is a certain voltage drop from the source voltage of the PchFET 3 is output from the gate voltage adjustment circuit 6 and applied to the gate terminal of the PchFET 3. This constant voltage is determined from the Vgs (source-gate voltage) -Rds (source-drain resistance) characteristic of the PchFET 3 shown in FIG. For example, when 1 A is set as the maximum current value at the time of abnormality, Rds may be 3 ohms when the source voltage of the PchFET 3 is 3V. Therefore, as shown in FIG. 2, Vgs may be 1V, and if the gate voltage is 2V, Rds is 3 ohms. Thus, if 2V is output from the gate voltage adjusting circuit 6, the abnormal current 1A can be kept.

また異常時より電流が正常時に戻った場合には、以下の動作となる。ＰｃｈＦＥＴ３のＲｄｓが３オームの時、１Ａの異常電流が０．５Ａの正常電流に戻ったとすると、１Ａの時のＰｃｈＦＥＴ３のソース−ドレイン間の電位差は３Ｖであるが、０．５Ａのときの電位差は、１．５Ｖとなる。このとき異常最大設定電流値が１Ａであるから、Ｒｄｓは１．５オームで良いため、ＰｃｈＦＥＴ３のゲート電圧は１．５Ｖを印加すれば良い。すると正常電流値０．５Ａであれば、ＰｃｈＦＥＴ３のソース−ドレイン間の電位差は０．７５Ｖとなる。この一連の動作を繰り返すことにより差動増幅器５から出力されるＰｃｈＦＥＴ３のソース−ドレイン間の電位差が、ゲート電圧調整回路６に入力されている閾値電圧を下回り、上述した正常動作へ戻ることができる。 When the current returns to normal from the time of abnormality, the following operation is performed. When the Rds of the PchFET 3 is 3 ohms, if the abnormal current of 1A returns to the normal current of 0.5A, the potential difference between the source and drain of the PchFET 3 at 1A is 3V, but the potential difference at 0.5A Becomes 1.5V. At this time, since the abnormal maximum set current value is 1 A, Rds may be 1.5 ohms, so that the gate voltage of PchFET 3 may be 1.5 V. Then, if the normal current value is 0.5 A, the potential difference between the source and the drain of the PchFET 3 is 0.75V. By repeating this series of operations, the potential difference between the source and the drain of the PchFET 3 output from the differential amplifier 5 is lower than the threshold voltage input to the gate voltage adjusting circuit 6, and the normal operation described above can be restored. .

本発明の実施の形態を示す移動通信機器における電源制御回路のブロック図である。1 is a block diagram of a power supply control circuit in a mobile communication device showing an embodiment of the present invention. 本発明の実施の形態の動作を説明するためＰｃｈＦＥＴにおけるＶｇｓｖｓＲｏｎ特性の一例を示す図である。It is a figure which shows an example of the Vgs vs. Ron characteristic in PchFET, in order to demonstrate operation | movement of embodiment of this invention. 従来の移動通信機器における電源制御回路の一例を示すブロック図である。It is a block diagram which shows an example of the power supply control circuit in the conventional mobile communication apparatus.

Explanation of symbols

１電力増幅器
２電池
３ＰｃｈＦＥＴ
４ソース電圧検出部
５差動増幅器
６ゲート電圧調整回路
６１比較器
６２電圧発生器
６３切替部
1 Power amplifier 2 Battery 3 PchFET
4 Source Voltage Detection Unit 5 Differential Amplifier 6 Gate Voltage Adjustment Circuit 61 Comparator 62 Voltage Generator 63 Switching Unit

Claims

A P-channel field effect transistor that performs switching so that a voltage is applied to the power amplifier only during transmission of a communication device having a power amplifier that amplifies a high-frequency signal, and a potential difference between the drain voltage and the source voltage of the P-channel field effect transistor A potential difference detecting means for detecting the source voltage of the P channel field effect transistor and a gate-source voltage of the P channel field effect transistor when a voltage obtained from the potential difference detecting means exceeds a predetermined voltage; By adjusting the gate voltage of the P-channel field effect transistor based on the characteristics of the drain-source resistance and varying the drain-source resistance, a current exceeding a certain level is prevented from flowing through a power amplifier that amplifies a high-frequency signal. And a gate voltage adjusting means. Source control circuit.

The gate voltage adjusting means compares the output of the potential difference detecting means with a preset threshold value to determine normality / abnormality, and when the abnormality occurs, the drain-source resistance increases at the gate terminal of the P-channel field effect transistor. A comparator that outputs such a voltage, a voltage generator that inputs the source voltage and outputs a voltage determined by a potential difference between a drain voltage and a source voltage output from the potential difference detecting means, and the potential difference detecting means The power supply control circuit according to claim 1, further comprising: a switching unit that switches to output a voltage corresponding to the output of the potential difference detection means from the voltage generator when the output voltage of the voltage difference exceeds a threshold value.

3. The power supply control circuit according to claim 1, wherein the potential difference detecting means is a differential amplifier.

A power amplifier that amplifies a high-frequency signal; a P-channel field effect transistor that performs switching so as to apply a voltage to the power amplifier only during transmission of a communication device having the power amplifier; and a source terminal of the P-channel field effect transistor A battery connected to supply voltage to the power amplifier, a source voltage detector for monitoring a source voltage of the P-channel field effect transistor, a drain voltage of the P-channel field effect transistor and a source monitored by the source voltage detector A differential amplifier for detecting a potential difference from the voltage; a source voltage obtained from the source voltage detector when a voltage obtained from the differential amplifier exceeds a predetermined voltage; and a gate of the P-channel field effect transistor -P based on the characteristics of the source voltage and the drain-source resistance. Yaneru adjust the drain gate voltage of the field effect transistor - the power control circuit, comprising a gate voltage adjustment circuit to vary the source resistance to prevent certain level of current flows to the power amplifier.

A mobile communication device comprising the power supply control circuit according to claim 1.

A power supply control method in a mobile communication device that detects a potential difference between a drain voltage and a source voltage of a P-channel field effect transistor that switches voltage supply to a power amplifier that amplifies a high-frequency signal, and the potential difference is predetermined. If the voltage exceeds, the gate voltage of the P-channel field effect transistor is adjusted based on the source voltage of the P-channel field effect transistor and the characteristics of the gate-source voltage and the drain-source resistance of the P-channel field effect transistor; A power supply control method in a mobile communication device, wherein a resistance between a drain and a source of the P-channel field effect transistor is varied to restrict a current exceeding a certain value from flowing through the power amplifier.

The power control method for a mobile communication device according to claim 6, wherein a potential difference between a source voltage and a drain voltage of the P-channel field effect transistor is detected, and a current value flowing through the power amplifier is repeatedly monitored.