JP2005039260A - Stress relaxation structure and formation method therefor, stress relaxation sheet and manufacturing method therefor, and semiconductor device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stress relaxation structure and its formation method that is superior in stress relaxation effects upon thermal stress and improves the reliability of a semiconductor device, and to provide a stress relaxation sheet and its manufacturing method, and a semiconductor device, having the stress relaxation sheet and electronic equipment having the semiconductor device. <P>SOLUTION: The stress relaxation structure, which has a wave-shaped insulating layer 4 that exists between a chip 5, on which a semiconductor device 6 is formed and a mounting substrate 7, has the above problem resolved by making the wiring 3 wave-shaped. In addition, the stress relaxed structure is formed, by forming an insulating layer 4 having a wavy shape that displaces in the thickness direction on a process substrate or a wafer, having a semiconductor element and forming wiring 3 having a wavy shape on the insulating layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a stress relaxation structure and a method for forming the same, a stress relaxation sheet and a method for manufacturing the same, a semiconductor device having the stress relaxation sheet, and an electronic device having the semiconductor device. The present invention relates to a technical field for improving the reliability of a device.

  Conventionally, a mounting substrate such as a semiconductor package has mainly used a ceramic material as an insulating material. However, in recent years, mounting substrates using an organic material as an insulating material have come to be used for reasons such as high-temperature processing not required, easy processing, light weight, and cost reduction. In the case of a board-type mounting board such as a mother board, an organic material is also used as an insulating material because of its large size.

  Semiconductor elements such as LSI and VLSI are formed on the surface of a chip or wafer such as silicon. However, the thermal expansion coefficient of silicon is as small as 4 ppm / ° C, whereas the linear expansion coefficient of organic materials is 10 ppm / ° C or more, usually several tens of ppm / ° C to 100 ppm / ° C or more. Considerably larger than. For this reason, when a silicon chip or wafer on which a semiconductor element is formed (including a chip after cutting) is connected to a mounting substrate mainly made of an organic material, it is caused by a difference in thermal expansion coefficient between different materials used. Stress, that is, thermal stress is generated.

  Examples of a thermal factor that generates such thermal stress include heating for soldering, heating by a thermal cycle test (TC), and heat generation from a semiconductor element. In addition, thermal stress may be generated depending on the use environment such as a semiconductor mounted on an automobile.

  The thermal factor generates thermal stress in a direction parallel to the chip surface. FIG. 10 is a schematic diagram for explaining the thermal stress generated between the semiconductor chip 101 and the mounting substrate 102. Here, a case where the semiconductor chip 101 is mounted on the mounting substrate 102 by flip chip connection is shown. The semiconductor chip 101 and the mounting substrate 102 are connected by solder balls 103 or the like while being heated to around 260 ° C. Since the thermal expansion coefficient of the mounting substrate 102 is considerably larger than the thermal expansion coefficient of the semiconductor chip 101 made of silicon or the like, when the semiconductor chip 101 is cooled to room temperature, a compressive stress P1 from the chip end toward the chip center is applied to the semiconductor chip 101 side. As a result, an outward tensile stress P2 is generated on the mounting substrate 102 side. Under restraint conditions, vertical stress is also generated in order to release this in-plane compressive / tensile stress.

  This thermal stress is concentrated on the connection portion between the semiconductor chip and the mounting substrate. Therefore, there is a risk of destruction of the land for flip chip (FC) or ball grid array (BGA), destruction of solder balls, cutting of metal wiring inside the substrate, etc. There is a risk that it will not function properly. In addition, there is a possibility that warpage occurs in the semiconductor chip or the like due to vertical stress generated under restraint conditions. In particular, in recent years, with the increase in the number of signal lines accompanying the increase in the density of semiconductors, there has been a trend in which connections between semiconductor elements and mounting boards have shifted from wire bonding connections to flip chip connections, and problems due to thermal stress have become prominent. ing.

  As a method for relieving such thermal stress, it is effective to provide a semiconductor device with a structure for relieving thermal stress. As a method for this, it has been conventionally considered that an insulating layer has a stress relaxation function.

  FIG. 11 is a cross-sectional view showing an example of a conventional semiconductor device having a stress relaxation function (see, for example, Patent Document 1). In this semiconductor device 111, the stress relaxation resin layer 113 having a predetermined elastic modulus and thickness is provided on the semiconductor element 112 without providing the package electrode 116 immediately above the semiconductor element electrode portion 114, and the stress relaxation resin layer. The thermal stress is alleviated by extending the wiring 115 from the semiconductor element electrode portion 114 onto the 113 and connecting the wiring 115 to the package electrode 116. Further, as the resin forming the stress relaxation resin layer 113, a resin having a normal elastic modulus (about 2.8 GPa) is used.

Further, in Patent Document 2 below, by providing a groove in a copper pattern provided between an insulating substrate and a semiconductor chip, stress concentration generated at the bonding interface between the copper pattern and the insulating substrate is alleviated. The occurrence of peeling is prevented.
JP 2000-323628 A (FIG. 1, paragraph numbers 0041 to 00 43) JP 2002-299495 A (paragraph numbers 0009, 0010, FIG. 1)

  However, the thermal stress generated in the direction parallel to the chip surface increases in proportion to the distance from the center of the chip. Therefore, when the chip becomes large, the calculation at the end of the chip is about several tens to hundreds of μm. May cause large displacement. However, as described in Patent Document 1 described above, a large displacement cannot be absorbed only by providing the insulating layer with a stress relaxation function. In particular, in recent years, this problem has become prominent because semiconductor chips and semiconductor packages on which the semiconductor chips are mounted tend to increase in size as the performance of semiconductors and the number of pins increase.

  Further, in a general semiconductor device, the elastic modulus of a metal such as copper forming a wiring is usually around 100 GPa, which is nearly two orders of magnitude larger than the resin forming the stress relaxation resin layer. For this reason, in the structure of the prior art in which a metal wiring made of a high elastic modulus material is provided on the stress relaxation resin layer, even if a groove is formed in the copper pattern as described in Patent Document 2, it is parallel to the chip surface. The thermal stress generated in the direction is transmitted to the semiconductor element and the solder connection portion through the wiring. Therefore, even with such a structure, problems due to thermal stress, such as destruction of land portions for FC or BGA, destruction of solder balls, cutting of metal wiring inside the substrate, etc. cannot be solved, and a reliable semiconductor device is obtained. I couldn't.

  Furthermore, a low-K material having a low dielectric constant tends to be used for an insulating layer inside a semiconductor element in order to improve the performance of the semiconductor. However, since the mechanical strength of the low-K material is lower than that of conventionally used organic materials, in the semiconductor device having the structure of the prior art, the stress transmitted through the wiring is directly applied to the low-K material of the semiconductor element. There is a risk of problems such as destruction of the semiconductor element.

  The present invention has been made to solve the above-described problems, and its object is to provide a stress relaxation structure that is excellent in stress relaxation effect against thermal stress and improves the reliability of a semiconductor device, a method for forming the stress relaxation structure, and stress relaxation. An object of the present invention is to provide a sheet, a manufacturing method thereof, a semiconductor device having a stress relaxation sheet, and an electronic apparatus having the semiconductor device.

  In order to solve the above problems, the stress relaxation structure of the present invention includes an insulating layer having a corrugated shape existing between a chip on which a semiconductor element is formed and a mounting substrate, and a wiring formed on the insulating layer. A stress relaxation structure including: wherein the wiring has a waveform shape.

  According to the present invention, since the corrugated wiring has an effect as a spring structure, the generated thermal stress is efficiently absorbed by the stress relaxation structure having the wiring. As a result, when the stress relaxation structure of the present invention is applied to a semiconductor device, the stress at the connection portion between the semiconductor element and the mounting substrate can be relaxed. For example, the land portion for FC or BGA A semiconductor device with high reliability against thermal stress can be realized without causing destruction, destruction of solder balls, destruction of Low-K material, cutting of metal wiring inside the substrate, and the like.

  In the stress relaxation structure of the present invention, (A) the waveform shape of the wiring is displaced in the thickness direction, (B) the waveform shape of the wiring is displaced in the in-plane direction, (C) The wiring waveform has a spiral shape formed by superposing a sine wave shape or a substantially sine wave shape displaced in the thickness direction and a sine wave shape or a substantially sine wave shape displaced in the in-plane direction. (D) The width of the wiring is different between the upper part and the lower part in the thickness direction, or (E) the wiring is a metal wiring, and the metal wiring is configured on the chip side surface of the metal wiring. It is preferable that a thin layer made of a metal different from the main metal component is provided.

  According to these inventions, since the wiring has the corrugated shape or the like, the generated thermal stress can be absorbed more efficiently.

  In the stress relaxation structure of the present invention, (F) the extension direction of the wiring is parallel or substantially parallel to a virtual line extending radially from the center of the chip, or (G) the extension of the wiring. The diagonal direction is constant in each quadrant arranged four times symmetrically with the center of the chip as a symmetric point, and the extension direction is a diagonal axis passing through the symmetric point among the diagonal axes in each quadrant Is preferably parallel or substantially parallel to.

  According to these inventions, the stress relaxation structure can absorb the generated thermal stress more efficiently because the extension direction of the wiring is substantially the same as the direction of the generated thermal stress.

  In the stress relaxation structure of the present invention, (H) the tensile elastic modulus of the insulating layer is 1 GPa or less, (I) the tensile breaking elongation of the insulating layer is 10% or more, and (J) the insulation. The layer comprises two or more insulating layers, (K) the corrugated shape of the insulating layer includes one or more indentations, or (L) the insulating layer is formed adjacent to the chip. It is preferable.

  According to these inventions, it is possible to ensure the stress relaxation function of the wiring having the waveform shape formed on the insulating layer.

  The stress relaxation sheet of the present invention for solving the above-described problem is a stress relaxation sheet used for relaxing stress between a chip on which a semiconductor element is formed and a mounting substrate, and has the above-described stress relaxation structure. It is characterized by having.

  According to this invention, since the stress relaxation sheet has the above-described stress relaxation structure, the problem due to the thermal stress of the semiconductor device using the stress relaxation sheet can be solved.

  A semiconductor device of the present invention for solving the above-described problems has the above-described stress relaxation structure or stress relaxation sheet.

  According to the present invention, since the semiconductor device has the stress relaxation structure or the stress relaxation sheet having the stress relaxation structure described above, it is possible to obtain a highly reliable semiconductor device in which problems due to thermal stress hardly occur.

  In order to solve the above-described problems, an electronic device according to the present invention includes the above-described semiconductor device.

  In order to solve the above problems, a stress relaxation structure forming method of the present invention includes an insulating layer having a corrugated shape existing between a chip on which a semiconductor element is formed and a mounting substrate, and an insulating layer formed on the insulating layer. A method of forming a stress relaxation structure including a wiring, comprising: forming an insulating layer having a waveform shape displaced in a thickness direction on a process substrate or a wafer having a semiconductor element; and forming the waveform shape on the insulating layer A wiring having the following is formed.

  According to the present invention, since the wiring is formed on the insulating layer having the corrugated shape, the corrugated wiring capable of efficiently absorbing the stress can be formed by a simple method.

  In the method for forming a stress relaxation structure of the present invention, (a) the insulating layer having the corrugated shape forms an insulating layer on a process substrate or a wafer having a semiconductor element, and the rectangular depression is formed in the insulating layer. (B) the insulating layer having the corrugated shape is formed on the process substrate or on the wafer having the semiconductor element. An insulating layer made of a negative photosensitive resin is formed, and the insulating layer is exposed and developed in a state where a mask on which a rectangular pattern is formed is floated, and (c) has the corrugated shape. The insulating layer is formed by forming an insulating layer made of a positive photosensitive resin with low transmittance on a process substrate or a wafer having a semiconductor element, and exposing and developing the insulating layer. (D) The insulating layer having the corrugated shape includes two or more depressions, and the insulating layer is an insulating layer made of a positive photosensitive resin on a process substrate or a wafer having a semiconductor element. It is preferable that the insulating layer is formed after the film is formed and irradiated with a different amount of light at each location.

  According to these inventions, since the corrugated shape of the insulating layer is formed by heat treatment or the like, the corrugated insulating layer can be formed by a simple method.

  In the method of forming the stress relaxation structure of (a), the material of the insulating layer is a photosensitive resin, and the rectangular recess of the insulating layer is formed by exposing and developing the insulating layer. Is preferred. At this time, it is preferable that the insulating layer is composed of two or more layers, and two or more types of depressions are formed in the insulating layer by one exposure. Also, in the method of forming the stress relaxation structure of (b) or (c), the insulating layer is composed of two or more insulating layers, and two or more types of indentations including openings are formed by one exposure. It is preferable to form.

  In the present application, the “dent” means a portion lowered from the surface of the insulating layer, and is formed in a concave shape without penetrating the insulating layer, and a through-hole structure such as a via penetrating the insulating layer. It is used in the meaning including the structure. In the present application, the term “opening” is used to indicate a through-hole structure such as a via penetrating the insulating layer in the “indent”.

  Moreover, in the formation method of the stress relaxation structure of this invention, it is preferable that the insulating layer which has the said waveform shape is formed by processing nonphotosensitive resin. At this time, (i) the insulating layer having the corrugated shape includes two or more depressions, and the insulating layer is an insulating layer made of a non-photosensitive resin on a process substrate or a wafer having a semiconductor element. After forming a layer and forming two or more mask layers on the insulating layer, the insulating layer is preferably formed by etching. Further, (ii) the insulating layer having the corrugated shape is formed by applying a non-photosensitive resin after forming a plating pattern on a process substrate or a wafer having a semiconductor element, and then etching and removing the plating pattern. It is preferable to be formed.

  According to these inventions, since the insulating layer is formed of a non-photosensitive resin, a low-elasticity resin and a high tensile elongation at break desired for the insulating layer can be selected from a wide range.

  In order to solve the above problems, a stress relaxation structure forming method of the present invention includes an insulating layer having a corrugated shape existing between a chip on which a semiconductor element is formed and a mounting substrate, and an insulating layer formed on the insulating layer. And a spiral shape formed by superimposing a sine wave shape or a substantially sine wave shape displaced in the thickness direction and a sine wave shape or a substantially sine wave shape displaced in the in-plane direction. A method of forming a stress relaxation structure, comprising: forming an insulating layer having a sine wave shape or a substantially sine wave shape waveform displaced in a thickness direction on a process substrate or a wafer having a semiconductor element; A wiring having a sinusoidal or substantially sinusoidal waveform that is displaced in an in-plane direction in a plan view and having inflection points alternately at the waveform top and waveform bottom in the thickness direction of the insulating layer. As a result, a spiral wiring is formed. It is characterized in.

  The manufacturing method of the stress relaxation sheet of this invention for solving the said subject forms a stress relaxation structure by the above-mentioned method on the said process board | substrate, Then, the said process board | substrate is peeled or removed, It is characterized by the above-mentioned.

  As described above, according to the stress relaxation structure and the stress relaxation sheet of the present invention, the corrugated wiring has an effect as a spring structure and can efficiently absorb the thermal stress generated in the semiconductor device. Further, according to the semiconductor device of the present invention, stress at the connection portion between the semiconductor element and the mounting substrate is relieved, for example, destruction of a land portion for flip chip connection, solder balls for connecting the semiconductor element and the mounting substrate In addition, a highly reliable semiconductor device can be obtained without causing destruction of wiring, Low-K material, wiring inside the mounting substrate, and the like.

  In addition, the stress relaxation structure of the present invention can be applied to a large semiconductor device having a large thermal stress, a semiconductor device using a material having a low mechanical strength such as a Low-K material, or a flip chip ball grip array (FCBGA) having a large number of pins. This is effective when applied to packages such as The stress relaxation structure of the present invention is effective not only for thermal stress but also for stress other than thermal stress, such as drop impact.

  Moreover, according to the method for forming a stress relaxation structure of the present invention, the stress relaxation structure can be easily produced. Further, by forming the insulating layer from a non-photosensitive resin, a low-elasticity resin desired for the insulating layer and a resin having a high tensile elongation at break can be selected from a wide range.

  Hereinafter, the stress relaxation structure of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing an example of a semiconductor device having a stress relaxation structure of the present invention. As shown in FIGS. 1A and 1B, the stress relaxation structure 2 of the present invention includes an insulating layer 4 having a corrugated shape that exists between a chip 5 on which a semiconductor element 6 is formed and a mounting substrate 7. The wiring 3 formed on the insulating layer is characterized in that the wiring 3 has a corrugated shape. In addition, the wiring 3 in FIG. 1 shows the aspect which the waveform shape displaces to thickness direction, and the code | symbol 2 shows a stress relaxation structure or a stress relaxation sheet.

  FIG. 1A shows a mode in which a stress relaxation sheet having a stress relaxation structure in a part thereof is provided between a chip and a mounting substrate. The chip 5 and the mounting substrate 7 are solder balls 8 / stress relaxation. They are connected via wiring 3 / solder balls 8 in the sheet. FIG. 1B shows a mode in which the stress relaxation structure is formed on a chip 5 or a wafer having a semiconductor element. The chip 5 and the mounting substrate 7 are included in the stress relaxation structure formed on the chip 5. The wiring 3 and the solder ball 8 are connected to each other. In general, the solder ball on the chip 5 side is larger than the solder ball on the mounting substrate 7 side. In the present invention, the solder ball on the chip 5 side may have a larger diameter than the solder ball on the mounting substrate 7 side, or may have the same diameter as the solder ball on the mounting substrate 7 side.

  1A and 1B, an insulating layer 4 having a corrugated shape is formed on the chip side of the wiring, and another insulating layer 9 is formed on the mounting substrate side of the wiring. However, the insulating layer 9 is not necessarily provided. Reference numeral 22 denotes a smooth depression that forms the corrugated shape of the insulating layer 4, and reference numeral 23 denotes a chip-side wiring connection portion for connecting to the semiconductor element 6 on the chip directly or via the solder ball 8. Reference numeral 24 denotes a mounting board side pad for connection to wiring on the mounting board.

(Stress relaxation structure and stress relaxation sheet)
First, the stress relaxation structure of the present invention will be described in detail.

  As shown in FIG. 1, the stress relaxation structure of the present invention includes an insulating layer 4 having a corrugated shape existing between a chip 5 on which a semiconductor element 6 is formed and a mounting substrate 7, and on the insulating layer 4. This structure includes the formed wiring 3.

  Since the corrugated wiring has an effect as a spring structure, it efficiently absorbs the generated stress. Therefore, in the semiconductor device having the stress relaxation structure of the present invention, the stress applied to the connection portion between the chip on which the semiconductor element is formed and the mounting substrate can be suppressed. Therefore, the semiconductor device having this structure does not cause destruction of the land for FC or BGA, destruction of the solder ball, cutting of the metal wiring inside the substrate, etc., even if thermal stress due to heat during soldering occurs. Since the function of the semiconductor element is not hindered, the reliability is high.

  The waveform shape of the wiring 3 includes a waveform shape that is displaced in a direction perpendicular to the chip surface (ie, the thickness direction) and a waveform shape that is displaced in a direction horizontal (ie, in-plane direction) to the chip surface. However, from the viewpoint of efficiently absorbing stress, a corrugated shape that is displaced in the thickness direction is preferable. Since such wiring is usually strip-shaped and wide, a corrugated wiring that is displaced in the in-plane direction has a large amount of distortion due to the bending of the wiring and is difficult to deform, but a waveform that is displaced in the thickness direction. Since the shape of the wiring is easy to deform, higher stress relaxation effect can be obtained.

  FIG. 2 is a plan view showing an example of a semiconductor device having a stress relaxation structure including a corrugated wiring that is displaced in the thickness direction. The waveform shape displaced in the thickness direction of the wiring 21 is formed along the smooth recess 22 of the insulating layer, that is, along the waveform shape displaced in the thickness direction of the insulation layer. In FIG. 2, reference numeral 22 denotes a smooth recess that forms the corrugated shape of the insulating layer, reference numeral 23 denotes a chip-side wiring connection portion, and reference numeral 24 denotes a mounting board-side pad.

  The waveform shape of the wiring is desirably a smooth shape, and particularly desirably a smooth shape having a sine wave shape or a substantially sine wave shape. The wiring having such a shape can uniformly disperse the generated stress and efficiently absorb it, and can prevent breakage of the wiring due to excessive stress generated at a specific portion of the wiring.

  The wiring is formed by being provided on a corrugated insulating layer. For example, when the insulating layer has a waveform shape that is displaced in the thickness direction, the wiring also has the same waveform shape as that shape.

  The waveform shape of the wiring is preferably a spiral shape. The spiral shape is formed by superimposing a sine wave shape or a substantially sine wave shape displaced in the thickness direction and a sine wave or a substantially sine wave shape displaced in the in-plane direction.

  FIG. 3 is a plan view illustrating an example of a semiconductor device having a stress relaxation structure including a spiral wiring. The spiral shape of the wiring 31 is formed by overlapping a corrugated wiring shape that is displaced in the thickness direction of the insulating layer (formed on the recess 22) and a corrugated wiring shape that is displaced in the in-plane direction. ing. In FIG. 3, (A) is an aspect in which the spiral is formed in 1.5 periods, and (B) is an aspect in which the spiral is formed in 2.5 periods. The spiral wiring has a longer wiring length than the corrugated wiring, and can absorb the generated stress more efficiently. Further, as will be described with reference to FIG. 6 and the like, when the stress relaxation structure in the chip is a four-fold symmetrical structure, a slight deviation occurs between the stress generation direction and the stress absorption direction of the wiring. If a spiral wiring is formed, there is a merit that the stress accompanying this slight deviation can be efficiently absorbed. Furthermore, an inductance-like electrical function can be added to the wiring by appropriately controlling the number of spirals and the size of the spiral.

  The number of wiring waves is preferably 1 or more and 20 or less, preferably between 2 and 5 or less, between the chip-side wiring connection portion 23 that is the wiring connection portion (23, 24) and the mounting substrate side pad 24. More preferably it is formed. The number of waves in the wiring is preferably larger from the viewpoint of stress relaxation. However, when the number of waves is larger than the above range, the interval between the wirings is narrowed and the formation becomes difficult. In addition, the wave height of the corrugated shape that is displaced in the thickness direction is preferably high from the viewpoint of stress relaxation, and ranges from the range that uses all the thickness of the insulating layer to the range that uses about half the thickness. The height is desirable, and the specific height is desirably 10 to 100 μm.

  FIG. 4 shows a plan view (A) showing an example of a mode in which a spiral wiring is provided on an insulating layer, and a C-C ′ sectional view (B) thereof. In FIG. 4A, the H region represents a sine wave-shaped or substantially sine wave-shaped peak portion displaced in the thickness direction, and the L region represents a valley portion. The spiral shape of the wiring 42 is a sine wave shape in which the inflection point D of the wiring 42 having a sine wave shape or a substantially sine wave shape that is displaced in the in-plane direction in a plan view of FIG. This is realized when the substantially sinusoidal insulating layer 41 is formed so as to alternately correspond to the waveform top 43 and the waveform bottom 44.

  FIG. 5 is a schematic diagram illustrating an example of an aspect in which the width of a wiring exhibiting a waveform shape differs in each part. For example, as shown in FIG. 5, when the width W1 of the wiring 51 far from the chip 53 is larger than the width W2 of the wiring 51 nearer to the chip 53, the chip 53 is easily stressed. There is an advantage that the possibility of breakage of the wiring 51 at a distant upper portion is reduced. On the other hand, when the width W1 of the wiring 51 far from the chip 53 is smaller than the width W2 of the wiring 51 nearer to the chip 53, the advantage that the transmission of the generated thermal stress through the wiring can be suppressed. There is.

  The wiring is usually formed of a metal having good conductivity such as copper. It is preferable that a thin layer made of a metal different from the main metal component constituting the wiring is provided between the wiring and the insulating layer on the chip or wafer side. This thin layer improves the adhesion between the wiring and the insulating layer, and further improves the reliability of the semiconductor device having the stress relaxation structure. The preferred thickness of the thin layer is 0.01-1 μm.

  As a material for forming the insulating layer 4, a conventional insulating layer material (for example, a tensile elastic modulus of about 2 to 3 GPa and tensile rupture can be used as long as it is an insulating layer on which a waveform having a waveform of the present invention is formed. An insulating material having an elongation of less than 10% can be used, but an insulating material having a low elastic modulus is more preferably used. As the low elastic modulus insulating material, for example, an insulating material having an insulating layer having a tensile elastic modulus of 1 GPa or less is preferably used. Such an insulating material varies depending on the waveform forming method described later. For example, a photosensitive elastomer, a photosensitive silicone (Toray Dow M150-P: a tensile elastic modulus is about 0.16 GPa, and a tensile elongation at break is about 0.16 GPa. A material having a low tensile elastic modulus such as about 20%) and a high tensile elongation at break is preferably used. When the insulating layer is formed of a material having a low elastic modulus, adjacent wirings can be efficiently deformed against stress. In addition, although there is no restriction | limiting in particular about the minimum of a tensile elasticity modulus, Usually, it is 10 MPa. Further, as the material for forming the insulating layer, an insulating material in which the tensile breaking elongation of the insulating layer is 10% or more can be preferably used. Examples of such a material include photosensitive elastomers and photosensitive silicones (Toray Dow M150-P), although they vary depending on the corrugated forming method. When the insulating layer is formed of a material having a high tensile elongation at break, the insulating layer is not broken even if the wiring is greatly deformed. The upper limit of the tensile elongation at break is not particularly limited but is usually 500%. The tensile elastic modulus and tensile elongation at break described above are calculated from data measured based on the JPCA standard built-up wiring board JPCA-BU01.

  In the present invention, it is more preferable that the material for forming the insulating layer has desirable characteristics of both tensile modulus and tensile elongation at break. Moreover, it is preferable that the insulating layer 9 provided on the chip side of the wiring shown in FIG.

  The thickness of the insulating layer is preferably about 20 μm to 100 μm thick, rather than about a few μm thin. The insulating layer having a thickness in this range can increase the wave height of the waveform shape displaced in the thickness direction, and as a result, the displacement of the waveform shape of the wiring can be increased.

  The insulating layer may be a single layer or two or more layers, but from the viewpoint of stress relaxation, it is preferable that the insulating layers are two or more layers and each layer is formed of different insulating materials. For example, an insulating layer having a low elastic modulus can be formed in a layer close to the chip or wafer, and the stress applied to the semiconductor element on the chip or wafer can be reduced as much as possible. In addition, a high-strength, high-elastic insulating layer can be formed on a layer close to the chip or wafer to protect the semiconductor element on the chip or wafer from stress. In addition, by making any one of the insulating layers a high-strength insulating layer or a highly elastic insulating layer, the stress relaxation sheet is strengthened and becomes easy to handle.

  When each of the two or more insulating layers is formed of the same material, the total thickness of the insulating layers can be increased, and a corrugated shape is formed in one insulating layer, and the other insulating layers are formed as chips. Alternatively, a two-layer structure or a multi-layer structure used for controlling the distance between the wafer and the mounting substrate can be used.

  FIG. 6 is a cross-sectional view showing an example of the stress relaxation structure of the present invention including an insulating layer having a two-layer structure, and a cross-sectional view showing an example of the stress relaxation structure of the present invention having a corrugated shape having a plurality of peaks.

  In FIG. 6, the two-layer insulating layer 60 is directly formed on the chip 64 having the semiconductor element 68, the first insulating layer 61 is formed on the semiconductor element 68, and the second insulating layer 62 is formed thereon. Further, a corrugated wiring 63 is formed thereon. According to this aspect, since the first insulating layer 61 is provided, the corrugated wiring 63 is separated from the chip 64 having the semiconductor element 68. A solder ball 67 is placed on the pad of the wiring 63.

  6A shows an aspect in which the thickness of the wiring 65 in the portion connected to the chip 64 is thicker than the thickness of the wiring 63 in the other portion, and FIG. The thickness of the wiring 65 is the same as the thickness of the wiring 63 in other portions. When the insulating layer is composed of two or more insulating layers, as will be described later, when forming the corrugated shape in the insulating layer, it can be formed to a two-stage depth by one exposure, There is an advantage that the cost can be reduced.

  6C and 6D are examples of a stress relaxation structure having a corrugated shape having two apexes. In the present invention, as shown in FIG. 6C, a corrugated shape having two or more wave crests may be formed on the insulating layer 60 having a two-layer structure. Of course, FIG. As shown in FIG. 3, the insulating layer 60 in which the waveform shape having two or more wave crests is formed may be a single layer.

  Next, the extending direction of the corrugated wiring in the stress relaxation structure of the present invention will be described.

  The extending direction of the wiring having a waveform shape is preferably parallel or substantially parallel to a virtual line extending in the radial direction from the center of the chip. The amount of strain caused by the thermal stress generated between the chip and the mounting substrate is proportional to the distance from the center of the chip, and the direction of the stress is the radial direction from the center of the chip. Therefore, the generated stress can be absorbed more efficiently by matching the extension direction of the wiring in a direction parallel or substantially parallel to a virtual line extending in the radial direction from the center of the chip.

  The extension direction of the wiring 3 is constant in each quadrant arranged symmetrically four times with the center of the chip as a symmetry point, and the extension direction is the symmetry point of the diagonal axes in each quadrant. It may be parallel or substantially parallel to the diagonal axis passing through. FIG. 7 is a plan view illustrating an example of a semiconductor device in which the extending direction of the wiring having a waveform shape is the above-described direction. 7 is the same as that shown in FIG.

  It is most desirable from the viewpoint of stress relaxation that the extension direction of the wiring 21 is parallel or substantially parallel to a virtual line extending in the radial direction from the center of the chip 5, but changing the extension direction of the wiring for each pad 24 is a mask. Design and production become complicated. On the other hand, the wiring 21 of the embodiment shown in FIGS. 7A and 7B is easy to design because its extension direction is constant in each quadrant arranged symmetrically four times with the center of the chip as the symmetry point P. Among the diagonal axes in each quadrant, the stress relief effect is excellent because it is parallel or substantially parallel to the diagonal axis Q passing through the symmetry point P. Further, by making the extension direction of the wiring 21 parallel or substantially parallel to the diagonal axis Q of the chip 5, it is possible to secure the longest distance for the stress relaxation structure when the pads 24 are arranged in a lattice pattern. Can do. Note that extending in the radial direction means that the chip-side wiring connection portion 23 is close to the center (see FIG. 7A) and the mounting substrate-side pad 24 is close to the center (FIG. 7B). ))).

  Next, a method for forming a stress relaxation structure will be described.

  As shown in FIG. 1A, the stress relaxation structure is formed on a sheet 2 used to relieve stress between the chip 5 on which the semiconductor element 6 is formed and the mounting substrate 7, or FIG. As shown in B), it can be directly formed on a chip or wafer on which the semiconductor element 6 is formed.

  When forming a stress relaxation sheet having a stress relaxation structure, an insulating layer 4 having a corrugated shape is formed on a process substrate, and a wiring 3 having a corrugated shape or a spiral shape is formed along the shape of the insulating layer. Then, a method of peeling or removing the process substrate is applied. At this time, the insulating layer having a corrugated shape is formed by applying an insulating material on the substrate to form an insulating layer having a uniform thickness, and then performing a corrugated forming process on the insulating layer. .

  As the process substrate, a substrate that is appropriately adhered to the insulating material and that is suitable for removal by mechanical peeling or chemical etching can be preferably used. For example, a copper substrate suitable for chemical etching can be applied. When a copper substrate is used, it is desirable to form an etching barrier layer for the copper etchant before forming the wiring. The process substrate is a substrate used in the process, and is finally a substrate that is peeled or removed.

  As shown in FIG. 1B, when a stress relaxation structure is formed directly on a chip or wafer on which a semiconductor element is formed, the chip or wafer is not limited to a silicon chip or wafer but for other compound devices. A glass substrate or the like on which a chip or wafer or a semiconductor element can be formed can be used. Such a chip or wafer is particularly preferable as a substrate on which an insulating layer is formed because the surface thereof has molecular level flatness, a high elastic modulus, and a small thermal expansion coefficient.

  Next, a method for making the insulating layer corrugated will be described.

  Examples of the treatment for changing the shape of the insulating layer into a corrugated shape that is displaced in the thickness direction include heat treatment, optical treatment, surface treatment, treatment with a solvent, and the like. In these processes, the insulating layer formed on the process substrate or the chip or wafer forms a smooth recess 22 with a rounded edge as shown in FIG. 8, and as a result, the insulating layer 4 is corrugated. Is the method. As a material for forming the insulating layer 4, a material suitable for each treatment is selected.

  FIG. 9 shows an example of a step of forming a corrugated insulating layer on a wafer on which a semiconductor element is formed.

  In the case of forming a waveform shape by heat treatment, first, an insulating material is applied to a process substrate or a wafer having a semiconductor element (referred to as process substrate 92 or the like) to form a uniform insulating layer 91 (FIG. 9 ( See A)). Next, a part of the insulating layer 91 is exposed and developed using a mask having a rectangular pattern such as L / S (line and space) to form a rectangular recess 93 (FIG. 9B). reference). The recess 93 is a rectangular through hole in the insulating layer 91 alone. After that, the insulating layer in the developed part is dripped greatly by heat curing, and the top edge 95 and the bottom edge 96 as shown in FIG. 8 form a smoothly rounded recess 93 and harden ( (See FIG. 9C). Note that it is preferable to optimize the temperature and time of PEB (Post-Exposure-Bake) in order to appropriately promote the reaction in the exposed area. In this way, the insulating layer 94 having a corrugated shape is formed on the process substrate 92 and the like.

  Exposure and development can be performed by a conventionally known method. For example, a high pressure mercury lamp, a xenon lamp, etc. are used for exposure, and the developer is a solution obtained by adding a water-soluble organic solvent such as methanol or ethanol or a surfactant to an alkaline aqueous solution such as sodium hydroxide or sodium carbonate. Is used.

Each condition (exposure amount, heating temperature, etc.) of exposure, PEB, and heating cure is set to an optimum condition that causes the insulating layer to sag and smoothes the edge of the rectangular recess to a rounded state. . This optimum condition is selected depending on the insulating material used.

  As the insulating material, among the photosensitive resins, those in which the shape formed by development drastically sag due to heat at the time of heat curing and the bottom edge of the sag is a smooth rounded shape are preferable. Preferred examples of such photosensitive resins include WPR1050 and WPR S110, which are phenolic photosensitive resins. These photosensitive resins are high-resolution photosensitive insulating resins that can be used for WLCSP (Wafer Level Chip Size Package), etc., but suppress exposure and reaction by PEB, and perform post-exposure irradiation before curing (heating) In this case, the rectangular depressions droop greatly due to heat during curing, and the top and bottom edges of the depressions are rounded smoothly.

  Even if the insulating material is a photosensitive resin in which the top edge and the bottom edge are not smoothly rounded due to heat during normal curing, for example, if it is a resin whose edge is smoothly rounded by rapid heating, etc. Can be applied. Examples of such a resin include photosensitive polyimide. As a method of rapidly heating, there is a method of placing an insulating layer in which a rectangular depression is formed on a hot plate heated in advance to a predetermined high temperature, for example, about 200 ° C.

  Even if the insulating material is a non-photosensitive material, for example, a method of forming a pattern to be described later, or a rectangular through-hole is formed in the insulating layer by a laser or the like in a semi-cured state, and an appropriate temperature and temperature increase are made. Any resin can be used as long as the edge portion of the rectangular through hole hangs down by a method of heating at a speed and the top edge and the bottom edge are rounded smoothly. Examples of the non-photosensitive resin include non-photosensitive polyimide (manufactured by Ube Industries, trade name: Iupicoat), and non-photosensitive polyamideimide (trade name: HL-P200, manufactured by Hitachi Chemical Co., Ltd.).

  When the corrugated shape is formed by surface treatment, a rectangular recess is formed in an insulating layer formed on a process substrate or a wafer having a semiconductor element (referred to as a process substrate), and surface treatment such as plasma irradiation is performed. Then, process so that the edge of the indentation is rounded smoothly. In this case, in order to prevent the hollow formed in the rectangle from expanding, it is preferable to form a small hollow first. Note that the rectangular depression in the insulating layer can be formed by a method similar to the method described in the description of the heat treatment.

  When the corrugated shape is formed by treatment with a solvent, a rectangular recess 123 having a top edge 125 and a bottom edge 126 is formed in the insulating layer 121 formed on the process substrate 122 as shown in FIG. (See FIG. 12 (A)), by leaving it in a solvent atmosphere, the top edge 125 and the bottom edge 126 of the recess 123 are processed so as to be smoothly rounded (see FIG. 12 (B)). Note that the rectangular recess 123 as shown in FIG. 12A is a through hole of only the insulating layer 121, and can be formed in the insulating layer 121 by the same method as described above.

  The roundness of the top edge 125 and the bottom edge 126 can be controlled by the good solvent property of the solvent used for the insulating material, the standing time in the solvent atmosphere, and the standing temperature. That is, each edge is likely to be rounded if a solvent having a high good solvent property for the insulating material is used, and each edge is difficult to be rounded if a solvent having a low good solvent property for the insulating material (poor solvent) is used. Further, if the leaving time is lengthened, each edge is likely to be rounded, and if the leaving time is shortened, each edge is not easily rounded. Further, the degree of rounding of each edge can be changed by changing the standing temperature.

  By optimizing these conditions, although depending on the rectangular shape (size, etc.) of each depression, (i) an opening 127 where no insulating layer remains on the side of the process substrate 122 having a wiring portion, (ii) a recess 128 in which an insulating layer slightly remains on the process substrate 122 side, (iii) a recess 129 in which an insulating layer remains in an appropriate thickness on the process substrate 122 side, etc. The above indentations (in FIG. 12B, three types of “indentations” including the opening 127 and the two indentations 128 and 129 are illustrated) can be arbitrarily formed. As a result, a shape capable of obtaining an effective stress relaxation effect can be freely obtained.

  In the above heat treatment or surface treatment, when a photosensitive resin is used as the insulating material, two or more insulating layers can be formed, and a two-step depth can be formed by one exposure. This method utilizes the property that the smaller the hole, the slower the development speed due to the difference in the developer penetration speed. In other words, a fine hole can be a recess opened only in the upper layer, and a slightly larger hole (via) can be an opening opened to the lower layer. Accordingly, a rectangular recess having two levels of depth can be formed by a single exposure, and a rounded shape with a smooth edge can be easily formed during the heat treatment.

  In the case of forming a waveform shape by optical treatment, there are a method using a negative photosensitive resin and a method using a positive photosensitive resin as an insulating material. In any of these methods, a known photosensitive resin can be used.

  In the method of using a negative photosensitive resin as an insulating material, a mask having a rectangular pattern is masked on an insulating layer formed on a process substrate or the like so that it is slightly lifted, and this is exposed and developed to form a wavy shape. An insulating layer is formed. When exposure is performed with the mask slightly lifted, light for exposure leaks little by little from the edge of the mask, and the pattern shape obtained after development becomes rounded. Therefore, the process of rounding the edge after development can be omitted.

  In the method using a positive photosensitive resin as an insulating material, a large amount of an initiator is intentionally added, and this is exposed and developed to form a corrugated insulating layer. By adding a large amount of initiator to the positive photosensitive resin, it is possible to obtain a rounded top edge and bottom edge by reducing light transmittance and preventing light from reaching the bottom sufficiently.

  As another optical process, there is a method of forming a round shape by intentionally shifting the focus at the time of exposure to make the pattern cut worse.

  For the exposure / development, a conventionally known method exemplified in the description of the heat treatment can be used. The conditions such as the exposure amount are set so that the rectangular pattern sag and the bottom edge is rounded.

  As another method of forming a wave shape that is displaced in the thickness direction, a rectangular pattern is formed on an insulating layer formed on a process substrate, and the same resin or another resin is thinly applied thereon. Examples include a method in which a rectangular top edge and a bottom edge are smoothly rounded.

  The above-mentioned various treatments can easily form an insulating layer having a smooth waveform shape, and can further form an insulating layer having a sine wave shape or a substantially sine wave shape in cross section, and on a chip or wafer. Since the semiconductor is separated from the wiring, a good stress relaxation structure with less contact and less damage can be obtained.

  Next, another method for forming a plurality of recesses having different depths will be described.

  As shown in FIG. 13, the insulating layer having a corrugated shape is formed by forming an insulating layer 131 made of, for example, a positive photosensitive resin on the process substrate 132 (see FIG. 13A). It is formed by developing the insulating layer 131 after irradiating a different amount of light for each location using a mask from above 131 (see FIGS. 13B to 13D). According to this method, two or more kinds of depressions 133 and 134 having different depths can be formed in the insulating layer 131 (see FIGS. 13D and 13E). As a control of the amount of light to be irradiated (exposure amount), when forming the depression 133 (opening) that penetrates the insulating layer 131, the exposure amount is increased, and when forming the depression 134 that does not penetrate the insulating layer 131. Reduce exposure. Adjustment of the exposure amount at a desired location can be performed by performing multiple exposures using a plurality of masks to be exposed. By such means, a plurality of “dents” having different depths can be formed in the insulating layer 131.

  Specifically, as shown in FIG. 13A, a process substrate 132 on which an insulating layer 131 made of a positive photosensitive resin is formed is prepared, and the insulating layer 131 is formed as shown in FIG. Then, light is irradiated through the first mask 136 having a predetermined mask pattern. The exposure amount at this time is an amount by which the depression 134 that does not penetrate the insulating layer 131 can be formed. Next, as shown in FIG. 13C, the insulating layer 131 exposed through the first mask is irradiated with light through the second mask 137 having a predetermined mask pattern. The exposure amount at this time is set to an amount by which the sum of the exposure amount when the first mask 136 is used and the depression 133 (opening) penetrating the insulating layer 131 can be formed. Note that the first exposure amount using the first mask 136 and the second exposure amount using the second mask 137 may be the same. Next, as shown in FIG. 13D, by developing after performing the second exposure, one or more types of indentations 134 having different depths from the opening 133 or two or more types of different depths are formed. Recesses can be formed. Thereafter, as shown in FIG. 13E, the stress relaxation structure of the present invention can be formed by performing an operation of rounding the edge of the recess having a rectangular shape.

  Next, a case where a non-photosensitive resin is used as an insulating material will be described.

  When a non-photosensitive resin is used as the insulating material, the corrugated insulating layer is formed by processing the insulating layer made of the non-photosensitive resin. When a photosensitive resin is used as the insulating layer, the number of steps for forming an insulating layer having a predetermined shape is preferably reduced. However, since the photosensitive resin has a characteristic of being photosensitive, it has an elastic modulus and tensile fracture. The elongation rate may be limited. On the other hand, since the non-photosensitive resin does not have such a restriction, it has a low elastic modulus material and a high tensile elongation at break which are desirable as a material for the insulating layer of the present invention, compared to the case where the photosensitive resin is used. The material can be freely selected.

  Since the non-photosensitive resin does not have the pattern forming ability like the photosensitive resin, it is necessary to form a pattern by some method. As one method, there is a method in which a pattern is prepared in advance with a photosensitive resin and a pattern of a non-photosensitive resin is formed using this pattern as a mold. In this case, a pattern having a rectangular cross section of the non-photosensitive resin can be formed by applying the non-photosensitive resin on the pattern of the photosensitive resin and then removing the photosensitive resin. Thereafter, the stress relaxation structure of the present invention can be formed by performing an operation of rounding the edge of the hollow having a rectangular shape.

  In this pattern forming method, the shape of the photosensitive resin may be deformed when the non-photosensitive resin is applied, and there is a limitation that it is necessary to find a combination of resins that do not cause such deformation. In addition, the upper part of the photosensitive resin may be covered with the non-photosensitive resin. In this case, it is necessary to scrape the non-photosensitive resin on the photosensitive resin by a mechanical method such as cutting or polishing. When such treatment is necessary, problems such as insufficient mechanical strength of the photosensitive resin may occur.

  As a method for solving such a problem, for example, as shown in FIG. 14A, a metal pattern 145 using a plating method is formed on a process substrate 142, and then, as shown in FIG. 14B. Then, a non-photosensitive resin is applied on the metal pattern 145 by a spin coating method to form the insulating layer 141. Thereafter, as shown in FIG. 14C, the metal pattern 145 is removed by etching, whereby a pattern of the insulating layer 141 having a rectangular cross section of the non-photosensitive resin can be formed. Thereafter, as shown in FIG. 14D, the stress relaxation structure of the present invention can be formed by performing an operation of rounding the edge of the recess having a rectangular shape. In this method, there are advantages such that the plating is not deformed by application of the non-photosensitive resin, and that the plating is not deformed even if a mechanical operation such as cutting or polishing is performed.

  As the non-photosensitive resin to be used after forming the plating pattern, a solution can be applied by spin coating or the like, but a dry film can also be used.

  Further, in order to remove the plating pattern after applying the non-photosensitive resin on the plating pattern, the head of the plating film needs to be exposed. For this reason, it is desirable to make the thickness of the plating film larger than the thickness of the non-photosensitive resin. When a non-photosensitive resin thin film is formed on the plating film, the non-photosensitive resin thin film can be removed by a mechanical operation such as cutting or polishing. Further, the thin film of the non-photosensitive resin can be removed by using a chemical operation such as ashing. In addition, as an effective method, a film that is difficult to wet with a non-photosensitive resin such as a fluorine coating is formed on the head of the plating film in advance, and a solution of the non-photosensitive resin is repelled, so The part can also be exposed.

  The non-photosensitive resin can be patterned by forming a mask with a photosensitive resin or other material that can be patterned, and then performing patterning by a method such as dry etching or wet etching. As a mask for such etching, a photosensitive resin itself can be used, or a metal mask patterned using a photosensitive resin or the like can be used.

  Among these non-photosensitive resin patterning methods, the wet etching method needs to select a non-photosensitive resin that is soluble in a solvent as the insulating layer material. This method is applicable when a polyimide resin before curing is selected as the non-photosensitive resin. On the other hand, since patterning by the dry etching method is performed by plasma or the like, it can be applied to most non-photosensitive resins, but the etching rate is slightly low.

  In the stress relaxation structure of the present invention, an insulating layer having a total of two or more types of indentations with different depths is formed, such as an opening that penetrates only the insulating layer and one or more types of indents that do not penetrate the insulating layer. It is preferable. As a method for manufacturing such a multistage structure in one etching process, an insulating layer 151 made of a non-photosensitive resin is formed on a process substrate 152 or the like as shown in FIG. A method of performing etching after forming two or more kinds of mask layers 156 and 157 can be given.

  Specifically, as shown in FIG. 15A, first, a process substrate 152 on which an insulating layer 151 made of a non-photosensitive resin is formed is prepared, and then, as shown in FIG. A first mask 156 having a predetermined mask pattern is formed on the layer 151. Since the mask 156 is made of a material having resistance to dry etching such as Cu, the portion covered with the mask 156 is not etched and does not become a dent.

  Next, as shown in FIG. 15C, a second mask 157 having a predetermined mask pattern is formed over the insulating layer 151 provided with the first mask 156. Since this mask 157 is made of a material that does not have etching resistance to dry etching, such as a photosensitive resin, a portion where the mask 157 is not provided directly etches the insulating layer 151 to form a deep recess. be able to. On the other hand, in the portion where the mask 157 is provided, the insulating layer 151 is etched after the mask 157 is etched first, so that a shallow depression can be formed. Therefore, the thickness of the second mask 157 is such that an opening 159 (a through hole of only the insulating layer 151) can be formed in the insulating layer 151 by dry etching only once, and the second mask 157 is etched. After that, a part of the insulating layer 151 in the thickness direction is etched so that the recess 158 having a predetermined depth can be formed.

  Next, as shown in FIG. 15D, dry etching is performed. By dry etching, an opening 159 and one or more types of depressions 158 are formed in the insulating layer 151. Next, as shown in FIG. 15E, the mask 156 having etching resistance is removed, and as shown in FIG. 15F, an operation of rounding the edge of the recess having a rectangular shape is performed. A stress relaxation structure having a plurality of different indentations 160 and 161 can be formed. In this way, by forming a multi-stage mask, the mask 157 having no etching resistance causes a time difference in etching, and the indentation depth of the insulating layer 151 where the mask 157 without the etching resistance is present and where the mask 157 is not present. It can be changed. In this way, a multistage structure such as a depression can be produced by one etching.

  Next, a method for forming a wiring on a corrugated insulating layer will be described.

  By forming the wiring on the insulating layer described above, it is possible to easily form a corrugated wiring that is displaced in the thickness direction.

  As described above with reference to FIG. 4, the spiral wiring forms an insulating layer having a sinusoidal or substantially sinusoidal waveform that is displaced in the thickness direction on a process substrate or a wafer having a semiconductor element, A sinusoidal or substantially sinusoidal waveform shape displaced in the in-plane direction in plan view on the insulating layer, with inflection points alternately at the waveform top and waveform bottom in the thickness direction of the insulation layer. It is formed by forming a wiring.

  Specifically, a mask in which a mask pattern for wiring formation having a sine wave shape or a substantially sine wave shape is formed on an insulating layer having a waveform shape that is displaced in the thickness direction is aligned with the above-described position, It is formed by performing exposure / development processing and surface treatment. Note that when the mask pattern or the shape controlled in the thickness direction deviates from the sinusoidal shape, the spiral structure will be distorted, but even in that case, the shape may be sufficient as long as it has a stress relaxation function. No problem.

  Examples of the formation of the wiring on the insulating layer include a full additive method and a semi-additive method. For example, when copper wiring is formed by a semi-additive method, a seed layer is formed by metal sputtering on the insulating layer pattern formed as described above, and after applying a plating resist to a portion other than the wiring pattern, Plating can be performed to remove the resist and seed layer to form a copper wiring.

  When a thin layer made of a metal different from the main metal component constituting the wiring is provided on the chip or wafer side surface of the wiring, titanium or chromium is previously formed after the seed layer is formed and before the wiring is formed. Etc. can be provided.

(Semiconductor device)
As shown in FIG. 1, the semiconductor device of the present invention has a stress relaxation sheet 2 connected by soldering to a chip 5 on which a semiconductor element 6 is formed (see FIG. 1A), or a semiconductor A structure in which the mounting substrate 7 is connected to the chip 5 on which the element 6 is formed on the chip 5 (see FIG. 1B) directly connected to the mounting substrate 7 by a solder ball or the like. is there. Since the semiconductor device 1 having such a configuration has the stress relaxation structure of the present invention, the stress at the connection portion between the semiconductor element and the mounting substrate is relaxed. For example, a flip chip (FC) or a ball grid array ( The semiconductor device function is not easily disturbed by thermal stress without causing destruction of the land portion for BGA), destruction of the solder balls, cutting of the metal wiring inside the substrate, and the like, resulting in a highly reliable semiconductor device.

  The semiconductor element 6 may be a micro-electro-mechanical system (MEMS) manufactured using a silicon chip or a wafer in addition to an electrical semiconductor element. The mounting board 7 includes both an intermediate board such as an interposer and a board used for mounting to a housing such as a motherboard. The semiconductor chip and the mounting substrate can be connected by a known connection method such as wire bonding connection or flip chip connection. In a flip-chip type semiconductor device, a solder resist layer having a recess can be formed in a portion where a solder ball on the flip chip pad is mounted, and the solder ball can be mounted in the recess. At this time, in order to prevent the flip chip pad from being eroded by the solder, it is desirable to provide a barrier metal layer such as nickel and a gold layer that has good adhesion to the solder in this order in advance on the portion where the solder ball is mounted. . The semiconductor device 1 may be one in which an underfill is filled between the chip 5 on which the semiconductor element 6 is formed and the mounting substrate 7. Since the semiconductor device of the present invention already has a stress relaxation effect, it is possible to appropriately select the presence or absence of underfill according to the required reliability and other conditions.

  The electronic device according to the present invention incorporates such a semiconductor device, and the function of the semiconductor element is hardly hindered. In particular, the electronic device of the present invention has high reliability of the semiconductor function even if thermal stress is likely to be generated because the semiconductor element easily generates heat or thermal stress is likely to be generated depending on the use environment.

  Hereinafter, the present invention will be described in more detail based on examples and comparative examples. Note that the present invention is not limited thereby.

(Example 1)
A phenol-based photosensitive resin (manufactured by JSR, product name: WPR S110) was used as an insulating material, and an 8-inch wafer having one side of a test daisy chain wiring formed on the surface was used as a substrate. On this substrate, an insulating material for the insulating layer is applied and dried by spin coating so as to have a thickness of 20 μm, and then passed through a mask having a predetermined pattern, and then exposed to g-line by an exposure machine using a high-pressure mercury lamp as a light source. A mixed light of h-line and i-line was irradiated at 200 mJ / cm ² , and then PEB was performed at 100 ° C. for 3 minutes. As the mask, a mask capable of forming a depression for forming a waveform shape at a position where wiring is formed was used. Thereafter, development was performed with a 2.38 wt% TMAH aqueous solution. When the insulating layer after development was observed with a microscope, a clear rectangular pattern was formed.

  Next, heating curing was performed for 5 minutes at a curing temperature of 150 ° C. on a hot plate. When the shape of the heat-cured insulating layer was observed with an optical microscope and an electron microscope, it was confirmed that the formed rectangular pattern was softened and had a rounded smooth shape. Furthermore, the insulating layer was cured by heating at 190 ° C. for 30 minutes in a nitrogen atmosphere to obtain an insulating layer having a corrugated shape.

  Next, a seed layer for electroplating was formed in the order of titanium and copper by sputtering, and a plating resist was applied, exposed and developed through a predetermined mask, and an opening corresponding to the wiring pattern was formed. The used mask is formed with an FC pad pattern of 140 μmφ at a pitch of 200 μm in addition to the wiring portion. Thereafter, wiring and pads having a thickness of 5 μm were formed by copper electroplating, and the plating resist and the seed layer were peeled in this order to obtain a wafer on which the stress relaxation structure was directly formed. At this point, a copper-plated wiring having a corrugated shape was formed on the corrugated insulating layer, and the wiring on the wafer and a daisy chain for testing were configured. The wiring on the insulating layer had a length of about 80 μm and was arranged to extend in a diagonal direction close to the radial direction from the center of each semiconductor chip.

  Next, a plating resist layer was formed so as to have an opening in the pad portion, and then a nickel plating layer and a gold plating layer were formed in this order on the pad. Next, a solder resist layer was formed from a photosensitive resin, and was exposed and developed through a mask to form a solder resist layer having an opening at a portion corresponding to the pad.

  Thereafter, the wafer was cut into 17 mm square chips, and then solder balls were mounted on the solder resist openings to obtain semiconductor chips. The obtained semiconductor chip was mounted on a mounting substrate via solder balls, and the semiconductor device of Example 1 was obtained.

  Using the semiconductor device thus obtained, a thermal cycle test of −40 ° C. to 125 ° C. was performed for 1000 cycles, and the presence or absence of disconnection in the daisy chain portion was observed. As a result, disconnection was not confirmed even after 1000 cycles of the thermal cycle test. After the measurement, the cross section was observed, but no breakage of the wiring was observed. The tensile modulus of the film test piece of 1 cm × 8 cm photosensitive resin formed by the same formation method as the insulating layer of this semiconductor device was measured to be 2.0 GPa and the tensile elongation at break was 8.2. %Met. The tensile elastic modulus and the tensile elongation at break were measured by the measuring method described in the column of the embodiment of the invention.

(Example 2)
An insulating layer, a wiring, a pad, and a solder resist layer were formed in the same procedure as in Example 1, using a 0.25 mm thick copper plate as the process substrate and using the same insulating material as in Example 1. After that, a plating resist is applied to the process substrate, an opening is formed at a position to be an electrode on the chip side, a pad on the chip side is formed in the order of copper, nickel, gold, nickel, and copper, and each etching is performed. By using the liquid to remove the lower copper plate and the nickel of the lower layer pad, a stress relaxation sheet having pads corresponding to the chip side and the substrate side was obtained. Solder bumps were formed on the pads on the chip side of the stress relaxation sheet by printing, and solder balls were mounted on the mounting substrate side. Each surface of the stress relaxation sheet was connected to a chip on which a daisy chain wiring was formed and a mounting substrate to obtain a semiconductor device of Example 2.

  About the obtained semiconductor device, the thermal cycle test similar to Example 1 was done, and the disconnection in a daisy chain part was observed. As a result, disconnection was not confirmed even after 1000 cycles of the thermal cycle test. After the measurement, the cross section was observed, but no breakage of the wiring was observed.

(Example 3)
As the substrate, as in Example 1, an 8-inch wafer having a surface on one side of a test daisy chain wiring was used. On this substrate, the same insulating material as in Example 1 was applied and dried to a thickness of 20 μm by spin coating, and then exposed and developed in the same manner as in Example 1 through a mask having a pattern in which only the via portion was opened. Thereafter, heating was performed at 190 ° C. for 30 minutes in a nitrogen atmosphere to complete the curing of the first insulating layer.

  Next, after applying and drying the same insulating material as the first layer on the first insulating layer by spin coating so as to have a thickness of 20 μm, exposure is performed in the same manner as the first layer using a predetermined mask. After developing, it was cured as in Example 1. The mask used for the exposure at this time has a pattern in which only the via portion serving as the opening is exposed. When the shape of the obtained insulating layer was observed with an optical microscope and an electron microscope, the formed rectangular pattern was soft and rounded, and the via portion was open. A dent in the state where the wiring bottom was not opened was confirmed. Further, the insulating layer was cured by heating at 190 ° C. for 30 minutes in a nitrogen atmosphere. When a cross-sectional sample was prepared from a part of the sample and observed, a corrugated insulating layer having a two-stage depression with an opening in the via portion and no opening in the wiring portion was obtained.

  On the obtained two insulating layers, a wiring, a nickel plating layer, a gold plating layer, and a solder resist layer were formed in the same manner as in Example 1. In the same manner as in Example 1, chip cutting, solder ball mounting, and mounting on a mounting substrate were performed to obtain a semiconductor device.

  Using the obtained semiconductor device, a thermal cycle test of −40 ° C. to 125 ° C. was performed 1000 cycles, and the presence or absence of disconnection in the daisy chain portion was observed. As a result, disconnection was not confirmed even after 1000 cycles of the thermal cycle test. After the measurement, the cross section was observed, but no breakage of the wiring was observed.

(Example 4)
As the substrate, as in Example 1, an 8-inch wafer having a surface on one side of a test daisy chain wiring was used. On this substrate, a seed layer for electroplating was formed in the order of titanium and copper by sputtering, and a plating resist was applied on this seed layer. The thickness of the plating resist was 30 μm. A mask for forming only the insulating layer of the wiring portion as a through hole was used, and exposure and development were performed through the mask to form an opening (through hole) corresponding to a predetermined pattern. A copper plating pattern was deposited on the opening (through hole) by electrolytic copper plating to form a copper plating pattern, and then the plating resist was peeled off.

  A non-photosensitive resin (material is applied by spin coating?) Was dried at 80 ° C. for 2 minutes on the substrate on which the plating pattern was formed. When plasma ashing was applied for 10 minutes and observed with an optical microscope, it was confirmed that the upper part of the plating pattern was exposed. When the plating pattern was etched with the plating etching solution, a pattern of the non-photosensitive resin in which the via part and the wiring concave part were opened to form a through hole could be confirmed.

  The obtained sample was left for 30 minutes in an atmosphere of PGMEA (propylene glycol monoethyl acetate), which is a solvent for the non-photosensitive resin. When observing with an optical microscope, it was observed that only the wiring recess was filled up to about half, and the via portion was slightly opened with a slight side gradient. The insulating layer was completely cured by heating at 190 ° C. for 60 minutes in a nitrogen atmosphere.

  On the obtained insulating layer, a wiring, a nickel plating layer, a gold plating layer, and a solder resist layer were formed in the same manner as in Example 1. Similarly to Example 1, chip cutting, solder ball mounting, and mounting on a mounting substrate were performed to obtain a semiconductor device.

  Using the obtained semiconductor device, a thermal cycle test of −40 ° C. to 125 ° C. was performed 1000 cycles, and the presence or absence of disconnection in the daisy chain portion was observed. As a result, disconnection was not confirmed even after 1000 cycles of the thermal cycle test. After the measurement, the cross section was observed, but no breakage of the wiring was observed. When the film test piece of the non-photosensitive resin used similarly to Example 1 was produced and the tensile elasticity modulus was measured, it was 0.5 GPa and the tensile elongation at break was 30%.

(Example 5)
As the substrate, as in Example 1, an 8-inch wafer having a surface on one side of a test daisy chain wiring was used. On this substrate, a positive photosensitive resin was applied by spin coating and dried to form an insulating layer. Next, the first exposure was performed through a mask for exposing only the via portion, and then the second exposure was performed through a mask for exposing the via portion and the wiring recess. This second exposure was performed by equal light exposure with the same light amount as the first exposure. Thereafter, development was performed to obtain a pattern in which only the via portion was opened and the wiring recess was opened to about half the depth. Heating at 190 ° C. for 30 minutes in a nitrogen atmosphere completed the curing of the photosensitive resin insulating layer.

  On the obtained insulating layer, a wiring, a nickel plating layer, a gold plating layer, and a solder resist layer were formed in the same manner as in Example 1. Similarly to Example 1, chip cutting, solder ball mounting, and mounting on a mounting substrate were performed to obtain a semiconductor device.

  Using the obtained semiconductor device, a thermal cycle test of −40 ° C. to 125 ° C. was performed 1000 cycles, and the presence or absence of disconnection in the daisy chain portion was observed. As a result, disconnection was not confirmed even after 1000 cycles of the thermal cycle test. After the measurement, the cross section was observed, but no breakage of the wiring was observed.

(Example 6)
As the substrate, as in Example 1, an 8-inch wafer having a surface on one side of a test daisy chain wiring was used. On this substrate, the same insulating material as in Example 3 was applied by spin coating to a thickness of 20 μm, dried and cured.

  Next, a sputtered film of copper was formed on the cured insulating material, a photosensitive resin was applied thereon, and then exposed and developed to obtain a sputtered film pattern in which via portions and wiring recesses were opened.

  10 μm of a non-photosensitive resin (plating resist) was applied on the obtained sample, and was exposed and developed to obtain a pattern in which via portions and wiring concave portions were opened.

  The obtained sample was subjected to an ashing operation using oxygen plasma. When observing with an optical microscope after ashing, an insulating layer having a pattern in which only the via portion was opened and the wiring concave portion was opened about half was confirmed. Further, the shape of the insulating layer was round with rounded corners due to the wraparound of the plasma.

  On the obtained insulating layer, a wiring, a nickel plating layer, a gold plating layer, and a solder resist layer were formed in the same manner as in Example 1. Similarly to Example 1, chip cutting, solder ball mounting, and mounting on a mounting substrate were performed to obtain a semiconductor device.

  Using the obtained semiconductor device, 1000 cycles of a thermal cycle test of −40 ° C. to 125 ° C. was performed, and disconnection at the daisy chain portion was observed. As a result, disconnection was not confirmed even after 1000 cycles of the thermal cycle test. After the measurement, the cross section was observed, but no breakage of the wiring was observed.

  (Comparative Example 1) In the manufacture of the semiconductor device of Example 1, instead of forming the corrugated shape of the insulating layer, after applying and drying the insulating material, an opening was formed only at the connection portion with the wafer and via was performed. Produced a semiconductor device in the same procedure as in Example 1. In this semiconductor device, the insulating layer was flat and the wiring was linear.

  When the obtained semiconductor device was subjected to the same thermal cycle test as in Example 1, disconnection occurred in all the test pieces in 200 to 400 cycles. When the cross section was observed after the test, it was confirmed that the wiring was disconnected beside the via at the connection portion with the wafer.

  The stress relaxation structure and the stress relaxation sheet of the present invention are provided between the chip on which the semiconductor element is formed and the mounting substrate, so that the corrugated wiring included in the stress relaxation structure has an effect as a spring structure, The thermal stress generated in the semiconductor device can be efficiently absorbed. Therefore, the stress relaxation structure is applied to the semiconductor device, so that stress at the connection portion between the semiconductor element and the mounting substrate is relieved, for example, destruction of a land portion for flip chip connection, semiconductor element and mounting substrate Thus, a highly reliable semiconductor device can be obtained without causing destruction of solder balls and wiring for connecting the wiring and wiring inside the mounting substrate. Particularly effective when applied to large semiconductor devices with large thermal stress, semiconductor devices using materials with low mechanical strength such as Low-K materials, or packages such as flip chip ball grip arrays (FCBGA) with many pins. It is.

  In addition, according to the method for forming a stress relaxation structure of the present invention, a stress relaxation structure having a large stress relaxation effect such as a multistage structure can be easily formed, and a low-elasticity, high fracture elongation material effective for stress relaxation can be obtained. There is a merit that it can be used.

It is sectional drawing which shows an example of the semiconductor device which has a stress relaxation structure of this invention. It is a top view which shows an example of the semiconductor device which has a stress relaxation structure of this invention. It is a top view which shows an example of the semiconductor device which has a stress relaxation structure containing a helical wiring. They are a plan view (A) showing an example of a mode in which a spiral wiring is provided on an insulating layer, and a C-C ′ sectional view (B) thereof. It is the schematic which shows an example of the aspect from which the width | variety of the wiring which exhibits a waveform shape differs in each part. It is sectional drawing which shows an example of the stress relaxation structure of this invention containing the insulating layer of 2 layer structure, and sectional drawing which shows an example of the stress relaxation structure of this invention provided with the waveform shape which has a some top part. It is a top view which shows an example of the semiconductor device with which the extension direction of the wiring which has a waveform shape is a predetermined direction. It is a perspective view which shows the shape of a corrugated insulating layer. It is an example of a process of forming a corrugated insulating layer on a wafer on which a semiconductor element is formed. It is a schematic diagram for demonstrating the thermal stress which arises between a semiconductor chip and a mounting substrate. It is sectional drawing which shows an example of the semiconductor device which has the conventional stress relaxation function. It is a figure which shows an example of the formation method of the stress relaxation structure of this invention. It is a figure which shows an example of the formation method of the stress relaxation structure of this invention. It is a figure which shows an example of the formation method of the stress relaxation structure of this invention. It is a figure which shows an example of the formation method of the stress relaxation structure of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Stress relaxation sheet (stress relaxation structure)
3, 21, 31, 42, 51, 63, 65 Wiring 4, 41, 52, 60, 61, 62, 91, 121, 131, 141, 151 Insulating layer 5, 53, 64, 101 Chip 6, 68 Semiconductor element 7, 102 Mounting substrate 8, 67, 103 Solder ball 9, 66 Other insulating layers 22, 93, 123, 127, 128, 129, 133, 134, 158, 159, 160, 161 Recess 23 Wiring connection portion 24 Pad 43 Waveform top 44 Waveform bottom 92, 122, 132, 142, 152 Process substrate, etc. 94 Insulating layer 95, 125 Top edge 96, 126 Bottom edge 111 Semiconductor device 114 Semiconductor element electrode portion 136, 137, 156, 157 Mask 145 metal pattern

Claims (29)

  A stress relaxation structure including an insulating layer having a corrugated shape existing between a chip on which a semiconductor element is formed and a mounting substrate, and a wiring formed on the insulating layer, wherein the wiring has a corrugated shape. A stress relaxation structure characterized by comprising:   The stress relaxation structure according to claim 1, wherein a waveform shape of the wiring is displaced in a thickness direction.   The stress relaxation structure according to claim 1, wherein a waveform shape of the wiring is displaced in an in-plane direction.   The wiring waveform has a spiral shape formed by superposing a sine wave shape or a substantially sine wave shape displaced in the thickness direction and a sine wave shape or a substantially sine wave shape displaced in the in-plane direction. The stress relaxation structure according to any one of claims 1 to 3.   The stress relaxation structure according to claim 1, wherein a width of the wiring is different between an upper portion and a lower portion in a thickness direction.   The stress relaxation structure according to claim 1, wherein an extension direction of the wiring is parallel or substantially parallel to a virtual line extending in a radial direction from the center of the chip.   The extension direction of the wiring is constant in each quadrant arranged symmetrically four times with respect to the center of the chip, and the extension direction passes through the symmetry point among the diagonal axes in each quadrant. The stress relaxation structure according to any one of claims 1 to 6, wherein the stress relaxation structure is parallel or substantially parallel to a diagonal axis.   The said wiring is a metal wiring, The thin layer which consists of a metal different from the main metal component which comprises the said metal wiring is provided in the said chip side surface of the said metal wiring. The stress relaxation structure according to any one of the above.   The stress relaxation structure according to any one of claims 1 to 8, wherein a tensile elastic modulus of the insulating layer is 1 GPa or less.   The stress relaxation structure according to any one of claims 1 to 9, wherein the tensile breaking elongation of the insulating layer is 10% or more.   The stress relaxation structure according to claim 1, wherein the insulating layer includes two or more insulating layers.   The stress relaxation structure according to any one of claims 1 to 11, wherein the corrugated shape of the insulating layer includes one or more types of depressions.   The stress relaxation structure according to claim 1, wherein the insulating layer is formed adjacent to the chip.   A stress relaxation sheet used for relaxing stress between a chip on which a semiconductor element is formed and a mounting substrate has the stress relaxation structure according to any one of claims 1 to 13. Stress relaxation sheet.   A semiconductor device comprising the stress relaxation structure according to claim 1 or the stress relaxation sheet according to claim 14.   An electronic apparatus in which the semiconductor device according to claim 15 is incorporated.   A method of forming a stress relaxation structure including an insulating layer having a corrugated shape existing between a chip on which a semiconductor element is formed and a mounting substrate, and a wiring formed on the insulating layer. Alternatively, a stress relaxation structure forming method comprising: forming an insulating layer having a corrugated shape that is displaced in a thickness direction on a wafer having a semiconductor element; and forming a wiring having a corrugated shape on the insulating layer.   The insulating layer having the corrugated shape is formed by forming an insulating layer on a process substrate or a wafer having a semiconductor element, forming a rectangular recess in the insulating layer, and then performing heat treatment or surface treatment. The method of forming a stress relaxation structure according to claim 17.   The insulating layer having the corrugated shape is formed by forming an insulating layer on a process substrate or a wafer having a semiconductor element, and forming a rectangular recess in the insulating layer and then placing the insulating layer in a solvent atmosphere. The method of forming a stress relaxation structure according to claim 17.   The material of the said insulating layer is photosensitive resin, The rectangular hollow of the said insulating layer is formed by exposing and developing the said insulating layer, The any one of Claims 17-19 characterized by the above-mentioned. A method for forming the stress relaxation structure as described.   The insulating layer having the wavy shape is formed by forming an insulating layer made of a negative photosensitive resin on a process substrate or a wafer having a semiconductor element, and floating the mask on which a rectangular pattern is formed. The method of forming a stress relaxation structure according to claim 17, wherein the stress relaxation structure is formed by exposing and developing the substrate.   The insulating layer having the wavy shape is formed by forming an insulating layer made of a positive photosensitive resin having low transmittance on a process substrate or a wafer having a semiconductor element, and exposing and developing the insulating layer. The method of forming a stress relaxation structure according to claim 17.   The insulating layer having the corrugated shape includes two or more types of depressions, and the insulating layer forms an insulating layer made of a positive photosensitive resin on a process substrate or a wafer having a semiconductor element, The method of forming a stress relaxation structure according to claim 17, wherein the insulating layer is developed after irradiating different amounts of light for each location.   The stress relaxation structure according to any one of claims 20 to 23, wherein the insulating layer includes two or more layers, and two or more kinds of depressions are formed in the insulating layer by one exposure. Forming method.   The method for forming a stress relaxation structure according to any one of claims 17 to 19, wherein the corrugated insulating layer is formed by processing a non-photosensitive resin.   The insulating layer having the corrugated shape includes two or more types of depressions, and the insulating layer forms an insulating layer made of a non-photosensitive resin on a process substrate or a wafer having a semiconductor element, 20. The method of forming a stress relaxation structure according to claim 17, wherein two or more mask layers are formed on the insulating layer, and then the insulating layer is etched. .   The insulating layer having the corrugated shape is formed by applying a non-photosensitive resin after forming a plating pattern on a process substrate or a wafer having a semiconductor element, and then etching and removing the plating pattern. The method for forming a stress relaxation structure according to claim 17, wherein the stress relaxation structure is formed.   A sinusoidal wave that includes a corrugated insulating layer that exists between a chip on which a semiconductor element is formed and a mounting substrate, and a wiring formed on the insulating layer, and the wiring is displaced in the thickness direction. A method of forming a stress relaxation structure having a spiral shape formed by superimposing a shape or a substantially sine wave shape and a sine wave shape or a substantially sine wave shape displaced in an in-plane direction, on a process substrate or a semiconductor element An insulating layer having a sinusoidal or substantially sinusoidal waveform that is displaced in the thickness direction is formed on a wafer having a sine wave shape or a substantially sinusoidal shape that is displaced in an in-plane direction in plan view on the insulating layer. Stress relaxation, characterized in that a spiral-shaped wiring is formed by forming a wiring having a wavy waveform shape and alternately having inflection points at the waveform top and waveform bottom in the thickness direction of the insulating layer Structure formation method.   A method for producing a stress relaxation sheet, comprising: forming a stress relaxation structure on the process substrate by the method according to any one of claims 17 to 28; and then peeling or removing the process substrate.

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