JP2005039055A - Exposing mask, its manufacturing method, exposing method, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an exposing mask prevented from being damaged due to the electrification of an object to be exposed at the time of exposure and capable of preventing the positional accuracy and resolution of an exposure pattern from being deteriorated due to vibration, a method for manufacturing the exposing mask, an exposing method, and a method for manufacturing a semiconductor device. <P>SOLUTION: The exposing mask 100 is constituted of a supporting frame 4, beams 5 for supporting a membrane 6 integrally with the supporting frame 4, the membrane 6 composed of a pattern forming part 7 or the like in which electron beam penetration holes 9 are formed, conductive projections 11, and so on. The height of the conductive projection 11 is the same as a distance between the mask 100 and an object to be exposed (e.g. a resist layer on a semiconductor wafer) at the time of exposure. Consequently, the conductive projections 11 can be brought into contact with the object to be exposed almost without applying stress to the mask 100 and the object and the generation of electrification and vibration can be prevented. The contact position is a non-circuit pattern forming area such as scribe lines. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an exposure mask, a manufacturing method thereof, an exposure method, and a semiconductor device manufacturing method.

  In recent years, semiconductor devices are increasingly miniaturized and are going to exceed the resolution limit of lithography using ultraviolet light. For this reason, a fine processing technique for drawing a fine circuit pattern using a charged particle beam such as an electron beam or an ion beam or an X-ray has been developed.

  For example, in the conventional direct drawing method in which a semiconductor wafer or the like is scanned and exposed with a focused electron beam, the data amount increases as the pattern becomes finer, the drawing time becomes longer, and the productivity (throughput) decreases. . In view of this, an electron beam projection exposure apparatus or an ion beam projection exposure apparatus has been proposed in which an exposure mask having a predetermined circuit pattern is irradiated with an electron beam, an ion beam, or the like, and the circuit pattern is collectively transferred onto the wafer.

  These exposure techniques include, for example, electron beam transfer lithography (EPL: Electron Projection Lithography, HCPfeiffer et al., Jpn. J. Appl. Phys., (1995), 34, 6658 using a high energy electron beam. Low-energy electron beam proximity projection lithography using low-energy electron beams (see LEEPL: Low Energy Electron-beam Proximity projection Lithography, T. Utsumi, US Patent No. 5831272 (3 November 1998)), ion beam Ion beam transfer lithography (see Ion Projection Lithography, H. Loeschner et al., J. Vac. Sci. Technol., (2001), B19, 2520).

  As electron beam transfer type lithography, PREVAIL (Projection Exposure with Variable axis Immersion Lenses) jointly developed by IBM and Nikon, SCALPEL (Scattering with Angular Limitation in Projection Electron-beam Lithography) developed by Lucent Technology, etc., and Tokyo Seimitsu And LEEPL (Low Energy Electron-beam Proximity Projection Lithography) jointly developed by Sony.

  For PREVAIL and SCALPEL, a high energy electron beam having an acceleration voltage of about 100 kV is used. In the case of PREVAIL and SCALPEL, the electron beam transmitted through a part of the mask is imaged on the resist by a reduction projection system of 4 times, and the pattern is transferred.

  On the other hand, a low energy electron beam having an acceleration voltage of about 2 kV is used for LEEPL (T. Utsumi, J. Vac. Sci. Technol. B 17, p. 2897, (1999), H. Nakano et al., Proc. (See SPIE 4754, p.827, (2002).) LEEPL has an advantage that the configuration of the electron lens barrel can be simplified as compared with PREVAIL and SCALPEL.

  In general, as the electron acceleration voltage increases, the scattering of electrons in the resist decreases, and the probability that the electrons react with the resist decreases. Therefore, in lithography using a high energy electron beam, a resist with higher sensitivity is required. On the other hand, since LEEPL has a low electron beam energy, the resist can be used with high sensitivity and high productivity can be realized.

  An exposure mask used in LEEPL is a stencil-like mask having a structure different from that of a mask used in conventional optical lithography, and is called a stencil mask. The stencil mask is a membrane (thin film) that does not transmit the exposure electron beam. Electron beam passage holes are provided corresponding to the exposure pattern, and the electron beam that has passed through the beam passage holes forms a resist on the wafer. By exposing it, the pattern on the mask is transferred onto the wafer at the same magnification.

  In the stencil mask, a very thin membrane is used for the purpose of preventing the beam passing through the electron beam passage hole from being reflected by the side wall of the hole and impairing the pattern accuracy. Further, in order to process the beam passage hole with high accuracy by etching, the membrane should be thin. Specifically, a thin film such as silicon, silicon carbide, or diamond having a thickness of about 100 nm to 10 μm is used as the membrane.

  FIG. 14 is a schematic cross-sectional view showing a state in the vicinity of the exposure mask 200 when exposure is performed in LEEPL using the conventional exposure mask 200. In LEEPL, an exposure mask (stencil mask) 200 is provided so that the resolution of the electron beam 32 that has passed through the electron beam passage hole 9 does not decrease before reaching the exposure surface due to repulsion between electrons. Exposure is carried out by arranging it at a position very close to the exposure surface. Specifically, the gap between the exposure mask 200 and the electron beam resist 42 is several tens of μm, for example, about 30 μm.

For this reason, as a problem of LEEPL exposure, there is a problem that mask breakage occurs due to electrostatic force due to charging of the wafer. When the semiconductor wafer 40 on which the insulating film 41 is formed is exposed by LEEPL, the insulating film 41 and the electron beam resist 42 on the semiconductor wafer 40 are charged and expressed by the following equation (1) between the exposure mask and the semiconductor wafer 40. Electrostatic force (Coulomb force) F is applied.
F = εSV ² / 2G ² (1)
Here, ε is the dielectric constant, S is the charged area of the wafer, V is the potential of the charged region, and G is the distance between the exposure mask and the electron beam resist 42. When a load exceeding the yield stress of the material of the membrane 6 is applied by the electrostatic force F, the exposure mask is damaged.

  As a method for preventing the insulating film 41 and the electron beam resist 42 from being charged, a technique of releasing a charge by applying a conductive organic film on the surface of the resist 42 is known in the electron beam direct writing method. For example, commercially available products such as aqua SAVE (trade name) from Mitsubishi Rayon and Espacer (trade name) from Showa Denko have been developed, and their typical film thickness is about 50 to 70 nm.

  However, in the case of LEEPL, since the acceleration voltage is as small as about 2 kV, the penetration depth of electrons into the resist 42 is only 100 nm, and when a conductive organic film is applied, most of the electrons lose energy in the conductive organic film. As a result, the resist cannot be exposed. Further, the resolution is degraded due to forward scattering of the conductive organic film. Further, when the conductive organic film is used, if the electron beam resist 42 is thinned as a countermeasure against a decrease in the penetration depth of electrons, another problem that etching resistance of the resist 42 deteriorates occurs. From these points, it is considered that introduction of the conductive organic film has a great disadvantage in LEEPL.

  On the other hand, a method for preventing charging of the exposure mask 200 by forming a metal layer on the surface of the membrane 6 or using a conductive material for the membrane 6 has been proposed (for example, a patent described later). See references 1 and 2.) However, since these exposure masks 200 are used in a state where there is no electrical contact with the wafer 40, prevention of charging of the exposure mask 200 does not help prevention of charging of the wafer 40.

  As another problem of LEEPL exposure, there is a problem that resolution and position accuracy are deteriorated due to vibration during exposure. When the exposure mask or the semiconductor wafer 41 vibrates during exposure, the high frequency component causes degradation of resolution and the low frequency component causes degradation of position accuracy.

  In order to reduce these vibrations, the LEEPL technology adopts the SLA (Scattered Light Allignment) alignment method (see T.Miyatake and M.Hirose, Proc. SPIE 3048, p.225 (1997)). The relative position of the exposure mask 200 or the semiconductor wafer 40 is measured with a microscope, and the position and rotation component of the wafer stage 50 and the mask holder (not shown) are controlled in real time.

  However, in the SLA method, a CCD (Charge Coupled Device) image capture and signal processing require a finite time, so that high frequency components cannot be detected. Furthermore, even if sudden vibrations occur, it takes a finite time to detect the vibrations and complete the correction, and since exposure proceeds during this time, degradation of position accuracy and resolution is inevitable. .

JP 2002-34710 A (Page 8, FIGS. 1 and 2) JP 2003-37055 A (4th and 6th pages, FIG. 3)

  In view of the above circumstances, the object of the present invention is that there is no risk of damage to the exposure mask due to charging of the exposure object during exposure, and there is no deterioration in the position accuracy or resolution of the exposure pattern due to vibration. It is an object of the present invention to provide a mask, a method for manufacturing the same, an exposure method, and a method for manufacturing a semiconductor device.

  That is, according to the present invention, an exposure beam passage hole penetrating from one surface side to the other surface side is formed in a predetermined pattern, and exposure of the predetermined pattern is performed on an exposure target by the exposure beam passing through the exposure beam passage hole. An exposure mask used for the first exposure mask, having a conductor in contact with the exposure target on a surface facing the exposure target at the time of exposure, and An exposure beam passage hole penetrating from one surface side to the other surface side is formed in a predetermined pattern, and is used for exposure of the predetermined pattern on an exposure target by the exposure beam passing through the exposure beam passage hole. The mask relates to a second exposure mask having a protrusion having a height in contact with the exposure target on a surface facing the exposure target during exposure.

  Further, in the method for manufacturing the exposure mask, a conductor material or a projection material is deposited on a surface facing the exposure target using a mask, and the conductor or the projection is formed in a predetermined pattern. A method of manufacturing an exposure mask, comprising: a step of patterning a surface facing the object to be exposed to form the conductor or the protrusion. It relates to the manufacturing method.

  Further, when exposing the exposure target to a predetermined pattern using the exposure mask, the mask pattern portion of the exposure mask and the exposure target are held at a predetermined interval, and the conductor or the protrusion is The present invention relates to an exposure method in which the exposure is performed while being in contact with the object to be exposed, and when the resist layer on the semiconductor wafer is exposed to a predetermined pattern using the exposure mask, the mask pattern portion of the exposure mask And the resist layer at a predetermined interval, the exposure is performed while the conductor or the protrusion is in contact with the resist layer, and the resist is developed after the exposure. It is related to.

  Since the first exposure mask or the second exposure mask of the present invention has a conductor or protrusion having a height in contact with the exposure target on the surface facing the exposure target at the time of exposure, these exposures are performed. When the exposure target is exposed to a predetermined pattern using a mask for the exposure, if the mask pattern portion of the exposure mask and the exposure target are held at a predetermined interval, stress is almost applied to the exposure mask and the exposure target. Without adding, the conductor or the protrusion can be brought into contact with the exposure object.

  According to the exposure method of the present invention, since the exposure is performed in the above-described state, a conductive connection is formed between the exposure mask and the exposure target by using the first exposure mask. Therefore, both are kept at the same potential, and there is no fear that the exposure mask is damaged by the electrostatic force resulting from the charging of the exposure object. If the second exposure mask is used, the exposure mask and the exposure object are integrated by contact with each other, so that the position accuracy and resolution of the exposure pattern are not deteriorated by vibration or the like. At this time, since the stress applied to the exposure mask or the exposure target by the contact is slight, there is a concern that the exposure mask or the exposure target may be distorted and damaged or a contaminant may be generated. rare.

  The method for manufacturing a semiconductor device of the present invention applies the exposure method when exposing a resist layer on a semiconductor wafer to a predetermined pattern, and thus has the same characteristics as the exposure method, If an exposure mask is used, there is no risk of damage to the exposure mask due to charging of the resist layer, and if a second exposure mask is used, the positional accuracy and resolution of the exposure pattern deteriorates due to vibration or the like. There is no. At this time, there is almost no fear that the exposure mask and the object to be exposed are damaged or that contaminants are generated by the contact of the conductor or the protrusion with the resist layer.

  Further, according to the method for manufacturing an exposure mask of the present invention, a conductor material or a projection material is deposited on a surface facing the exposure target using a mask, and the conductor or the projection is predetermined. Since it has a step of forming a pattern, or a step of patterning a surface facing the object to be exposed to form the conductor or the protrusion, it is surely efficient and has a predetermined height. An exposure mask having a conductor or the protrusion can be manufactured.

  In the present invention, the conductor is preferably composed of at least one conductive protrusion. This is because in order to form a conductive connection between the exposure mask and the object to be exposed, both need only be connected in at least one place. Further, it is preferable that the protrusion is composed of at least three insulating or conductive protrusions. This is because contact at three or more locations is desirable in order to form a relationship in which the exposure mask and the object to be exposed support each other dynamically and stably.

  The exposure beam may be a charged particle beam. The exposure target may be a semiconductor wafer having a resist layer provided on the surface thereof. The present invention is most effective when a fine pattern that cannot be formed by photolithography is formed on the semiconductor wafer by the charged particle beam such as an electron beam or an ion beam.

  In addition, the portion where the conductor or the protrusion is in contact with the object to be exposed and the vicinity thereof are disposed outside the circuit pattern region, or are disposed in the circuit pattern region which does not hinder device operation even if foreign matter is generated. Is good. This is because damage or contamination due to contact with the conductor or the protrusions cannot be said to occur at all, and the influence thereof is suppressed as much as possible to improve the performance and manufacturing yield of the device.

  In addition, after the exposure in one exposure area is completed, the conductor or the protrusion and the exposure target are separated, and in this state, the relative position of the exposure target with respect to the exposure mask is changed to the next exposure area. The step of moving and the step of bringing the conductor or the protrusion again into contact with the exposure target at the moving position and performing the exposure on the exposure target are performed at least once on the exposure target. It is preferable to form the exposure pattern. As a result, it is possible to prevent an accident in which the exposure object contacts the exposure mask during movement.

  Further, the exposure may be performed by arranging the conductor or the protrusion in a non-exposed region. This is because, as described above, it cannot be said that there is no damage or contamination due to the contact of the conductor or the protrusions, so that the influence is suppressed as much as possible.

  In the method for manufacturing a semiconductor device, the exposure may be performed by arranging the conductor or the protrusion in a non-exposed region. Moreover, it is preferable to etch the lower layer into a predetermined pattern using the resist pattern formed by development.

  Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

Exposure Mask FIG. 1A is a cross-sectional view taken along line AA of an exposure mask (stencil mask) 100 according to the present embodiment, and FIG. 1B is a top view thereof. The exposure mask 100 includes a support frame 4 for maintaining the rigidity of the entire mask 100, a beam 5 that supports the membrane 6 integrally with the support frame 4, a membrane 6 that is supported by the support frame 4 and the beam 5, and a book. It consists of a conductive protrusion 11 or the like that hits a conductor or protrusion that is a feature of the invention.

  The shape of the support frame 4 is preferably a shape that forms the outer periphery of the mask without a break in order to maintain rigidity. For example, when the support frame 4 is formed from a disc-shaped silicon wafer, the central portion of the disc is cut into a rectangular shape and the outer peripheral portion is left completely. The shape of the beam 5 is not particularly limited, but generally a lattice shape is convenient.

  Desirably, the support frame 4 and the beam 5 are made of materials having similar coefficients of thermal expansion so that they will not be deformed even if the temperature of the exposure mask 100 rises due to heating by absorption of the exposure electron beam. More preferably, the support frame 4 and the beam 5 are made of the same material, and are made of a solid material by a method described later. Examples of the material of the support frame 4 and the beam 5 include silicon oxide, silicon nitride, silicon carbide, and metal materials (for example, gold, silver, chromium, tungsten, platinum, palladium, titanium, etc.) in addition to the silicon wafer. Can do.

  The membrane 6 includes a pattern forming portion 7 in which an electron beam passage hole 9 corresponding to an exposure pattern is formed, and a support portion 8 that is joined to the support frame 4 or the beam 5 and is disposed so as to surround the pattern forming portion 7. (In FIG. 1B, the electron beam passage hole 9 is not shown). As shown in FIG. 1B, the entire membrane region 6 surrounded by the support frame 4 is divided into a large number of pattern forming portions 7 by a support portion 8 joined to the beam 5. In the figure, an example in which the image is divided into 16 small areas is shown. However, this is for convenience of illustration, and is usually divided into a larger number of small areas.

  As described above, it is preferable that the membrane 6 be thin in order to suppress scattering of electrons on the side wall of the beam passage hole 9 and to process the beam passage hole 9 with high accuracy by etching. Specifically, a thin film such as a single crystal silicon layer having a thickness of about 0.3 to 0.6 μm is used as the membrane.

  In general, the thinner the membrane 6, the more easily the membrane 6 bends, and the deflection of the membrane 6 causes distortion of the transferred pattern and displacement of the pattern. However, according to the present embodiment, as described above, the membrane 6 is supported by being divided into a large number of small regions by the beams 5, so that the deflection of the membrane 6 is suppressed, and the distortion of the transferred pattern and the position of the pattern are suppressed. Deviation can be minimized.

  A problem in forming the beam 5 is that it becomes impossible to form the electron beam passage hole 9 at the position of the beam 5, but this problem can be solved by performing multiple exposure using a complementary mask. (See JP 2003-59819 A). Multiple exposures with complementary masks are usually used with stencil masks to form so-called donut-shaped exposure patterns and line and space exposure patterns with a large aspect ratio (aspect ratio). Therefore, no extra burden is caused by the formation of the beam 5.

  The material of the membrane 6 is excellent in rigidity and preferably has a high heat transfer coefficient in order to quickly dissipate heat generated by absorption of the electron beam. In addition to single crystal silicon, silicon oxide, silicon nitride, carbonized carbon is preferable. Examples thereof include silicon, polycrystalline diamond, titanium nitride, titanium oxynitride TiON, and metal materials (eg, gold, silver, chromium, tungsten, platinum, palladium, titanium, etc.).

  The height of the conductive protrusion 11 corresponding to the conductor or protrusion, which is a feature of the present invention, is the distance (10 μm or more, usually between the exposure mask 100 and the exposure target (for example, a resist layer on a semiconductor wafer) at the time of exposure. 30 to 50 μm). For example, when the distance between the exposure mask 100 and the exposure target is 30 μm, the conductive protrusion 11 is formed to a thickness of 30 μm.

  When the height of the conductive protrusion 11 is set in this way, when the pattern forming portion 7 of the exposure mask 100 and the exposure target are held at a predetermined distance (for example, 30 μm), the exposure mask 100 and the exposure target are separated. The conductive protrusion 11 can be brought into contact with the exposure target with almost no stress (as will be described later, the exposure mask 100 is brought close to the exposure target as will be described later, and the conductive protrusion 11 It is preferable that the exposure mask 100 and the exposure target are fixed and held when they are slightly in contact with the exposure target.

  In this embodiment, since exposure is performed in this state, the exposure mask 100 and the exposure target are electrically connected by the contact of the conductive protrusions 11, and both are kept at the same potential. There is no fear that the exposure mask 100 will be damaged by the electrostatic force resulting from the charging. Further, when the conductive protrusions 11 come into contact with the exposure target at four locations, the exposure mask 100 and the exposure target are in a fixed relationship with each other, and are integrated. Resolution does not deteriorate.

  At this time, since the stress applied to the exposure mask 100 or the exposure target by contact is slight, there is almost no fear that the exposure mask 100 or the exposure target is distorted due to this, or a contaminant is generated.

Production of exposure mask (1)
In this embodiment, an example will be described in which a metal is deposited by vapor deposition to form the conductive protrusions 11 and the exposure mask 100 shown in FIGS. 1A and 1B is manufactured. FIG. 2 is a flowchart showing a process of manufacturing the exposure mask 100, and FIGS. 3 and 4 are schematic sectional views showing the process.

  FIG. 3A shows an SOI (Silicon On Insulator) in which a silicon oxide layer 2 and a single crystal silicon film 3 having a thickness of about 0.3 μm are formed on a silicon substrate (wafer) 1 made of single crystal silicon. It is sectional drawing which shows a wafer. The single crystal silicon film 3 of the SOI wafer is processed into a membrane 6 by the following process, and the silicon substrate 1 is supported by the support frame 4 that maintains the rigidity of the entire mask, and the beam 5 that supports the membrane 6 integrally with the support frame 4. To process.

  First, as shown in FIG. 3B, a resist film is applied to the back surface of the silicon substrate 1 and then exposed and developed to form a resist pattern 21 patterned corresponding to the shapes of the support frame 4 and the beam 5. Form. The shape of the support frame 4 is preferably a shape that forms a mask outer peripheral portion without a break. The shape of the beam 5 is not particularly limited, but generally a lattice shape is convenient.

  Next, as shown in FIG. 3C, the silicon substrate 1 is etched by a Bosch process using the resist pattern 21 as a mask to form the support frame 4 and the beam 5. Etching is performed until the silicon oxide layer 2 is exposed, and the silicon oxide layer 2 is used as an etching stopper layer. After the etching is completed, the resist pattern 21 is removed. The Bosch process is an etching method in which deposition (deposition) conditions and etching conditions are repeated alternately.

  Next, as shown in FIG. 3D, the silicon oxide layer 2 is removed by etching using the support frame 4 and the beam 5 as a mask. This etching step is, for example, wet etching using hydrofluoric acid. Thus, a membrane 6 (silicon thin film) supported by the support frame 4 and the beam 5 is formed. The membrane 6 includes a support portion 8 in contact with the support frame 4 and the beam 5 and a pattern forming portion 7 surrounded by the support portion 8. This completes the processing of the back surface.

  Next, as shown in FIG. 3E, a positive resist having a thickness of 50 μm is applied to the surface of the single crystal silicon film 3, and then exposed and developed to form a resist pattern 22. The resist pattern 22 has recesses 23 for forming the conductive protrusions 11 shown in FIGS. 1A and 1B at the positions of the four corners of the exposure mask. The recess 23 has a trapezoidal cross section in the vertical direction, and the upward opening has a square shape with a side of 50 μm. Such a divergent recess can be produced by using polymethyl methacrylate as a resist and using a mixed solution of methyl isobutyl ketone and isopropyl alcohol as a developer.

  Next, as shown in FIG. 4F, a metal such as tungsten or aluminum is deposited from above the resist pattern 22 to form the conductive protrusions 11 in the recesses 23. Thereafter, as shown in FIG. 4G, a lift-off process is performed, and the resist pattern 22 is removed together with the metal layer 24 adhering to the upper portion. The height (layer thickness) of the conductive protrusions 11 is the same as the distance between the exposure mask 100 and the exposure target during exposure. For example, when the electron beam resist layer located 30 μm away is exposed using the exposure mask 100, the thickness of the conductive protrusion 11 is set to 30 μm.

  Next, as shown in FIG. 4 (h), a resist film is applied again on the surface of the membrane region 6 of the single crystal silicon film 3, and exposed and developed to form an electron beam passage hole 9 corresponding to the exposure pattern. A resist pattern 25 is formed. Patterning of the resist film can be performed by ordinary electron beam lithography.

  Next, as shown in FIG. 4I, the membrane region 6 of the single crystal silicon film 3 is etched using the resist pattern 25 as a mask to form an electron beam passage hole 9.

  Next, as shown in FIG. 4J, the resist pattern 25 is removed, and the exposure mask 100 is completed.

Production of exposure mask (2)
In this embodiment, an example in which the protrusion 11b is formed by etching and the exposure mask 101 is manufactured will be described. FIG. 5 is a flowchart showing a process for producing an exposure mask, and FIGS. 6 and 7 are schematic sectional views showing the process. Hereinafter, in order to avoid duplication, an explanation will be given with an emphasis on the difference from the production of the exposure mask (1).

  FIG. 6A is a cross-sectional view showing an SOI (Silicon On Insulator) wafer in which a silicon oxide layer 2 and a single crystal silicon film 3b are formed on a silicon substrate (wafer) 1 made of single crystal silicon. . Through the following steps, the single crystal silicon film 3b of the SOI wafer is processed into the membrane 6 and the protrusion 11b, and the support frame 4 for maintaining the rigidity of the entire silicon substrate 1 and the support frame 4 and the membrane 6 are integrated. It is processed into a supporting beam 5.

  The thickness of the single crystal silicon film 3b is obtained by adding the thickness of the membrane 6 to the distance between the exposure mask 101 and the exposure target (for example, an electron beam resist layer on a semiconductor wafer) at the time of exposure. For example, when the distance between the exposure mask 101 and the object to be exposed is 30 μm and the thickness of the membrane 6 is 0.5 μm, the thickness of the single crystal silicon film 3b is 30.5 μm.

  First, the back surface is processed in the same manner as in the production of the exposure mask (1), and the support frame 4 and the beam 5 are formed.

  That is, as shown in FIG. 6B, a resist film is applied to the back surface of the silicon substrate 1 and then exposed and developed to form a resist pattern 21 patterned corresponding to the shapes of the support frame 4 and the beam 5. Form. The shape of the support frame 4 is desirably a shape that forms an outer periphery of the mask without a break, and the shape of the beam 5 is preferably a lattice shape.

  Then, as shown in FIG. 6C, the silicon substrate 1 is etched by the Bosch process using the resist pattern 21 as a mask to form the support frame 4 and the beam 5. Etching is performed until the silicon oxide layer 2 is exposed, and the silicon oxide layer 2 is used as an etching stopper layer. After the etching is completed, the resist pattern 21 is removed.

  Further, as shown in FIG. 6D, the silicon oxide layer 2 is removed by wet etching using, for example, hydrofluoric acid using the support frame 4 and the beam 5 as a mask. Thus, a structure in which the single crystal silicon film 3b is supported by the support frame 4 and the beam 5 is formed.

  Next, the single crystal silicon film 3 b is processed into the protrusion 11 b and the membrane 6.

  First, as shown in FIG. 6E, a negative resist is applied to the surface of the single crystal silicon film 3b, and then exposed and developed to form resist patterns 26 at the four corner positions of the exposure mask. The cross section in the horizontal direction of the resist pattern 26 is a square having a side of 50 μm.

  Subsequently, as shown in FIG. 7F, the single crystal silicon film 3b is etched by 30 μm using the resist pattern 26 as a mask to form a protrusion 11b having a height of 30 μm, and the main part of the single crystal silicon film 3b is formed. It is processed into a membrane 6 having a thickness of 0.5 μm. This etching step is performed by, for example, wet etching using a 50% by mass potassium hydroxide (KOH) aqueous solution or a tetramethylammonium hydroxide (TMAH) aqueous solution at a temperature of 70 ° C. After the etching is completed, the resist pattern 26 is removed as shown in FIG.

  After the projections 11b and the membrane 6 are formed as described above, the membrane 6 is processed in the same manner as in the exposure mask fabrication (1) to complete the exposure mask 101.

  That is, as shown in FIG. 7 (h), a resist pattern 25 is formed by electron beam lithography on the surface of the membrane region 6 of the single crystal silicon film 3b. Next, as shown in FIG. 7 (i), the resist pattern The membrane region 6 is etched using 25 as a mask to form the electron beam passage hole 9, and then the resist pattern 25 is removed as shown in FIG. 7 (j).

Exposure method Next, an exposure apparatus and an exposure method for performing exposure will be described with reference to the exposure mask 100.

  FIG. 8 is an explanatory diagram of the electron beam exposure apparatus 30 and an exposure method using the same. The electron beam exposure apparatus 30 includes an electron gun 31 that generates an electron beam 32 as an exposure beam. On the flight path of the electron beam 32 emitted from the electron gun 31, the electron beam 32 is sequentially formed from the electron gun 31 side. The condenser lens 33 that aligns the traveling directions in parallel, the aperture 34 that restricts the electron beam 32, and the electron beam 32 are scanned in the raster scan mode or the vector scan mode. Even at that time, the electron beam 32 remains parallel to each other. A main polarizer 35, a sub-deflector 36, and the like that control the electron beam 32 so as to be perpendicularly incident on are arranged.

  In the electron beam exposure apparatus 30 used in LEEPL, the incident angle of the electron beam incident on the exposure mask 100 is slightly changed from the vertical direction by adjusting the sub deflector 36 as shown by the dotted line in FIG. The sub-deflector 36 can be controlled to correct a slight misalignment or line width.

  In the electron beam exposure apparatus of FIG. 8, the exposure mask 100 is held at a predetermined position by a mask holder (not shown). On the other hand, the semiconductor wafer 40 to be exposed is held at a predetermined position by the wafer stage 50 with an insulating layer 41 such as a silicon oxide layer and an electron beam resist layer 42 formed on the surface. The relative position of the semiconductor wafer 40 with respect to the exposure mask 100 can be moved in the horizontal direction (xy direction) and the vertical direction (z direction) by adjusting the wafer stage 50. During exposure, the membrane of the exposure mask 100 6 and the electron beam resist layer 42 on the semiconductor wafer 40 can be set to a predetermined value (10 μm or more, usually 30 to 50 μm).

  The relative position data of the semiconductor wafer 40 with respect to the exposure mask 100 can be acquired in real time by taking a microscope image with a CCD by the SLA alignment mechanism 37 described above and performing image processing such as pattern recognition. In addition to being used for alignment of the semiconductor wafer 40 before exposure, the data is irradiated with the electron beam 32 while controlling the sub-deflector 36 of the electron beam exposure apparatus 30 to correct the positional deviation during exposure. It is used to control the position and rotation components of the wafer stage 50 and the mask holder in real time to suppress the influence of vibration and the like during exposure.

  At the time of exposure, the electron beam 32 emitted from the electron gun 31 is shaped by the condenser lens 33 and the aperture 34, and the irradiation position of the electron beam 32 is controlled by the main polarizer 35 and the sub-polarizer 36. Scan the top in raster scan mode or vector scan mode. The electron beam resist 42 that has been irradiated with electrons that have passed through the electron beam passage hole 9 of the exposure mask 100 is exposed to light, so that the mask pattern of the exposure mask 100 is transferred to the electron beam resist 42 at the same magnification. .

  FIG. 9 is a flowchart of the exposure method based on the present embodiment, and FIG. 10 is a schematic sectional view thereof.

  When performing exposure using the electron beam exposure apparatus 30 shown in FIG. 8, first, the exposure mask 100 is held by a mask holder (not shown), and an insulating layer 41 such as a silicon oxide layer and an electron beam resist are formed on the surface. By holding the semiconductor wafer 40 on which the layer 42 is formed by the wafer stage 50, the exposure mask 100 and the semiconductor wafer 40 are placed on the exposure apparatus 30 at respective predetermined positions.

  Next, the semiconductor wafer 40 is moved in the horizontal direction by the operation of the wafer stage 50 and moved to the first exposure region, and then the exposure mask 100 and the semiconductor wafer 40 are aligned by the SLA alignment mechanism 37 (FIG. 10 (a)).

  Next, the wafer stage 50 is driven by a piezo element to move upward, and the surface of the semiconductor wafer 40, specifically the surface of the electron beam resist layer 42, is exposed on the conductive protrusion 11 protruding below the exposure mask 100. Contact is made (FIG. 10B).

  Next, the amount of misalignment between the exposure mask 100 and the semiconductor wafer 40 is measured again by the SLA alignment mechanism, and the electron beam is scanned while correcting the misalignment using the sub deflector 36 of the electron beam exposure apparatus 30. Then, the semiconductor wafer 40 is exposed to transfer the pattern (FIG. 10C).

  In this case, the exposure mask 100 and the electron beam resist layer 42 are electrically connected by contact of the conductive protrusions 11, and both are kept at the same potential, and the static electricity on the electron beam resist layer 42 is exposed. Since it is released to the ground through the mask 100 and the mask holder, there is no fear that the exposure mask 100 is damaged by the electrostatic force caused by the charging of the electron beam resist layer 42.

  Further, since the conductive protrusion 11 of the exposure mask 100 and the semiconductor wafer 40 are in contact with each other at four points and are fixed to each other and integrated, the influence of vibration, particularly high frequency vibration is suppressed, and the position of the exposure pattern is reduced. Accuracy and resolution are not degraded.

  At this time, since the stress applied to the exposure mask 100 or the semiconductor wafer 40 by the contact is slight, there is no fear that the exposure mask 100 or the semiconductor wafer 40 is distorted due to this, or a contaminant is generated. .

  After the transfer is completed, the wafer stage 50 is lowered and a sufficient distance is provided between the exposure mask 100 and the semiconductor wafer 40 (FIG. 10D). In this state, the semiconductor wafer 40 is moved in the horizontal direction by operating the wafer stage 50 and moved to the next exposure region (FIG. 10E).

  Thereafter, the semiconductor wafer 40 is repeatedly exposed and moved by the operations of FIGS. 10A to 10E to form a predetermined exposure pattern on the semiconductor wafer 40.

  Although not shown, in the method of manufacturing a semiconductor device, the step of developing the electron beam resist layer 42 and the resist pattern formed by the development are used to form the silicon oxide layer 41 and the silicon layer 40 thereunder. Etch into a predetermined pattern.

  FIG. 11 is an explanatory diagram showing a path for removing charges (electrons in this case) charged in the electron beam resist layer 42. 11A is a top view showing a state in which the exposure mask 100 is held by the mask holder 20 by means such as an electrostatic chuck, and FIG. 11B is the same as FIG. 10C. The mask holder 20 is added, and FIG. 11C is an enlarged schematic cross-sectional view of a part thereof.

  Electrons are emitted to the ground through the grounded mask holder 20. That is, as shown in FIG. 11C, the electrons charged in the electron beam resist layer 42 and the insulating layer 41 are taken out to the exposure mask 100 through the conductive protrusions 11 and tunnel through the thin silicon oxide layer 2. After passing through by the effect, it is escaped to the ground through the support frame 4 and the mask holder 20. For this reason, even when the semiconductor wafer 40 having the insulating layer 41 is exposed, a potential difference does not occur between the electron beam resist layer 42 and the exposure mask 100, and the trouble of membrane breakage does not occur.

  FIG. 12A is a top view of another example 110 of an exposure mask (stencil mask) based on the present embodiment. The exposure mask 110 is configured in substantially the same way as the exposure mask 100, except that a rectangular frame-shaped conductor 11c is provided on the back surface instead of the conductive protrusion 11, and an electron beam resist layer is provided. In order to prevent the charging of 42, it may be effective to provide a conductor in a strip shape as in this example. As described above, the shape and arrangement of the conductors or protrusions can be appropriately selected depending on the purpose and the shape of the mask pattern.

  As described above, since it cannot be said that there is no damage or contamination due to contact with the conductor or protrusion, in order to suppress the influence as much as possible and improve the device performance, production yield, etc., the conductor or It is desirable to arrange the contact area where the protrusions contact the semiconductor wafer and the vicinity thereof in areas other than the circuit pattern area, or in the circuit pattern area that does not hinder device operation even if foreign matter occurs. For example, the contact area may be arranged in a scribe line area used for separating a semiconductor device from a semiconductor wafer.

  When the purpose is to prevent the electron beam resist layer from being charged, it is preferable to distribute the conductor pattern over a relatively wide area. On the other hand, when the purpose is to reduce vibration, it is sufficient to provide protrusions at 3 to 6 points at even intervals on the outer peripheral portion as much as possible.

  FIG. 12B is a cross-sectional view showing an example of the shape of the vertical cross section of the conductor or protrusion. Various shapes of the vertical cross section are conceivable depending on the purpose and manufacturing method. For example, when formed by vapor deposition or the like, it tends to be rounded at the tip as shown in FIG. 12 (b-1) or (b-2), and when formed by etching or the like, the tip Tends to be flat.

  The width of the cross section of the conductor or protrusion is preferably 30 μm to 100 μm, more preferably about 50 μm. If the cross-sectional width is less than 30 μm, sufficient strength cannot be ensured. On the other hand, if it exceeds 100 μm, there is a disadvantage that the contact area protrudes from the scribe line area.

  FIG. 13 is an example of setting a desirable contact area. FIG. 13A shows a case where the chips 61 formed on the semiconductor wafer are not separated into pieces, but a plurality (six in the figure) are cut together as a module 62. . In such a case, the contact area 60 is provided on the outer scribe line (scribe line between modules) 63, and the alignment mark 65 conventionally provided on the outer scribe line 63 is provided on the inner scribe line (scribe lines other than the scribe line between modules). Line) 64 is preferable.

FIG. 13B shows an example 120 of a complementary exposure mask in which one mask is divided into four quadrants to form four complementary masks (see Japanese Patent Application Laid-Open No. 2003-59819). The configurations of the support frame 4, the beam 5, the membrane 6, the pattern forming unit 7, the support unit 8, and the like are the same as those of the exposure mask 101 described above. In this case, the contact area 60 may be anywhere on the support portion 8 which is the membrane 6 positioned below the beam 5.

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  For example, in the above description of the exposure method, an example in which a low-energy electron beam is used as an exposure beam has been described. However, the exposure method of the present invention is in a state in which an exposure mask having a membrane is brought close to the exposure surface. The present invention is widely applicable to exposure methods that perform exposure, and the exposure beam may be a charged particle beam such as an ion beam.

  The present invention relates to a microfabrication technique for drawing a fine circuit pattern, which cannot be formed by photolithography using ultraviolet light, on a semiconductor wafer or the like with a charged particle beam such as an electron beam or an ion beam. It is most effective when applied to a projection exposure technique that irradiates an exposure mask having an electron beam, an ion beam, or the like and transfers a circuit pattern onto a wafer at a time.

They are sectional drawing (a) which shows the example of the mask for exposure based on preferable embodiment of this invention, top view (b), and top view (c) of the exposure mask of a modification. It is a flowchart which shows the process of producing the mask for exposure same as the above. It is a schematic sectional drawing which shows the process of producing an exposure mask same as the above. It is a schematic sectional drawing which shows the process of producing an exposure mask same as the above. It is a flowchart which shows the process of producing another exposure mask same as the above. It is a schematic sectional drawing which shows the process of producing the other exposure mask same as the above. It is a schematic sectional drawing which shows the process of producing the other exposure mask same as the above. It is explanatory drawing of an electron beam exposure apparatus and the exposure method using the same. It is a flowchart which shows an exposure method similarly. It is a schematic sectional drawing which shows the exposure method equally. It is explanatory drawing which shows the path | route which removes the electric charge (in this case electron) charged to the electron beam resist layer. The top view (a) of the other example of the mask for exposure (stencil mask) and sectional drawing (b) which shows the example of the shape of the perpendicular | vertical cross section of a conductor or a protrusion. This is an example of setting a desirable contact area. It is a schematic sectional drawing which shows the state of the vicinity of the mask for exposure when performing exposure by LEEPL using the conventional mask for exposure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (wafer), 2 ... Silicon oxide layer, 3, 3b ... Single crystal silicon film,
4 ... support frame, 5 ... beam, 6 ... membrane, 7 ... pattern forming part, 8 ... support part,
9 ... Electron beam passage hole, 11 ... Conductive projection, 11b ... Projection,
21, 22, 25, 26 ... resist pattern, 23 ... concave, 24 ... metal layer,
30 ... Electron beam exposure apparatus, 31 ... Electron gun, 32 ... Electron beam,
33 ... Condenser lens, 34 ... Aperture, 35 ... Main polarizer, 36 ... Sub deflector,
37 ... SLA alignment mechanism, 40 ... Semiconductor wafer, 41 ... Insulating layer,
42 ... Electron beam resist layer, 50 ... Wafer stage, 60 ... Contact area, 61 ... Chip,
62 ... Module, 63 ... Outside scribe line (scribe line between modules),
64 ... inner scribe line (scribe line other than outer scribe line),
65 ... alignment mark,
100, 101, 110 ... exposure mask (stencil mask),
120: Complementary exposure mask (stencil mask),
200 ... Conventional exposure mask (stencil mask)

Claims (19)

  An exposure beam passage hole penetrating from one surface side to the other surface side is formed in a predetermined pattern, and is used for exposure of the predetermined pattern on an exposure target by the exposure beam passing through the exposure beam passage hole. A mask for exposure, comprising a conductor having a height in contact with the exposure target on a surface facing the exposure target during exposure.   The exposure mask according to claim 1, wherein the conductor is made of at least one conductive protrusion.   The exposure mask according to claim 1, wherein the exposure beam is a charged particle beam.   2. The device according to claim 1, wherein a portion where the conductor is in contact with the object to be exposed and the vicinity thereof are arranged outside the circuit pattern region, or arranged in a circuit pattern region which does not hinder device operation even if foreign matter is generated. Mask for exposure.   The exposure mask according to claim 1, wherein the exposure target is a semiconductor wafer having a resist layer provided on a surface thereof.   An exposure beam passage hole penetrating from one surface side to the other surface side is formed in a predetermined pattern, and is used for exposure of the predetermined pattern on an exposure target by the exposure beam passing through the exposure beam passage hole. An exposure mask having a protrusion having a height in contact with the exposure target on a surface facing the exposure target during exposure.   The exposure mask according to claim 6, wherein the protrusion is composed of at least three insulating or conductive protrusions.   The exposure mask according to claim 6, wherein the exposure beam is a charged particle beam.   The portion where the projection contacts the exposure target and the vicinity thereof are arranged outside the circuit pattern region, or arranged in a circuit pattern region which does not hinder device operation even if foreign matter is generated. Mask for exposure.   The exposure mask according to claim 6, wherein the exposure target is a semiconductor wafer having a resist layer provided on a surface thereof.   It is the manufacturing method of the mask for exposure described in any one of Claims 1-10, Comprising: Conductor material or protrusion material is adhered to the surface facing the said exposure object using a mask, The said A method for manufacturing an exposure mask, comprising a step of forming a conductor or the protrusion in a predetermined pattern.   It is a manufacturing method of the mask for exposure described in any one of Claims 1-10, Comprising: It is for exposure which has the process of patterning the surface facing the said exposure object, and forming the said conductor or the said protrusion. Mask manufacturing method.   When exposing the exposure object to a predetermined pattern using the exposure mask according to claim 1, the mask pattern portion of the exposure mask and the exposure object are held at a predetermined interval. An exposure method for performing the exposure while bringing the conductor or the protrusion into contact with the object to be exposed.   After the exposure in one exposure region is completed, the conductor or the protrusion and the exposure target are separated, and in this state, the relative position of the exposure target with respect to the exposure mask is moved to the next exposure region. A predetermined exposure is performed on the exposure target by performing the step and the step of bringing the conductor or the protrusion again into contact with the exposure target at the moving position and performing the exposure on the exposure target. The exposure method according to claim 13, wherein a pattern is formed.   The exposure method according to claim 13, wherein the exposure is performed by arranging the conductor or the protrusion in a non-exposed region.   When the resist layer on the semiconductor wafer is exposed to a predetermined pattern using the exposure mask according to claim 1, the mask pattern portion of the exposure mask and the resist layer are spaced at a predetermined interval. A method for manufacturing a semiconductor device, comprising: performing the exposure while holding the conductor or the protrusion in contact with the resist layer, and developing the resist after the exposure.   The method for manufacturing a semiconductor device according to claim 16, wherein a lower layer of the resist pattern formed by the development is etched into a predetermined pattern.   The method of manufacturing a semiconductor device according to claim 16, wherein the exposure is performed by arranging the conductor or the protrusion in a non-exposed region. The method of manufacturing a semiconductor device according to claim 18, wherein the non-exposure region is on a scribe line of the semiconductor device.