JP2005033945A - Power conversion device - Google Patents

Power conversion device Download PDF

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JP2005033945A
JP2005033945A JP2003272135A JP2003272135A JP2005033945A JP 2005033945 A JP2005033945 A JP 2005033945A JP 2003272135 A JP2003272135 A JP 2003272135A JP 2003272135 A JP2003272135 A JP 2003272135A JP 2005033945 A JP2005033945 A JP 2005033945A
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converter
parallel converter
series
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parallel
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JP4251030B2 (en
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Isao Amano
功 天野
Yasuhiro Okuma
康浩 大熊
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Fuji Electric FA Components and Systems Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To improve conversion efficiency by reducing the number of times of switching of a parallel converter and suppressing switching loss and conduction loss. <P>SOLUTION: This power conversion device is of a series-parallel type and comprises a series converter 7 and the parallel converter. In the power conversion device, the variation of a voltage of an AC power supply 1 is compensated by the switching operation of the series converter 7, to keep a voltage fed to a load 10 constant, the variation of a voltage of a capacitor 6 caused by the compensation operation of the series converter 7 is compensated by a charging/discharging operation between the AC power supply 1 and the parallel converter 5. A waveform command of an input current of the parallel converter 5 that is generated for PWM-controlling the parallel converter 5 is made to be an intermittent waveform command such that the parallel converter is not switched during a part of one cycle of the waveform command. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、交流電源に対して直列に接続された直列コンバータと並列に接続された並列コンバータとを備えた直並列形の電力変換装置に関し、詳しくは、交流電源電圧の変動分を直列コンバータが補償して負荷に一定の電圧を供給すると共に、直列コンバータによる補償に必要なエネルギーのみを並列コンバータが補償するようにした電力変換装置に関するものである。   The present invention relates to a series-parallel power converter including a series converter connected in series to an AC power supply and a parallel converter connected in parallel. The present invention relates to a power converter that compensates for supplying a constant voltage to a load and that a parallel converter compensates only for energy required for compensation by a series converter.

図７は、この種の電力変換装置の従来技術を示す回路図であり、例えば、後述する非特許文献１に記載されたものとほぼ同様の回路である。
図７において、１は交流電源、２，９はフィルタコンデンサ、３，８はリアクトル、４は電流検出器、５は並列コンバータ、６は直流リンク部に設けられたコンバータ電源としての電解コンデンサ、７は直列コンバータ、１０は負荷を示す。 FIG. 7 is a circuit diagram showing a conventional technique of this type of power conversion device, which is, for example, a circuit substantially similar to that described in Non-Patent Document 1 described later.
In FIG. 7, 1 is an AC power source, 2 and 9 are filter capacitors, 3 and 8 are reactors, 4 is a current detector, 5 is a parallel converter, 6 is an electrolytic capacitor as a converter power source provided in the DC link unit, 7 Indicates a series converter and 10 indicates a load.

ここで、並列コンバータ５及び直列コンバータ７は、例えば図８に示すように、還流ダイオードを逆並列接続してなるＩＧＢＴ等の半導体スイッチング素子５１〜５４，７１〜７４をそれぞれ単相ブリッジ接続して構成されている。また、並列コンバータ５の交流入力側または直列コンバータ７の出力側には、必要に応じて絶縁トランス（図示せず）が接続される。
なお、並列コンバータ５の一方の上下アーム、または直列コンバータ７の一方の上下アーム、例えばスイッチング素子７１，７２の直列回路をコンデンサの直列回路に置き換えることにより、直列コンバータをハーフブリッジとして構成しても良い。 Here, as shown in FIG. 8, for example, the parallel converter 5 and the series converter 7 are formed by connecting semiconductor switching elements 51 to 54 and 71 to 74 such as IGBTs having anti-reflective diodes connected in antiparallel to each other by a single-phase bridge connection. It is configured. An insulation transformer (not shown) is connected to the AC input side of the parallel converter 5 or the output side of the series converter 7 as necessary.
The series converter may be configured as a half bridge by replacing one upper and lower arms of the parallel converter 5 or one upper and lower arms of the series converter 7, for example, a series circuit of the switching elements 71 and 72 with a series circuit of capacitors. good.

図７の構成において、負荷１０には交流電源１の電圧と直列コンバータ７の出力電圧とが加算された電圧が印加されるため、直列コンバータ７は直列補償電圧源として動作する。例えば、交流電源１の電圧が変動して低下したとしても、交流電源電圧に直列コンバータ７の出力電圧を加算することで負荷１０へ供給する交流電圧を一定にすることができる。このため、図示されていないが、負荷１０の両端電圧を検出し、指令値との偏差がゼロになるように直列コンバータ７内のスイッチング素子のオン、オフが制御される。   In the configuration of FIG. 7, since the voltage obtained by adding the voltage of the AC power supply 1 and the output voltage of the series converter 7 is applied to the load 10, the series converter 7 operates as a series compensation voltage source. For example, even if the voltage of the AC power supply 1 fluctuates and decreases, the AC voltage supplied to the load 10 can be made constant by adding the output voltage of the series converter 7 to the AC power supply voltage. For this reason, although not shown, the voltage across the load 10 is detected, and the switching elements in the series converter 7 are controlled to be turned on and off so that the deviation from the command value becomes zero.

一方、並列コンバータ５は、直列コンバータ７のスイッチング動作に伴う直流リンク部（電解コンデンサ６）の電圧の変動を補償して一定に維持するために並列補償電流源として動作し、交流電源１との間で充放電動作を行う。その結果、負荷１０に供給されるエネルギーは直列コンバータ７だけを通り、並列コンバータ５には直列コンバータ７による電圧補償に使ったエネルギーだけが通過するので、並列コンバータ５における損失を低減して高効率化を図ることが可能になっている。   On the other hand, the parallel converter 5 operates as a parallel compensation current source in order to compensate and keep constant the voltage fluctuation of the DC link part (electrolytic capacitor 6) accompanying the switching operation of the series converter 7. Charge / discharge operation is performed between. As a result, the energy supplied to the load 10 passes only through the series converter 7, and only the energy used for voltage compensation by the series converter 7 passes through the parallel converter 5. Therefore, the loss in the parallel converter 5 is reduced and high efficiency is achieved. Can be realized.

次に、並列コンバータ５の動作を、図７における制御回路の構成と共に以下に述べる。
直流リンク部の電圧基準値Ｖｄｃｒｅｆと電圧検出値Ｖｄｃとの偏差を加算器１５により求め、その偏差を第１の調節手段としてのＰＩ調節器１６を介して乗算器１７に入力する。一方、電源電圧Ｖｉｎと基準正弦波Sin-refとをＰＬＬ回路１１により同期させて正弦波指令Sin-wtを得る。この正弦波指令Sin-wtを乗算器１７に入力して前記ＰＩ調節器１６の出力信号と乗算し、並列コンバータ５の入力電流の振幅指令ASin-wtを得る。この振幅指令ASin-wtを、前記電流検出器４により検出した入力電流Ｉｐｃと共に加算器１２に入力し、両者の偏差がゼロになるように第２の調節手段としてのＰＩ調節器１３及びＰＷＭ回路１４を介してＰＷＭパターンを生成し、このＰＷＭパターンに従ったゲートパルスを並列コンバータ５のスイッチング素子に与えてオン、オフ制御する。
これにより、直流リンク部の電圧を電圧基準値Ｖｄｃｒｅｆに維持しながら、並列コンバータ５の入力電流波形を正弦波状に制御することが可能である。 Next, the operation of the parallel converter 5 will be described below together with the configuration of the control circuit in FIG.
A deviation between the voltage reference value V dcref of the DC link unit and the voltage detection value V dc is obtained by the adder 15, and the deviation is input to the multiplier 17 via the PI regulator 16 as the first adjusting means. On the other hand, to obtain a sine wave command Sin-wt and a power supply voltage V in and the reference sine wave Sin-ref is synchronized by the PLL circuit 11. The sine wave command Sin-wt is input to the multiplier 17 and multiplied by the output signal of the PI regulator 16 to obtain an amplitude command ASin-wt of the input current of the parallel converter 5. This amplitude command ASin-wt is input to the adder 12 together with the input current I pc detected by the current detector 4, and the PI adjuster 13 and the PWM as the second adjusting means so that the deviation between them becomes zero. A PWM pattern is generated via the circuit 14, and a gate pulse according to this PWM pattern is applied to the switching element of the parallel converter 5 for on / off control.
Thereby, it is possible to control the input current waveform of the parallel converter 5 in a sine wave shape while maintaining the voltage of the DC link unit at the voltage reference value V dcref .

中井靖博、外２名，「直並列アクティブフィルタを用いた可変交流電子変圧器」，平成７年電気学会産業応用部門全国大会論文集，ｐ．２２７−２３０（Fig.3）Yasuhiro Nakai and two others, “Variable AC Electronic Transformer Using Series-Parallel Active Filters”, Proceedings of National Conference of Industrial Applications Division, IEEJ, p. 227-230 (Fig.3)

上述した従来技術において、並列コンバータ５は、その入力電流を振幅指令ASin-wtに追従させるために、電源電圧周期（商用周期）の全期間にわたってスイッチングを行っている。このため、並列コンバータ５が直列コンバータ７に対して補償するべきエネルギーが少ないにも関わらず、並列コンバータ５は正弦波電流を流すべく動作するためにスイッチング回数が増加し、スイッチング損失や素子の導通損失が増加してしまうという問題があった。   In the conventional technology described above, the parallel converter 5 performs switching over the entire period of the power supply voltage cycle (commercial cycle) in order to make the input current follow the amplitude command ASin-wt. For this reason, although the parallel converter 5 has less energy to be compensated for the series converter 7, the parallel converter 5 operates to pass a sine wave current, so that the number of times of switching increases, switching loss and element conduction. There was a problem that the loss increased.

そこで本発明は、並列コンバータのスイッチング回数を減少させ、スイッチング損失等を低減して変換効率を向上させた電力変換装置を提供しようとするものである。   Therefore, the present invention seeks to provide a power conversion device that improves the conversion efficiency by reducing the switching frequency of the parallel converter and reducing the switching loss and the like.

上記課題を解決するため、請求項１に記載した発明は、交流電源と負荷との間に直列接続され、かつコンバータ電源としてコンデンサを備えた直列コンバータと、前記交流電源に対して並列に接続された並列コンバータとが、前記コンデンサを有する直流リンク部を介して接続された電力変換装置であって、交流電源の電圧変動分を前記直列コンバータのスイッチング動作により補償して負荷への供給電圧を一定に保ち、前記直列コンバータの補償動作による前記コンデンサの電圧変動分を、前記並列コンバータによる交流電源との間の充放電動作により補償する電力変換装置において、
前記並列コンバータをＰＷＭ制御するために生成される前記並列コンバータの入力電流の波形指令を、その一周期のうち一部の期間は前記並列コンバータをスイッチングさせないような間欠的な波形指令とするものである。 In order to solve the above problems, the invention described in claim 1 is a series converter connected in series between an AC power source and a load and provided with a capacitor as a converter power source, and connected in parallel to the AC power source. The parallel converter is a power conversion device connected via a DC link unit having the capacitor, and the supply voltage to the load is kept constant by compensating the voltage fluctuation of the AC power supply by the switching operation of the series converter. In the power converter for compensating for the voltage fluctuation of the capacitor due to the compensation operation of the series converter by the charge / discharge operation between the parallel converter and the AC power source,
The waveform command of the input current of the parallel converter generated for PWM control of the parallel converter is an intermittent waveform command that does not switch the parallel converter during a part of one period. is there.

請求項２に記載した発明は、請求項１記載の電力変換装置において、
交流電源電圧に同期した基準波形指令を生成する手段と、直流リンク部の電圧検出値が電圧基準値に一致するように調節動作する第１の調節手段と、この手段の出力信号と前記基準波形指令とを乗算して並列コンバータの入力電流の振幅指令を生成する手段と、並列コンバータの入力電流の振幅が前記入力電流の振幅指令に追従するように調節動作する第２の調節手段と、第２の調節手段の出力信号から並列コンバータに対するＰＷＭ信号を生成する手段と、を備えたものである。 The invention described in claim 2 is the power conversion device according to claim 1,
Means for generating a reference waveform command synchronized with the AC power supply voltage, first adjusting means for adjusting the voltage detection value of the DC link unit to match the voltage reference value, the output signal of this means and the reference waveform Means for multiplying the command to generate an amplitude command of the input current of the parallel converter, second adjusting means for adjusting the amplitude of the input current of the parallel converter to follow the amplitude command of the input current, And a means for generating a PWM signal for the parallel converter from the output signal of the second adjusting means.

本発明によれば、いわゆる直並列形の電力変換装置において、並列コンバータに対する波形指令を間欠的にしてスイッチング期間を短くするものである。これにより、並列コンバータのスイッチング回数を減少させてスイッチング損失や素子の導通損失を低減することができ、装置の変換効率の向上やランニングコストの抑制が可能である。   According to the present invention, in the so-called series-parallel power converter, the waveform command for the parallel converter is intermittently made to shorten the switching period. Thereby, the switching frequency of a parallel converter can be reduced, switching loss and element conduction loss can be reduced, and conversion efficiency of the apparatus can be improved and running cost can be suppressed.

以下、図に沿って本発明の実施形態を説明する。
まず、図１は本発明の実施形態を示す回路図であり、図７と同一の構成要素には同一の参照符号を付して説明を省略し、以下では異なる部分を中心に説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 1 is a circuit diagram showing an embodiment of the present invention. The same components as those of FIG. 7 are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different parts will be mainly described.

図１の実施形態が図７と異なる部分は、以下の通りである。すなわち、図１では、電源電圧Ｖｉｎと基準波形Wave-refとをＰＬＬ回路１１により同期させて基準波形指令Wave-wtを得ており、この基準波形指令Wave-wtとＰＩ調節器１６の出力信号とを乗算器１７により乗算して並列コンバータ５の入力電流の振幅指令AWave-wtを得るようにした。 1 differs from FIG. 7 in the following manner. That is, in FIG. 1, to obtain a reference waveform command Wave-wt and a power supply voltage V in and the reference waveform Wave-ref is synchronized by the PLL circuit 11, the output of the reference waveform command Wave-wt and PI controller 16 The signal is multiplied by the multiplier 17 to obtain the amplitude command AWave-wt of the input current of the parallel converter 5.

ここで、図２は基準波形Wave-refの一例を概念的に示したもので、図示するように位相３０度から１５０度までの区間、及び、２１０度から３３０度までの区間だけ連続して値を持つような波形が基準波形Wave-refとして設定される。このような基準波形Wave-refに基づく基準波形指令Wave-wtとＰＩ調節器１６の出力信号とを乗算器１７で乗算することにより、並列コンバータ５の入力電流の振幅指令として、前記基準波形Wave-refに同期した振幅指令AWave-wtが得られることになる。   Here, FIG. 2 conceptually shows an example of the reference waveform Wave-ref. As shown in the figure, only the section from 30 degrees to 150 degrees and the section from 210 degrees to 330 degrees are continuously displayed. A waveform having a value is set as the reference waveform Wave-ref. By multiplying the reference waveform command Wave-wt based on the reference waveform Wave-ref by the output signal of the PI regulator 16 by the multiplier 17, the reference waveform Wave is used as an amplitude command of the input current of the parallel converter 5. The amplitude command AWave-wt synchronized with -ref is obtained.

上記振幅指令AWave-wtと並列コンバータ５の入力電流Ｉｐｃとの偏差が加算器１２により求められ、この偏差がゼロになるようにＰＩ調節器１３及びＰＷＭ回路を介して並列コンバータ５のスイッチング素子に対するゲートパルスが生成される。
このため、並列コンバータ５の入力電流Ｉｐｃは上記振幅指令AWave-wtに追従するように制御されて一周期のうち２／３の期間しか電流が流れなくなるので、この電流を流すための平均的なスイッチング回数も一周期全期間にわたり電流を流す場合に比べて２／３となる。従って、並列コンバータ５のスイッチング損失及び素子の導通損失を低減して変換効率を高めることができる。 A deviation between the amplitude command AWave-wt and the input current I pc of the parallel converter 5 is obtained by the adder 12, and the switching element of the parallel converter 5 is connected via the PI controller 13 and the PWM circuit so that the deviation becomes zero. A gate pulse for is generated.
For this reason, the input current I pc of the parallel converter 5 is controlled so as to follow the amplitude command AWave-wt, and the current only flows for a period of 2/3 of one cycle. The number of times of switching is 2/3 as compared with the case where a current is passed over the entire period of one cycle. Therefore, it is possible to reduce the switching loss of the parallel converter 5 and the conduction loss of the element and increase the conversion efficiency.

なお、直列コンバータ７側の制御としては、従来技術と同様に、負荷１０の両端電圧を検出して電圧指令値との偏差がゼロになるように直列コンバータ７内のスイッチング素子をオン、オフすることにより行われる。   As for the control on the side of the series converter 7, as in the conventional technique, the voltage across the load 10 is detected and the switching element in the series converter 7 is turned on and off so that the deviation from the voltage command value becomes zero. Is done.

なお、この実施形態では、振幅指令が正弦波である場合に比べて交流入力電流の波形が歪むため高調波成分の増加が予想されるが、本発明を比較的小容量（例えば１ＫＶＡ程度）の電力変換装置に適用する場合には、いわゆる高調波ガイドラインの適用対象にならず問題はない。   In this embodiment, the harmonic input component is expected to increase because the waveform of the AC input current is distorted as compared with the case where the amplitude command is a sine wave. However, the present invention has a relatively small capacity (for example, about 1 KVA). When applied to a power converter, the so-called harmonic guideline is not applicable and there is no problem.

また、前述したように、並列コンバータ５には直列コンバータ７による電圧補償に使ったエネルギー相当の電流しか流れず、その値は比較的小さいため、交流入力電流の波形歪みも僅かであって系統に与える影響は小さいものである。
例えば、図３は交流電源１の電圧が２０％低下した時に直列コンバータ７によって平常時の交流電源電圧（１００％）を維持するように動作させた場合の説明図であり、この場合には、交流電源１から直列コンバータ７を介して平常時の電流（１００％）が供給され、直列コンバータ７による電圧補償分に相当する分の電流（例えば２５％）が並列コンバータ５のみに流れることになる（よって、交流入力電流は１２５％となる）。
これらの交流入力電流、並列コンバータ５の電流、交流出力電流（直列コンバータ７の出力電流）を略図的に示すと図４（ａ），（ｂ），（ｃ）のようになり、並列コンバータ５に流れる電流は僅かであるため、交流入力電流の歪みもさほど問題とはならない。 Further, as described above, only the current corresponding to the energy used for the voltage compensation by the series converter 7 flows through the parallel converter 5 and the value thereof is relatively small. The impact is small.
For example, FIG. 3 is an explanatory diagram of a case where the series converter 7 is operated so as to maintain a normal AC power supply voltage (100%) when the voltage of the AC power supply 1 is reduced by 20%. A normal current (100%) is supplied from the AC power supply 1 via the series converter 7, and a current corresponding to the voltage compensation by the series converter 7 (for example, 25%) flows only in the parallel converter 5. (Thus, the AC input current is 125%).
These AC input current, parallel converter 5 current, and AC output current (output current of the series converter 7) are schematically shown in FIGS. 4 (a), 4 (b), and 4 (c). Since the current flowing through the circuit is very small, the distortion of the AC input current is not a problem.

次に、図５は、前述した図２のような基準波形Wave-refを用いて並列コンバータ５の入力電流を制御した場合（ここでは、間欠運転時という）の電流波形を、半周期中の通流期間１８０度（すなわち連続通流時）、１５０度、１２０度、９０度、６０度のそれぞれの場合について示したものである。電流の平均値を一定とすると、通流期間が短くなるほど電流の波高値は大きくなる。
以下、上記のように通流期間を変化させた場合の並列コンバータ５におけるスイッチング損失について考察する。 Next, FIG. 5 shows a current waveform when the input current of the parallel converter 5 is controlled using the reference waveform Wave-ref as shown in FIG. This is shown for each of the flow periods of 180 degrees (that is, during continuous flow), 150 degrees, 120 degrees, 90 degrees, and 60 degrees. Assuming that the average value of the current is constant, the peak value of the current increases as the conduction period becomes shorter.
Hereinafter, the switching loss in the parallel converter 5 when the conduction period is changed as described above will be considered.

ここでは、下記の簡略的な計算式により図５の各電流波形におけるスイッチング損失を計算した。
ＰＬＯＳＳ＝（Ｅｄ×Ｉ）／６×Ｔ×ｆｃｒｒ
なお、ＰＬＯＳＳ：スイッチング損失
Ｅｄ：直流リンク部の電圧
Ｉ：各電流波形の波高値
Ｔ：通流期間
ｆｃｒｒ：電流の周波数 Here, the switching loss in each current waveform of FIG. 5 was calculated by the following simple calculation formula.
P LOSS = (E d × I) / 6 × T × f crr
P LOSS : Switching loss E d : DC link voltage I: Peak value of each current waveform T: Current period f crr : Current frequency

上記計算式により計算した値について、通流期間１８０度（連続通流時）のスイッチング損失を１として規格化した結果を図６に示す。
通流期間が短い場合には遮断電流が全体的に大きくなるため１回のスイッチング損失は増加するが、図６から明らかなように、通流期間を短くしてＰＷＭ制御によるスイッチング回数を減少させることにより、総和としては連続通流時に比べて１０〜２０パーセント程度、損失が減少することがわかる。この損失低減効果は、通流期間が短いほど顕著なものとなる。 FIG. 6 shows a result obtained by normalizing the value calculated by the above calculation formula with the switching loss of the conduction period of 180 degrees (during continuous conduction) as 1. FIG.
When the conduction period is short, the cutoff current increases as a whole, so that one switching loss increases. However, as is apparent from FIG. 6, the conduction period is shortened to reduce the number of times of switching by PWM control. As a result, it is understood that the loss is reduced by about 10 to 20 percent as compared with the continuous flow. This loss reduction effect becomes more remarkable as the flow period is shorter.

なお、基準波形Wave-refとしては、正負半周期のピーク部を中心とした可変調状態の波形としても同様の作用効果を得ることができる。   Note that the same effect can be obtained even when the reference waveform Wave-ref is a modulatable waveform centered on the peak portion of the positive and negative half cycles.

本発明の実施形態が適用される電力変換装置の回路図である。It is a circuit diagram of a power converter to which an embodiment of the present invention is applied. 実施形態における基準波形の概念図である。It is a conceptual diagram of the reference waveform in the embodiment. 実施形態の動作説明図である。It is operation | movement explanatory drawing of embodiment. 実施形態における各部の電流波形図である。It is a current waveform figure of each part in an embodiment. 実施形態における間欠運転時の並列コンバータの入力電流波形図である。It is an input current waveform figure of the parallel converter at the time of intermittent operation in an embodiment. 実施形態における間欠運転時のスイッチング損失低減効果の説明図である。It is explanatory drawing of the switching loss reduction effect at the time of the intermittent operation in embodiment. 従来技術を示す回路図である。It is a circuit diagram which shows a prior art. 図７の主要部を示す回路図である。It is a circuit diagram which shows the principal part of FIG.

符号の説明Explanation of symbols

１：交流電源
２，９：フィルタコンデンサ
３，８：リアクトル
４：電流検出器
５：並列コンバータ
５１〜５４：半導体スイッチング素子
６：電解コンデンサ
７：直列コンバータ
７１〜７４：半導体スイッチング素子
１０：負荷
１１：ＰＬＬ回路
１２，１５：加算器
１３，１６：ＰＩ調節器
１４：ＰＷＭ回路
１７：乗算器 1: AC power supply 2, 9: Filter capacitor 3, 8: Reactor 4: Current detector 5: Parallel converter 51-54: Semiconductor switching element 6: Electrolytic capacitor 7: Series converter 71-74: Semiconductor switching element 10: Load 11 : PLL circuit 12, 15: Adder 13, 16: PI controller 14: PWM circuit 17: Multiplier

Claims (2)

交流電源と負荷との間に直列接続され、かつコンバータ電源としてコンデンサを備えた直列コンバータと、前記交流電源に対して並列に接続された並列コンバータとが、前記コンデンサを有する直流リンク部を介して接続された電力変換装置であって、交流電源の電圧変動分を前記直列コンバータのスイッチング動作により補償して負荷への供給電圧を一定に保ち、前記直列コンバータの補償動作による前記コンデンサの電圧変動分を、前記並列コンバータによる交流電源との間の充放電動作により補償する電力変換装置において、
前記並列コンバータをＰＷＭ制御するために生成される前記並列コンバータの入力電流の波形指令を、その一周期のうち一部の期間は前記並列コンバータをスイッチングさせないような間欠的な波形指令とすることを特徴とする電力変換装置。 A series converter connected in series between an AC power source and a load and provided with a capacitor as a converter power source, and a parallel converter connected in parallel to the AC power source via a DC link unit having the capacitor A connected power converter, wherein the voltage fluctuation of the AC power supply is compensated by the switching operation of the series converter to keep the supply voltage to the load constant, and the voltage fluctuation of the capacitor due to the compensation operation of the series converter. In a power conversion device that compensates for charging / discharging operation with an AC power source by the parallel converter,
The waveform command of the input current of the parallel converter generated for PWM control of the parallel converter is an intermittent waveform command that does not switch the parallel converter during a part of one period. A power conversion device. 請求項１記載の電力変換装置において、
交流電源電圧に同期した基準波形指令を生成する手段と、
直流リンク部の電圧検出値が電圧基準値に一致するように調節動作する第１の調節手段と、
この手段の出力信号と前記基準波形指令とを乗算して並列コンバータの入力電流の振幅指令を生成する手段と、
並列コンバータの入力電流の振幅が前記入力電流の振幅指令に追従するように調節動作する第２の調節手段と、
第２の調節手段の出力信号から並列コンバータに対するＰＷＭ信号を生成する手段と、
を備えたことを特徴とする電力変換装置。 The power conversion device according to claim 1,
Means for generating a reference waveform command synchronized with the AC power supply voltage;
First adjusting means for adjusting the voltage detection value of the DC link unit to match the voltage reference value;
Means for multiplying the output signal of this means and the reference waveform command to generate an amplitude command of the input current of the parallel converter;
Second adjusting means for adjusting the amplitude of the input current of the parallel converter so as to follow the amplitude command of the input current;
Means for generating a PWM signal for the parallel converter from the output signal of the second adjusting means;
A power conversion device comprising:
JP2003272135A 2003-07-09 2003-07-09 Power converter Expired - Lifetime JP4251030B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008312332A (en) * 2007-06-14 2008-12-25 Mitsubishi Electric Corp Uninterruptible power supply device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008312332A (en) * 2007-06-14 2008-12-25 Mitsubishi Electric Corp Uninterruptible power supply device

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