JP2005033724A - Video decoding output device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To guarantee a real-time performance by varying computational complexity of filter processing and sufficiently utilizing the computation resources when the computation complexity in decoding using a restoration processor is changed in a video decoding output device. <P>SOLUTION: In the video decoding output device, a loading state relating to the decoding in an image code stream decoding means 300 is detected from the values of a vertical synchronizing signal, a horizontal synchronizing signal and a signal V-Counter 703 counted up by falling of the horizontal synchronizing signal that is time information synchronized to the horizontal synchronizing signal, and is initialized to 0 each time the vertical synchronizing signal falls twice by a video synchronizing signal generating means 700. Further, when a load on the image code stream decoding means 300 is less, the number of filter taps in a filter processing means 500 is set high by this video decoding output device, so that the computation complexity of the filter processing means 500 is increased and when the load on the image code stream decoding means is heavy, the number of filter taps in the filter processing means 500 is set low. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a video decoding output apparatus that performs decoding processing, filtering processing, and video decoding processing of an image code string that is compressed image data in real time, and more particularly to a device that improves the efficiency of decoding processing.

  In recent years, with the spread of DVDs, digital televisions, etc., interest in multimedia technology has increased. There is a demand for lower cost in an apparatus that decodes and reproduces an image code string encoded by the MPEG technology.

Conventionally, in an apparatus for performing decoding / filtering on an encoded image code string, for example, a method described in Japanese Patent Application Laid-Open No. 09-172635 (Patent Document 1) has been considered.
JP 09-172635 A

  In FIG. 17, an NTSC decoder 19 (25) which is a decoding processing means for performing a decoding process corresponding to the transmission method on digital image data inputted from an antenna 17 and having a desired channel selected by a tuner 18 (24). And a CPU 22 which is a processing means for performing compression or expansion processing on the digital image data in accordance with a display size, and for correcting deterioration of image quality due to the compression or expansion processing on the digital image data. An image display system that includes a plurality (two in this case) of reproduction paths including a filter 21 (27) that performs filtering processing, and performs multi-screen display based on digital image data obtained from the filters 21 and 27 of the respective reproduction paths. Are reproduced by the disk reproducing device 30 and compressed by orthogonal transformation and quantization processing. An MPEG2 decoder 31 which is a decoding means for performing a decoding process on the encoded digital image data, and the digital image data decoded by the decoding means (MPEG2 decoder 31) are converted into the decoding processing means (NTSC decoder 25). ), Instead of the digital image data output from the selector 27, which is a derivation unit that leads to the filter 27, and the filter 27 from which the digital image data is derived by the derivation unit (selector 26), the compression or The image processing apparatus includes a CPU 22 that is a control unit that provides a filter coefficient for executing a filtering process for correcting image quality deterioration due to the decompression process and block distortion based on the decoding process.

  Then, the control means (CPU 22) generates a filter coefficient to be given to the filter 27 based on a motion vector or a bit rate of the compressed and encoded digital image data.

  With this configuration, images of two different channels on the same screen, or an image of one channel and an image reproduced from the disk playback device 30 can be divided and displayed simultaneously on one screen at an arbitrary size. It is possible.

  In the above apparatus, the filtering of the digital image data received by the tuner 24 and the filtering process of the digital encoded data output from the disk reproducing apparatus 30 are performed by using the existing filter 27 in combination. Thus, it is possible to provide a good digital image decoding apparatus capable of reducing block distortion without increasing the circuit scale.

  The conventional video decoding output apparatus is configured as described above, and can perform good digital image decoding processing without increasing the circuit scale. Even if the amount of computation of the decoding process by the restoration processor changes in the apparatus to be performed, there is a problem that the amount of computation of the filter processing is constant and the computation resources are not fully utilized.

  The present invention has been made to solve the above-described problems. When the amount of decoding processing by the restoration processor changes, the amount of filtering processing can be made variable so that the calculation resources can be fully utilized. An object of the present invention is to provide a video decoding output device.

  A video decoding output apparatus according to claim 1 of the present invention stores an image code string decoding processing means for decoding an image code string, which is compressed image data, and an image decoded by the image code string decoding processing means. And a memory processing unit, a tap coefficient of which is variable, a filter processing unit that performs a filtering process on an image stored in the memory unit, a video synchronization signal, and time information synchronized with the video synchronization signal Video synchronization signal generation means; and video signal output means for multiplexing the video processed by the filter processing means and stored in the memory means with the video synchronization signal generated by the video synchronization signal generation means, and outputting a video signal. Decoding processing load detection for detecting a processing load of the image code string decoding processing means using time information generated by the video synchronization signal generating means And a control unit that receives an external input signal and dynamically instructs the filter processing unit to change the number of taps based on the output of the decoding processing load detection unit and information provided as the external input signal. Means.

  The video decoding output device according to a second aspect of the present invention is the video decoding output device according to the first aspect, wherein the decoding processing load detection means is based on the time information generated by the video synchronization signal generation means. The processing load amount of the image code string decoding processing means is detected from the time required for the code string decoding processing means to decode a predetermined unit code string.

  A video decoding output device according to a third aspect of the present invention is the video decoding output device according to the first aspect, wherein the decoding processing load detecting means is based on the resolution information embedded in the image code string. The processing load amount of the image code string decoding processing means is detected from the time required for the process of decoding the code string of a predetermined unit by the sequence decoding processing means.

  The video decoding output device according to a fourth aspect of the present invention is the video decoding output device according to the first aspect, wherein the decoding processing load detection means is based on progress status information indicating a progress status of the filter processing means. The processing load amount of the image code string decoding processing means is detected from the time required for the image code string decoding processing means to decode the code string of a predetermined unit.

  The video decoding output device according to claim 5 of the present invention is the video decoding output device according to claim 2 or 4, wherein the control means is provided as an output of the decoding processing load detection means and the external input signal. In addition to information, the filter processing means is dynamically instructed to change the number of taps based on the luminance and color difference of the image code string.

  A video decoding output apparatus according to a sixth aspect of the present invention is the video decoding output apparatus according to the first aspect, wherein an enlargement / reduction process and a noise reduction process are performed when the decoding process of the image code string is performed by the external input signal. Information for performing the presence / absence switching process and the interlace / progressive conversion process.

  According to the video decoding output device of the present invention (Claim 1), the image code string decoding processing means for decoding the image code string which is the compressed data of the image, and the image code string decoding processing means decoded by the image code string decoding processing means Memory means for storing the image, filter processing means for changing the tap coefficient of the image, filtering the image stored in the memory means, a video synchronization signal, and time information synchronized with the video synchronization signal And a video signal for outputting a video signal by multiplexing the image processed by the filter processing unit and stored in the memory unit with the video synchronization signal generated by the video synchronization signal generation unit Decoding processing for detecting the processing load of the image code string decoding processing means using output means and time information generated by the video synchronization signal generating means Load detecting means and receiving an external input signal, and dynamically instructing the filter processing means to change the number of taps based on the output of the decoding processing load detecting means and the information given as the external input signal Therefore, when the load on the image code string decoding unit is low, the number of filter taps of the filter processing unit is set to be large and the amount of calculation of the filter processing unit is increased, thereby degrading the image quality. When the load of the image code string decoding means is large, the amount of image code string decoding processing is increased by setting the number of filter taps of the filter processing means to be small and reducing the calculation amount of the filter processing means. It is possible to prevent the subsequent filtering process from exceeding the amount of computation, and as a result, computational resources can be fully utilized. There is an effect.

  According to the video decoding output device of the present invention (Claim 2), in the video decoding output device according to Claim 1, the decoding processing load detection means uses the time information generated by the video synchronization signal generation means. On the basis of this, since the image code string decoding processing means detects the processing load amount of the image code string decoding processing means from the time required for the process of decoding a predetermined unit code string, the image code string decoding When the load on the means is low, the number of filter taps of the filter processing means is set to be large so as to increase the amount of calculation of the filter processing means to reduce image quality degradation. When the load on the image code string decoding means is high, the filter processing By setting the number of filter taps of the means to be small and reducing the amount of computation of the filter processing means, the amount of image code string decoding processing is large, so that Filtering can be prevented from becoming operational amount over, there is an effect that it is possible to sufficiently utilize the thus calculation resources.

  According to the video decoding output device of the present invention (Claim 3), in the video decoding output device according to Claim 1, the decoding processing load detection means is based on resolution information embedded in the image code string. The processing load amount of the image code string decoding processing means is detected from the time required for the image code string decoding processing means to decode the code string of a predetermined unit. When the load on the image code is low, the number of filter taps of the image code string decoding filter processing unit is set to increase the amount of calculation of the image code string decoding filter processing unit to reduce image quality degradation, the image resolution is high, and the image code When the load on the sequence decoding filter processing means is large, the number of filter taps of the image code sequence decoding filter processing means is set to be small and the image code sequence decoding filter processing is performed. It is possible to reduce the amount of calculation of the stage, and to prevent the filter processing of the image code string decoding filter processing means from exceeding the calculation amount when the amount of image code string decoding processing is large, and thus to fully utilize the calculation resources. There is an effect that can.

  According to the video decoding output device of the present invention (Claim 4), in the video decoding output device according to Claim 1, the decoding processing load detection means includes progress status information indicating a progress status of the filter processing means. Therefore, the processing load amount of the image code string decoding processing means is detected from the time required for the image code string decoding processing means to decode the code string of a predetermined unit. The load state of the decoding process of the image code string decoding unit is detected from the time, and when the remaining filter processing time is small and the load of the image code string decoding unit is low, the number of filter taps of the filter processing unit is set to be large. The amount of computation is increased to reduce degradation of image quality, and when the remaining time for filter processing is small and the load on the image code string decoding means is large, the filter processing is performed. By setting the number of filter taps of the means to be small, the calculation amount of the filter processing means is reduced, and the amount of image code string decoding processing is large, so that it is possible to prevent the subsequent filter processing from exceeding the calculation amount, and consequently There is an effect that the computing resources can be fully utilized.

  According to the video decoding output device of the present invention (Claim 5), in the video decoding output device according to Claim 2 or 4, the control means includes the output of the decoding processing load detection means and the external input. Since the number of taps is dynamically changed to the filter processing means based on the luminance and color difference of the image code string in addition to the information given as a signal, human visual effects are taken into consideration. In addition, by taking into account the luminance and the difference between the expressions, there is an effect that an image having a high effect by the filter processing can be obtained.

  According to the video decoding output device of the present invention (Claim 6), in the video decoding output device according to Claim 1, enlargement / reduction when the decoding process of the image code string is performed by the external input signal. Information, switching processing for presence / absence of noise reduction processing, and interlace / progressive conversion processing are provided, so that the computing resources can be fully utilized and whether expansion / reduction processing and noise reduction processing are performed. There is an effect that the switching process and the interlace / progressive conversion process can be performed.

(Embodiment 1)
Hereinafter, a video decoding output apparatus according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a video decoding processing apparatus according to Embodiment 1 of the present invention. In FIG. 1, 100 is a video decoding output device that performs decoding / filtering / video output processing of an image code sequence in real time, 200 is an image code sequence encoded according to the MPEG1 and MPEG2 standards, which are compressed image data, and 300. Is an image code string decoding processing means for decoding an MPEG1, MPEG2 standard image code string, 500 is a filter processing means for performing enlargement / reduction processing, noise reduction processing, and interlace / progressive processing, and 600 is an image code string decoding processing means. 300, memory means for storing the image processed by the filter processing means 500, 700 a vertical synchronizing signal and horizontal synchronizing signal, video synchronizing signal generating means for generating time information synchronized with the horizontal synchronizing signal, and 800 a memory The image stored in the means 600 is converted into a vertical synchronizing signal. And a video signal output means for outputting a video signal multiplexed with a horizontal synchronizing signal, 900 is a control means for controlling the image code string decoding processing means 300 and the filter processing means 500, and 1000 is an enlargement ratio information or It is an input means for giving noise reduction information. In the above configuration, the control unit 900 realizes a signal processing load detection unit.

  Next, the operation of the video decoding output device 100 configured as described above will be described below. First, the operation of the video synchronization signal generating unit 700 will be described. FIG. 2 shows a waveform diagram of a signal generated by the video synchronization signal generating means 700. In the case of NTSC interlaced video output, the video synchronization signal generating means 700, as shown in FIG. 2A, is a horizontal synchronization signal that is time information synchronized with the vertical synchronization signal, the horizontal synchronization signal, and the horizontal synchronization signal. A signal V-Counter 703 that is initialized to 0 each time the vertical synchronizing signal falls twice is generated. When the value of the signal V-Counter 703 counts 393, a control means start (start) interrupt command is issued to the control means 900.

  In addition, as shown in FIG. 2B, the video synchronization signal generation means 700 generates a video synchronization signal when the horizontal synchronization signal is 60 × 525 (Hz) and the signal V-Counter counts 786, as shown in FIG. The means 700 issues a control means start (activation) interrupt command to the control means 900.

  FIG. 3 is a diagram showing an operation flowchart of the control means 900. The control unit 900 receives a control unit start interrupt command issued by the video synchronization signal generation unit 700 (step S901), and performs pre-decoding processing (step S902) for performing settings necessary for operating the image code string decoding processing unit 300. ) Is started and the decoding completion interrupt waiting state from the image code string decoding processing means 300 is entered (step S903). When the decoding completion interrupt is received, settings necessary for operating the filter processing means 500 are entered. The filter preprocessing (step S904) is performed, and when the filter preprocessing is completed, the control unit start interrupt command from the video synchronization signal generation unit 700 is again waited (step S901), and the above contents are repeated. Processing contents of the pre-decoding process (step S902) by the control unit 900 will be described.

  FIG. 4 is a flowchart of the pre-decoding process. First, the control unit 900 acquires information provided by the input unit 1000 (step S906). Information to be acquired includes arbitrary enlargement / reduction ratio information, noise reduction ON / OFF information, and interlace / progressive video signal output selection information.

  Next, in order to cause the image code string decoding processing unit 300 to perform one frame decoding processing, the control unit 900 issues a decoding start interrupt instruction to the image code string decoding processing unit 300 (step S907), and before decoding. The process ends.

  Next, details of processing contents of the filter preprocessing (step S904) will be described with reference to FIG. First, the control means 900 sets the number of filter taps (step S908), and then enlargement / reduction ratio information and noise reduction ON / OFF information obtained by acquiring information (step S906) given by the input means 1000. Then, the interlace / progressive output selection information is set in the filter processing means 500 (steps S909 to S911).

  Next, in order to cause the filter processing unit 500 to perform one frame of filter processing, a filter start interrupt instruction is issued to the filter processing unit 500 (step S913), and the pre-filter processing is terminated.

Next, the processing content of the filter tap number setting (step S908) will be described in detail with reference to FIG. First, the change in the number of filter taps (step S914) based on the decoding processing time information (value of the signal V-Counter 703) will be described. The control unit 900 reads the value of the signal V-Counter 703 immediately after the start of the filter preprocessing (step S904), and can know the time taken by the image code string decoding unit 300 to decode one frame based on the value. Table 1 shows the relationship between the signal V-Counter 703 and the decoding processing time when the maximum value of the number of filter taps is N. The larger the decoding processing time is, the smaller the number of filter taps is set.

Next, when the information given by the input means 1000 is noise reduction ON, the number of filter taps is decreased (step S915).
Next, when the information given by the input unit 1000 is a progressive video output, the number of filter taps is further reduced (step S916).

When the change in the number of filter taps is completed, the number of filter taps is set for the filter processing unit 500 (step S917), and the process ends.
FIG. 7 is a timing chart showing an example of the effect of changing the number of filter taps based on the operation of the video decoding output device 100 described above. FIG. 7A will be described. When the value of the signal V-Counter 703 reaches 393, the video synchronization signal generation unit 700 issues a control unit start interrupt instruction 1101 to the control unit 900.

  In response to the interrupt instruction, the control unit 900 performs a pre-decoding process 1102. The control unit 900 acquires the information given by the input unit 1000 in the pre-decoding process 1102 and acquires a vertical enlargement ratio of 3/4, noise reduction ON, and interlaced output in this example.

  Next, a decoding start interrupt instruction 1103 is issued to the image code string decoding processing means 300. The image decoding processing unit 300 issues a decoding completion interrupt instruction 1105 to the control unit 900 after the completion of the one frame decoding processing 1104. The control unit 900 receives an interrupt and performs filter preprocessing 1106.

  The control means 900 reads the value of the signal V-Counter 703 immediately after the start of the filter preprocessing 1106. In this example, this value is 120, the number of filter taps is set to 7-1 = 6 according to the conditions in Table 1, and the decoding preprocessing is performed. By the noise reduction ON acquired in 1102, 6-1 = 5 is set in this example, and 5 taps are set for the filter processing unit 500. Next, the control unit 900 issues a filter start interrupt instruction 1107 to the filter processing unit 500. The filter processing unit 500 performs a 5-tap filter processing 1108.

  Next, FIG. 7B will be described. The outline of the operation is the same as in FIG. 7A, and the control means 900 reads the value of the signal V-Counter 703 immediately after the start of the filter preprocessing 1106. In this example, this value is more than that shown in FIG. It is assumed that the time taken to decode one frame is 250, and the number of filter taps is set to 7-2 = 5 according to the conditions in Table 1, and the noise reduction ON acquired in the pre-decoding process 1102 is set to 5-1 in this example. = 4 and 4 taps are set for the filter processing unit 500. The filter processing means 500 performs the filter processing 1108 with 4 taps.

  As described above, when the decoding process time by the image code string decoding unit 300 is small as in the case shown in FIG. 7A, the calculation time of the filter processing unit 500 has a margin, so the number of filter taps is set. When a large number is set and the amount of calculation of the filter processing unit 500 is increased, deterioration in image quality is reduced. Conversely, as shown in FIG. 7B, when the decoding processing time by the image code string decoding unit 300 is long. Therefore, the number of filter taps is set to be small, the amount of calculation of the filter processing unit 500 is reduced, and the amount of calculation of the filter processing is prevented from being exceeded from the image code string decoding processing.

  Thus, according to the first embodiment, the video synchronization signal generation means 700 counts up at the falling edge of the horizontal synchronization signal, which is time information synchronized with the vertical synchronization signal, the horizontal synchronization signal, and the horizontal synchronization signal. , Generating a signal V-Counter 703 that is initialized to 0 each time the vertical synchronization signal falls twice, detecting a load state applied to the decoding process of the image code string decoding unit 300 from the value of the signal V-Counter 703, When the load on the image code string decoding unit 300 is low, the number of filter taps of the filter processing unit 500 is set to be large so that the amount of calculation of the filter processing unit 500 is increased, thereby reducing image quality degradation. When the load on the filter processing unit 500 is large, the number of filter taps of the filter processing unit 500 is set to be small and the calculation amount of the filter processing unit 500 is reduced By reducing the amount, it is possible to prevent the subsequent filtering process from exceeding the calculation amount due to the large amount of the image code string decoding process, and thus the calculation resources can be fully utilized.

(Embodiment 2)
A video decoding output apparatus according to the second embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a diagram showing the configuration of the video decoding processing apparatus according to the second embodiment. In FIG. 8, reference numeral 2000 denotes a video decoding output device for performing decoding processing, filtering processing, and video output processing of an image code sequence in real time. 2100 denotes an image code sequence encoded according to the MPEG1 and MPEG2 standards, which are compressed image data. Is an image code string decoding filter processing means for performing decoding processing of an image code string of the MPEG1 and MPEG2 standards, performing filter processing on an image after decoding processing, and acquiring resolution information embedded in the image code string 2300 is a memory means for storing an image processed by the image code string decoding filter processing means 2200, 2400 is a video synchronization signal generating means for generating a vertical synchronization signal, a horizontal synchronization signal, and a counter synchronized with the horizontal synchronization signal, 2500 displays the image stored in the memory means 2300 vertically. Video signal output means for outputting a video signal multiplexed with a period signal and a horizontal synchronizing signal, 2600 is a control means for controlling the image code string decoding filter processing means 2200, and 2700 is an enlargement rate information and noise reduction for the control means. It is an input means for giving information.

  Next, the operation of the video decoding output device 2000 configured as described above will be described below. First, the video synchronization signal generating means 2400 will be described. FIG. 2 shows a signal generated by the video synchronization signal generating means 2400. As shown in FIG. 2A, the video synchronization signal generation unit 2400 generates a vertical synchronization signal and a horizontal synchronization signal. Also, the signal V-Counter 703 is counted up at the falling edge of the horizontal synchronizing signal and initialized to 0 each time the vertical synchronizing signal falls twice. When the value of the signal V-Counter 703 counts 393, a control means start interrupt command is issued to the control means 2600. FIG. 2 (b) shows the generation of a video synchronization signal at the time of progressive video output. When the horizontal synchronization signal is 60 × 525 (Hz) and the signal V-Counter 703 counts 786, a decoding start interrupt command is sent to the control means 2600. Issue.

  FIG. 9 is an operation flowchart of the control means 2600. The control unit 2600 receives a control unit start interrupt command issued by the video synchronization signal generation unit 2400 (step S2601), and performs pre-decoding processing (step S2602) for performing settings necessary for operating the image code string decoding filter processing unit 2200. When the pre-decoding process is completed, the control unit start interrupt waiting state again from the video synchronization signal generation unit 2400 is entered (step S2601), and the above contents are repeated.

Detailed processing contents of the pre-decoding process (step S2602) will be described with reference to FIG.
First, the information provided by the input unit 2700 is acquired (step S2603). Information to be acquired includes enlargement / reduction ratio information, noise reduction ON / OFF information, and interlace / progressive output selection information.

  Next, the enlargement / reduction ratio, noise reduction, and interlace / progressive output selection information, which are information provided by the input unit 2700, are set in the image encoding / decoding filter processing unit 2200 (steps S2604, S2605, and S2606).

  Next, the number of filter taps is set (step S2607), and then a decoding filter start interrupt instruction is issued to the image code string decoding filter processing means 2200 in order to start decoding processing and filtering processing for one frame ( Step S2608) The process ends.

  Next, the processing content of the filter tap number setting (step S2607) will be described with reference to FIG. First, when the information given by the input means 2700 is noise reduction ON, the number of filter taps is decreased (step S2609).

  Next, when the information given by the input means 2700 is a progressive video output, the number of filter taps is decreased (step S2610).

  When the above change in the number of filter taps is completed, the number of filter taps is set for the image code string decoding filter processing means 2200 (step S2611), and the process ends.

The above is the processing related to the control unit 2600.
Next, processing contents of the image code string decoding filter processing means 2200 will be described with reference to FIG.

When receiving the decoding filter start interrupt instruction from the control means 2600 (step S2201), the image code string decoding filter processing means 2200 starts the processing, first reads the image code string (step S2202), and embeds it in the image code string. The obtained resolution information is acquired (step S2203). Based on the resolution information, the image code string decoding filter processing means 2300 can predict the time required for decoding one frame. Table 2 shows the relationship between the resolution and the predicted decoding process time when the current filter tap number setting value is N. The larger the resolution, the smaller the filter tap number.

  The number of filter taps is changed according to the resolution information shown in Table 2 (step S2204).

  Next, the number of filter taps is set (step S2205). Next, one-frame decoding processing is performed (step S2206), and then the filtering processing (step S2207) with the designated number of filter taps is finished.

  FIG. 13 is a timing chart showing an example of the effect of changing the number of filter taps based on the operation of the video decoding output device 2000 according to the second embodiment. FIG. 13A will be described. When the value of the signal V-Counter 703 reaches 393, the video synchronization signal generation unit 700 issues a control unit start interrupt 2800 to the control unit 2600. In response to the interruption, the control unit 2600 performs a pre-decoding process 2801. The control means 2600 obtains the information given by the input means 2700, and in this example, obtains a horizontal enlargement ratio of 2 times, a vertical enlargement ratio of 2 times, noise reduction ON, and an interlace output. In addition, the image code string filter processing unit 2200 is configured to change the number of filter taps based on noise reduction information and to change the number of filter taps based on interlace / progressive output selection information.

  Next, the control unit 2600 issues a decoding start interrupt 2802 to the image code string decoding filter processing unit 2200. The image code string decoding filter processing means 2200 receives this and extracts the resolution information embedded in the image code string to change and set the number of filter taps.

  In this example, when the resolution is horizontal size = 352 and vertical size = 240, the number of filter taps is set to 7-2 = 5 based on Table 2, and 5 taps are set. The filter processing of the image code string decoding filter processing means 2200 performs 1-frame decoding processing 2803 and 5-tap filter processing 2805.

  Next, a case where an image having the resolution shown in FIG. 13B is processed will be described. The outline of the operation is the same as in FIG. 13A, and the image code string decoding filter processing means 2200 extracts the resolution information embedded in the image code string, changes the number of filter taps, and sets it. In this example, when the resolution is horizontal size = 544 and vertical size = 480, the number of filter taps is set to 7-3 = 4 based on Table 2 and 4 taps are set. The filter processing of the image code string decoding filter processing means 2200 performs filter processing 2805 with four taps.

  As described above, when it is predicted that the decoding process time by the image code string decoding filter processing unit 2200 is short, the calculation time of the filter process has a margin, so the filter process calculation is performed by setting a large number of filter taps. Decreasing the image quality by increasing the amount, setting the number of filter taps to be small when the decoding time by the image code string decoding filter processing unit 2200 is predicted to be large, and reducing the calculation amount of the filter processing unit 2200 Thus, the amount of computation of the filter process is prevented from being exceeded from the image code string decoding process.

  As described above, according to the second embodiment, the load state applied to the decoding process is detected based on the resolution information embedded in the image code string by the image code string decoding filter processing unit 2200, and the image code string decoding process is performed. When the load is low, the number of filter taps of the image code string decoding filter processing unit 2200 is set to be large, and the amount of calculation of the image code string decoding filter processing unit 2200 is increased to reduce image quality degradation, and the image resolution is high. When the load on the code string decoding filter processing means 2200 is large, the number of filter taps of the image code string decoding filter processing means 2200 is set to be small to reduce the amount of calculation of the image code string decoding filter processing means 2200, and When the amount is large, the filter processing of the image code string decoding filter processing means 2200 is Can be prevented from becoming a calculated amount over, it is possible to sufficiently utilize the thus calculation resources.

(Embodiment 3)
Next, a video decoding output apparatus according to a third embodiment of the present invention will be described with reference to the drawings. The video decoding output apparatus according to the third embodiment has the same basic configuration as that of the first and second embodiments described above, and the filter processing operation of the filter processing unit 500 or the image code string decoding processing unit 2200 is different. It is characterized by that. Also, as shown in FIG. 18, the difference is that FLINE generation means 1100 and 2800 which are filter progress information are provided. 18A shows a video decoding output device having the basic configuration of the first embodiment, and FIG. 18B shows a video decoding output device having the basic configuration of the second embodiment.

The operation will be described below with reference to FIG. 18A configured based on the first embodiment.
FIG. 14 is a flowchart showing the operation of the filter processing unit 500. The filter processing unit 500 receives the filter start interrupt issued from the control unit 900 and starts processing (step S3000). Next, one-line filter processing of the image is performed (step S3001).

  Next, FLINE which is filter progress information is incremented (step S3002). Next, when FLINE does not reach the 7 / 8th line of the image (step S3003), the process returns to step S3001 and step S3002 until the FLINE reaches the 7 / 8th line of the image. On the other hand, when FLINE reaches the 7 / 8th line of the image in step S3003, the process proceeds to step S3004 to change the number of filter taps.

表３に示すように、フィルター処理残時間が少ないほどフィルタータップ数を減少させて設定する。 In changing the number of filter taps, first, the value of the signal V-Counter 703 is read. The remaining filter processing time can be known from the value of the signal V-Counter 703. Table 3 shows the relationship between the signal V-Counter 703 and the remaining filter processing time.

As shown in Table 3, the smaller the remaining filter processing time is, the smaller the number of filter taps is set.

Next, the remaining filter processing is performed with the changed number of filter taps (step S3005). At the end of the process, FLINE = 0 is set (step S3006), and the process ends.
FIG. 15 is a timing chart showing an example of the effect of changing the number of filter taps by filter processing.

  When the value of the signal V-Counter 703 generated by the video synchronization signal generation unit 700 reaches 393, the video synchronization signal generation unit 700 issues a control unit start interrupt 3101 to the control unit 900.

  In response to the interruption, the control unit 900 performs a pre-decoding process 3102. In the pre-decoding process 3102, information given by the input unit 1000 is acquired, and in this example, horizontal 3/4 times, noise reduction OFF, and interlaced output are acquired.

  Next, the control unit 900 issues a decoding start interrupt 3103 to the image code string decoding processing unit 300. The image decoding processing unit 300 issues a decoding completion interrupt 3105 to the control unit 900 after the completion of the one frame decoding processing 3104. The control unit 900 receives an interrupt and performs filter preprocessing 3106. The filter processing means 500 reads the value of the signal V-Counter 703 immediately after the start of the filter preprocessing 3106. In this example, the value is 120. According to the conditions in Table 1, the number of filter taps is 7-1 = 6, A tap is set for the filter processing means 500.

  Next, a filter start interrupt 3107 is issued to the filter processing means 500. The filter processing unit 500 performs a 6-tap filter process 3108. Here, when the vertical size of the image is 480 and FLINE = 480 * 7/8 = 420, the remaining filter time is checked based on the value of the signal V-Counter 703. In this example, it is assumed that this value is 260, and according to Table 3, the number of filter taps is set to 6-2 = 4, and the number of filter taps is set. The filter processing means 500 performs the remaining filter processing with the number of filter taps being 4.

  As shown in FIG. 15, by checking the remaining filter time during the filter process and reducing the number of filter taps, it is possible to prevent the calculation amount of the filter process from being exceeded and to guarantee real-time performance.

  As described above, according to the third embodiment, the video synchronization signal generation means 700 counts up the vertical synchronization signal, the horizontal synchronization signal, the time information synchronized with the horizontal synchronization signal, and the falling edge of the horizontal synchronization signal. The signal V-Counter 703, which is initialized to 0 each time the vertical synchronization signal falls twice, is generated, and the signal V-Counter 703 is obtained when the filter progress information FLINE reaches a predetermined value (7/8 line). The remaining filter time is checked based on the value of the -Counter 703, the load state applied to the decoding process of the image code string decoding unit 300 is detected from the remaining filter process time, and the load of the image code string decoding unit 300 is reduced because the remaining filter process time is small. When the value is low, the number of filter taps of the filter processing unit 500 is set to be large, and the amount of calculation of the filter processing unit 500 is increased to improve the image quality. Deterioration is reduced, and when the filter processing remaining time is small and the load on the image code string decoding unit 300 is large, the number of filter taps of the filter processing unit 500 is set to be small to reduce the calculation amount of the filter processing unit 500, and the image code string decoding is performed. Since the amount of processing is large, it is possible to prevent the subsequent filter processing from exceeding the amount of computation, and as a result, computation resources can be fully utilized.

(Embodiment 4)
Next, a video decoding output apparatus according to a fourth embodiment of the present invention will be described with reference to the drawings. The basic configuration of the video decoding output apparatus of the fourth embodiment is the same as that of the first and second embodiments described above, and the filter processing of the filter processing unit 500 or the image code string decoding filter processing unit 2200 is different. It is characterized by. Hereinafter, the operation will be described based on the first embodiment.

  FIG. 16 is a diagram showing an operation flowchart of the filter processing means 500. When the filter processing unit 500 receives a filter processing start interrupt from the control unit 900 (step S4000), the filter processing unit 500 first acquires the number of filter taps N (step S4001).

  Next, in order to increase the number of filter taps with respect to luminance, N + 1 is set as the number of luminance filter taps (step S4002). Next, in order to reduce the number of filter taps with respect to the color difference, N−1 is set as the number of color difference filter taps (step S4003).

  Next, 1-frame filter processing is performed with different filter tap numbers for luminance and color difference (step S4004), and the processing ends.

  As described above, by reducing the number of filter taps for color differences that are difficult for the human eye to perceive and increasing the number of filter taps for brightness that is easily perceived by the human eye, an image that is highly effective by filtering Can be obtained.

  As described above, according to the fourth embodiment, when setting the tap coefficient of the filter, only the load state applied to the decoding process of the image code string decoding unit 300 (image code string decoding filter processing unit 2200) is considered. In addition, in consideration of human visual effects, luminance and color difference are also taken into account, so that an image with a high effect by filter processing can be obtained.

  The value of the increase / decrease in the number of filter taps performed in each of the above embodiments is not limited to the example described in each of the above embodiments.

It is a block diagram which shows the structure of the video decoding output apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the signal generation timing of the video synchronous signal generation means which comprises the said video decoding output apparatus. It is a figure which shows the operation | movement flowchart of the control means which comprises the said video decoding output apparatus. It is a figure which shows the operation | movement flowchart of the pre-decoding process in the pre-decoding process of the said video decoding output apparatus. It is a figure which shows the operation | movement flowchart of the filter pre-processing in the control means which comprises the said video decoding output apparatus. It is a figure which shows the operation | movement flowchart of the filter tap number setting during the filter pre-processing of the said video decoding output apparatus. It is a timing diagram for showing the effect of the above-mentioned video decoding output device. It is a block diagram which shows the structure of the video decoding output apparatus which concerns on Embodiment 2 of this invention. It is a figure which shows the operation | movement flowchart of the control means which comprises the video decoding output apparatus which concerns on the said Embodiment 2. FIG. It is a figure which shows the operation | movement flowchart of the decoding pre-process of the video decoding output apparatus which concerns on the said Embodiment 2. FIG. It is a figure which shows the operation | movement flowchart of the filter tap number setting in the video decoding output apparatus which concerns on the said Embodiment 2 during the pre-decoding process. It is a figure which shows the operation | movement flowchart of the image code stream filter process means which comprises the video decoding output device which concerns on the said Embodiment 2. FIG. It is a timing diagram for showing the effect of the video decoding output device of the second embodiment. It is a timing diagram of the filter process means which comprises the video decoding output apparatus which concerns on Embodiment 3 of this invention. It is a timing diagram for showing the effect of the video decoding output device of the third embodiment. It is a timing diagram of the filter process means which comprises the video decoding output apparatus which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the conventional video decoding output apparatus. It is a block diagram which shows the structure of the video decoding output apparatus concerning Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Video decoding output apparatus 200 Image code sequence 300 Image code sequence decoding process means 400 1st memory means 500 Filter processing means 600 2nd memory means 700 Video synchronization signal generation means 800 Video signal output means 900 Control means 1000 Input means 2000 Video decoding output device 2100 Image code string 2200 Image code string decoding filter processing means 2300 First memory means 2400 Video synchronization signal generating means 2500 Video signal output means 2600 Control means 2700 Input means

Claims (6)

Image code string decoding processing means for decoding an image code string that is compressed image data;
Memory means for storing images decoded by the image code string decoding processing means;
Filter processing means whose tap coefficient is variable, and which performs filter processing on the image stored in the memory means;
A video synchronization signal, and a video synchronization signal generating means for generating time information synchronized with the video synchronization signal;
Video signal output means for multiplexing the image processed by the filter processing means and stored in the memory means with the video synchronization signal generated by the video synchronization signal generation means, and outputting a video signal;
Decoding processing load detection means for detecting a processing load of the image code string decoding processing means using time information generated by the video synchronization signal generating means;
Control means for receiving an external input signal, and dynamically instructing the filter processing means to change the number of taps based on the output of the decoding processing load detection means and information given as the external input signal;
A video decoding output device comprising: The video decoding output device according to claim 1, wherein
The decryption processing load detection means includes
Based on the time information generated by the video synchronization signal generating means, the processing load amount of the image code string decoding processing means is calculated from the time required for the image code string decoding processing means to decode a code string of a predetermined unit. Detect
A video decoding output device. The video decoding output device according to claim 1, wherein
The decryption processing load detection means includes
Based on the resolution information embedded in the image code string, the processing load amount of the image code string decoding processing means is calculated from the time required for the image code string decoding processing means to decode a code string of a predetermined unit. To detect,
A video decoding output device. The video decoding output device according to claim 1, wherein
The decryption processing load detection means includes
Based on the progress status information indicating the progress status of the filter processing means, the processing load of the image code string decoding processing means is calculated from the time required for the image code string decoding processing means to decode a code stream of a predetermined unit. Detect the quantity,
A video decoding output device. The video decoding output device according to claim 2 or 4,
The control means includes
In addition to the output of the decoding processing load detecting means and the information given as the external input signal, the number of taps is dynamically changed with respect to the filtering means based on the luminance and color difference of the image code string. Instruct,
A video decoding output device. The video decoding output device according to claim 1, wherein
Information for performing enlargement / reduction processing, switching processing of presence / absence of noise reduction processing, and interlace / progressive conversion processing when performing decoding processing of an image code string is given by the external input signal.
A video decoding output device.

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