JP4184223B2 - Transcoder - Google Patents

Description

  The present invention relates to a technique for transcoding moving image data received by digital broadcasting or the like into moving image data of different encoding formats.

In recent years, in order to enable digital broadcasting to be viewed not only by a TV receiver but also by a mobile terminal or the like, for example, as disclosed in Patent Document 1, an MPEG2 stream broadcast for a TV receiver is reduced to a low level such as an MPEG4 stream. Techniques for transcoding to resolution streams have been proposed.
In this technology, considering the reduction of the disk occupancy rate of the device and the reduction of the time from the reception of the MPEG2 stream to the generation of the MPEG4 stream, the transcoder can transmit data to the TV receiver as shown in FIG. The transcoding is performed simultaneously with the streaming reproduction.

In FIG. 1, when the transcoder receives the MPEG2 stream, the transcoder decodes the compressed video data included in the MPEG2 stream by the decoding unit 80 and outputs the video data to the resizing unit I50 and the resizing unit II60. The resizing unit I50 converts the video data into a resolution of HDTV receiver, for example, 1920 pixels × 1080 lines, 30 frames / s, and outputs the converted data to the receiver. At the same time, the resizing unit II 60 converts the video data into a resolution for mobile terminals, for example, a resolution of 360 pixels × 240 lines, 10 frames / s, and outputs the converted data to the re-encoding unit 70. The re-encoding unit 70 performs MPEG4 format encoding and outputs an MPEG4 stream. This MPEG4 stream is transmitted to the mobile terminal through the Internet or a recording medium.
JP 2001-285875 A

  In contrast to the prior art shown in FIG. 1, the present invention has an object to provide a transcoder with a reduced amount of hardware in order to reduce the size and cost of the apparatus.

  In order to achieve the above object, the transcoder of the present invention reproduces a moving image, which is a set of images, to a reproducing device that reproduces a moving image by alternately repeating a display period for displaying an image and a non-display period for not displaying the image. A transcoder for resizing and outputting to a first resolution required by the machine, a resizing unit for resizing a moving image to a moving image of a specified resolution, and displaying one image for each display period In addition, the first resolution is designated in the resizing unit, and each image in the moving image is resized. In the interval between the resizing of each image, the resizing unit has a second resolution lower than the first resolution. A control unit that designates the resolution and resizes each image in the moving image.

  With the above-described configuration, the resizing unit performs resizing to the first resolution in accordance with the display period of the playback device. As a result, the resizing processing time becomes free corresponding to the non-display period, and the second time is included in the free time. Resize to resolution. As a result, the transcoder of the present invention can perform two types of resizing in parallel with one resizing portion without having two resizing portions as in the prior art.

  The transcoder further includes a receiving unit for receiving encoded moving image data from the outside, a decoding unit for decoding moving image data to obtain a moving image, and encoding a moving image to newly generate a moving image. An encoding unit that generates data, and the control unit specifies a first resolution for each image in the moving image as a result of receiving the moving image data by the receiving unit and decoding the decoding unit. The resizing is performed by the resizing unit, and the control unit is further configured to cause the encoding unit to encode a moving image composed of each image obtained as a result of the resizing by specifying a second resolution. It may be configured.

With this configuration, the moving image resized at the second resolution is encoded by the encoding unit, and can be recorded on a recording medium, for example, via the Internet or transmitted to a mobile terminal or the like.
In the transcoder, the encoding unit calculates a prediction error by a predetermined calculation between consecutive images forming a moving image to be encoded, and encodes a moving image based on the prediction error. The result of encoding once is decoded using the decoding unit in a period other than the decoding period for resizing by designating the first resolution, and the decoding result is calculated for calculating the prediction error. You may comprise so that it may be used for.

With this configuration, the encoding unit performs decoding for predictive encoding using the decoding unit using the free time of the decoding unit, that is, the free time of decoding for resizing to the first resolution. The circuit of the encoding unit can be simplified.
In the transcoder, the moving image data received by the control unit by the control unit is DCT and quantized, and the decoder performs inverse quantization corresponding to the quantization on the moving image data. An inverse quantization unit that performs the inverse DCT corresponding to the DCT on the moving image data, and the control unit performs decoding on the decoding unit and the encoding unit performs on the decoding unit The decoding may be configured to be processing including the inverse quantization and the inverse DCT.

With this configuration, the decoding unit and the encoding unit can share the inverse quantization unit and the inverse DCT unit.
The transcoder includes a selector, an adder / subtracter, a multiplier, and a cumulative adder, each of which multiplies the output value of the selector and the output value of the adder / subtracter by the multiplier. Or the output value of the adder / subtracter includes a shared circuit connected to be input to the cumulative adder, the resizing unit and the encoding unit share the shared circuit, and the resizing unit includes: The selector performs selection of a filter coefficient, the adder / subtracter adds adjacent pixels constituting the image, the selected filter coefficient and the addition result of the pixels are multiplied by the multiplier, and the multiplication result The cumulative adder performs cumulative addition to resize the image, and the encoding unit causes the selector to select a pixel to be compared between successive images. A configuration in which the subtraction between pixels is performed by the adder / subtracter, and the difference value as the subtraction result is cumulatively added by the cumulative adder to perform the predetermined calculation and obtain the result of the cumulative addition as the prediction error. May be.

With this configuration, a circuit used for resizing and motion prediction can be shared.
In the transcoder, the one display period may be a period for displaying an image corresponding to one field.
Since the CRT receiver has a vertical blanking period every time one field is displayed, the transcoder uses the free time of resizing to the first resolution that occurs in accordance with the vertical blanking period to generate the second resolution. Resizing to
The first resolution may be HDTV or SDTV size, and the second resolution may be CIF size, QVGA size, or QCIF size.

Further, the resizing unit may be configured so that when the second resolution is specified and each image in the moving image is resized, the images constituting the moving image are thinned out to be resized. Good.
Since the bit rate of the moving image is lowered by this thinning, resizing to the second resolution can be performed at higher speed.

  The moving image may be in the MPEG2 format.

Hereinafter, a transcoder according to an embodiment of the present invention will be described.
This transcoder is provided in a satellite broadcast receiving device or a DVD (Digital Versatile Disc) playback device connected to an HDTV receiver or the like. When this receiving device or reproducing device acquires an MPEG2 stream from a satellite broadcast or a DVD, it inputs compressed video data (MPEG2 compressed video data) included in the MPEG2 stream to a transcoder. Receiving this input, the transcoder decodes the compressed video data, performs resizing according to the display performance of the receiver, and outputs it to the receiver. In parallel with the decoding and resizing processes, the transcoder transcodes the compressed video data related to the processes into MPEG4 compressed video data (MPEG4 compressed video data) for mobile terminals such as mobile phones. That is, after the decoded video data is resized in accordance with the display performance of the mobile terminal, it is encoded in MPEG4 format and output. The output MPEG4 compressed video data is recorded in a memory such as an SD card by a recording device provided in the receiving device or the playback device, or sent to a mobile terminal through the Internet or the like.

FIG. 2 is a configuration diagram of the transcoder.
In the figure, a transcoder 100 includes a decoding unit 10 for decoding MPEG2 compressed video data, a pixel processing unit 20 for mainly performing resizing for a receiver and a mobile terminal, and a recoding for encoding MPEG4 compressed video data. It comprises an encoding unit 30 and a processor 40 that controls each component.

  The decoding unit 10 includes a VLD (VLD: Variable Length Decoding) unit 12, an IQ (IQ: Inverse Quantization) unit 14, an IDCT (IDCT: Inverse Discrete Transform Transform) unit 16 and an MC (MC: Motion Coding unit). According to the control of the processor 40, MPEG2 compressed video data input from the outside is decoded and video data is output.

  The VLD unit 12 performs variable length decoding on the compressed video data. The decoded data includes various control information and macroblock data. The VLD unit 12 outputs control information to the processor 40 and outputs macroblock data to the IQ unit 14. The processor 40 that has received the control information analyzes the control information and controls each component of the decoding unit 10 according to the analysis result.

The IQ unit 14 dequantizes the macroblock data and outputs the result to the IDCT unit 16.
The IDCT unit 16 performs inverse discrete cosine transform on the dequantized macroblock data and outputs the result to the MC unit 18.
The MC unit 18 performs motion compensation on the macroblock data after the inverse discrete cosine transform, and outputs the resulting video data to the pixel processing unit 20.

Since variable length decoding, inverse quantization, inverse discrete cosine transform and motion compensation are known techniques, detailed description thereof will be omitted.
The pixel processing unit 20 resizes the video data output from the decoding unit 10 to a resolution specified by the processor 40 under the control of the processor 40.
There are two types of resolution designated by the processor 40: a resolution for a receiver and a resolution for a mobile terminal. The resolution for the receiver is acquired by the transcoder 100 from the receiver or stored in advance. For example, the resolution for HDTV is a screen size of 1920 pixels × 1080 lines and a frame rate of 30 frames / s. . Alternatively, the resolution for SDTV is 720 pixels × 480 lines, and the frame rate is 30 frames / s. The resolution for the mobile terminal is acquired by the transcoder 100 from the mobile terminal or stored in advance, and is, for example, CIF size 360 pixels × 240 lines and a frame rate of 10 frames / s. Instead of the CIF size, a QVGA size (320 pixels × 240 lines), a QCIF size (176 pixels × 144 lines), or the like may be used.

In addition to the resizing process, the pixel processing unit 20 performs a motion prediction process for each macroblock on the video data resized for the mobile terminal according to the control of the processor 40.
The pixel processing unit 20 includes a resizing / ME shared circuit 22 and uses this circuit in a time division manner during resizing processing and motion prediction processing. Details of this circuit will be described later with reference to FIG.

The re-encoding unit 30 further performs MPEG4 encoding on the data after the motion prediction processing and outputs MPEG4 compressed video data.
The re-encoding unit 30 includes a DCT (Discrete Cosine Transform) unit 32, a Q (Quantization) unit 34, and a VLC (Variable Length Coding) unit 36.

The DCT unit 32 performs discrete cosine transform on the macroblock data after the motion prediction process input from the pixel processing unit 20, and outputs the result to the Q unit 34.
The Q unit 34 quantizes the macroblock data subjected to discrete cosine transform, and outputs the result to the VLC unit 36.
The VLC unit 36 performs variable length coding on the quantized macroblock data and outputs the resulting MPEG4 compressed video data.

Note that the re-encoding unit 30 may be realized using a single microcomputer that performs the above-described processes.
FIG. 3 is a diagram illustrating the timing of each process of the transcoder 100.
In the same figure, P1, P2,. . . , P8P1 are vertical blanking periods. The vertical blanking period is a period from when the receiver has finished scanning the video signal of one screen (one field in this embodiment) to when scanning of the next screen is started. In the present embodiment, this vertical blanking period is a vertical blanking period that appears for each field when the receiver performs interlace scanning of a video signal having a screen size of 1920 pixels × 1080, and is 22.5H. . Here, H is one horizontal scanning period.

In a period between one vertical blanking period and the next vertical blanking period, the receiver scans the video signal of each field and displays each field. This period is called a vertical scanning period.
The pixel processing unit 20 performs resizing for the receiver in accordance with the output timing to the receiver so that the receiver can display each field in each vertical scanning period.

  More specifically, the resize for the receiver includes a vertical resize by the vertical filter (vertical resize) and a horizontal resize by the horizontal filter (horizontal resize). First, the pixel processing unit 20 performs vertical resizing on the decoded video signal using a vertical filter for each frame. Subsequently, the pixel processing unit 20 performs horizontal resizing on the video signal that has been resized in the vertical direction using a horizontal filter. Each frame includes a top-field video signal in the first half and a bottom-field video signal in the second half. Therefore, the resizing by the horizontal filter is performed alternately with the horizontal resizing for the top field and the horizontal resizing for the bottom field.

  The pixel processing unit 20 performs horizontal resizing of the top and bottom fields in accordance with each vertical scanning period as shown in FIG. Specifically, for example, horizontal resizing of one top field is performed in a period from time t28 to t29 substantially synchronized with the vertical scanning period between P3 and P4, and from time t30 in accordance with the vertical scanning period between P4 and P5. Horizontal resizing of one bottom field is performed in the period of t31.

For this reason, the period between the horizontal resizing of one field and the horizontal resizing of the next field, that is, the period of t25-t26, t27-t28, t29-t30, etc. is a period corresponding to about 22H to 23H. Horizontal resizing of is not performed.
Then, the pixel processing unit 20 performs vertical resizing of each frame at a timing slightly earlier than the horizontal resizing so that the horizontal resizing of each field is performed without delay. Specifically, for example, vertical resizing of one frame corresponding to the top and bottom fields is performed between t2 and t3 so that horizontal resizing of the top field from t28 to t29 and bottom field from t30 to t31 is performed without delay. . t2 is a time slightly earlier than the time t28 at which the horizontal resizing of the top field starts, and t3 is a time slightly earlier than the time t31 at which the horizontal resizing of the bottom field ends.

By performing vertical resizing for each frame in this way, reception is performed in the period between the vertical resizing of one frame and the vertical resizing of the next frame, that is, the period of t1-t2, t3-t4, and t5-t6. There is a period when vertical resizing for the machine is not performed.
If the processing amount per unit data of horizontal resizing and vertical resizing is the same, the length of this period is a vertical blanking period for each frame, that is, a period corresponding to 45H. However, the length of the period in which the vertical resize for the receiver is not performed varies depending on the processing capability of the vertical filter, the amount of the decoded video signal, and the like, and does not necessarily correspond to 45H. However, if the vertical resizing is performed so that the horizontal resizing is performed without any delay, a period in which the vertical resizing for the receiver is not performed occurs for each frame.

The pixel processing unit 20 performs the resizing and motion prediction processing for the mobile terminal using the vertical filter using the period in which the vertical resizing for the receiver is not performed.
Specifically, resizing for the mobile terminal is performed using a vertical filter between t7 and t8 in the period from t1 to t2. The resize processing target frame is the same frame as the vertical resize processing target frame for the receiver that is performed during the period from t0 to t1. That is, the pixel processing unit 20 performs vertical resizing for the receiver in the period from t0 to t1 on the video data of one frame output from the decoding unit 10, and from t7 to t8 on the video data of the same frame. Resize for mobile devices during the period.

  The resizing for the mobile terminal in the period from t7 to t8 is processing including both vertical resizing and horizontal resizing. That is, the pixel processing unit 20 performs vertical resizing for the mobile terminal for one frame in the first half of t7 to t8, and performs horizontal resizing for the video data of one frame that has been vertically resized in the second half. A vertical filter is used for both the vertical resizing and the horizontal resizing.

Subsequently, the pixel processing unit 20 performs motion prediction processing on the video data for one frame resized in the period from t7 to t8 between t8 and t9. Note that the period from t7 to t9 is included in the same time period as the period from t1 to t2 or the period from t1 to t2.
The motion prediction process for video data for one frame is not completed only during the period from t8 to t9. Therefore, the pixel processing unit 20 temporarily stops the motion prediction process at t9, and performs the subsequent motion prediction process during the period of t10-t11 and t12-t13. As described above, the pixel processing unit 20 performs the motion processing of the video data for one frame in three times from t8 to t9, from t10 to t11, and from t12 to t13. The period from t10 to t11 is included in the same time period as the period from t3 to t4 or the period from t3 to t4. The period from t12 to t13 is the same as the period from t5 to t6 or from t5 to t6. Included in the period.

In this way, the pixel processing unit 20 performs the resize and motion prediction processing for the mobile terminal for each frame.
The frame rate of video data decoded by the decoding unit 10 is 30 frames / s, whereas the frame rate of video data for mobile terminals is 10 frames / s. Therefore, the pixel processing unit 20 performs frame thinning for the mobile terminal before resizing and motion prediction. Specifically, two of every three consecutive frames are discarded, and the remaining one is subjected to resizing and motion prediction processing for the mobile terminal.

The video data that has been subjected to the motion prediction processing by the pixel processing unit 20 is sequentially output to the re-encoding unit 30, subjected to discrete cosine transform and quantization, and variable-length encoded.
In the figure, the processing results in the periods t8-t9, t10-t11, t12-t13, which correspond to motion prediction processing for one frame of mobile terminal, are subjected to discrete cosine transform and quantization at any time after t14. The

The motion prediction process performed in the pixel processing unit 20 is a process that requires a reference frame. In order to obtain this reference frame, it is necessary to perform local decoding in which the re-encoding unit 30 decodes the discrete cosine transform and quantized frame again. Local decoding is a process including inverse quantization, inverse discrete cosine transform, and motion compensation.
Therefore, the transcoder 100 performs this local decoding by using the IQ unit 14, the IDCT unit 16, and the MC unit 18 of the decoding unit 10.

  The decoding unit 10 decodes the MPEG2 compressed video data for each frame at the timing shown in FIG. 3 so that the vertical resize for each frame is performed without delay in the pixel processing unit 20. Between the decoding of one frame and the next frame, for example, as shown at t15-t16 and t17-t18, idle time occurs corresponding to the vertical blanking period of the receiver. Therefore, local decoding indicated by t19-20 and t21-t22 is performed during this idle time.

Next, the resize / ME shared circuit 22 included in the pixel processing unit 20 will be described.
The resizing / ME shared circuit 22 is a circuit configured by combining a resizing circuit that performs an operation for resizing and a motion prediction circuit that performs an operation for motion prediction so as to share a common arithmetic unit. . For the description of this circuit, FIG. 4A shows a resize circuit, FIG. 4B shows a motion prediction circuit, and FIG. 4C shows a resize / ME shared circuit 22 combining them.

FIG. 4A shows a configuration diagram of the resizing circuit.
In the figure, the resizing circuit includes a selector 600, an adder 601, a multiplier 602, and cumulative adders 603 and 604. The selector 600 selects a filter coefficient used for multiplication and outputs it to the multiplier 602. The adder 601 adds adjacent pixels and outputs the result to the multiplier 602. Multiplier 602 multiplies the filter coefficient and the addition result. Cumulative adders 603 and 604 obtain the final calculation result of the resizing circuit by cumulatively adding the multiplication results.

FIG. 4B shows a configuration diagram of the motion prediction circuit.
In the figure, the motion prediction circuit includes a selector 605, a selector 614, a subtracter 606, and cumulative adders 607 and 608. The selector 605 selects a pixel in the reference image. The selector 614 selects a pixel in the image to be encoded. The subtractor 606 obtains a difference value between the pixel in the selected reference image and the pixel being encoded. Cumulative adders 607 and 608 perform cumulative addition of difference values.

FIG. 4C shows a configuration diagram of the resize / ME shared circuit 22 in which FIGS. 4A and 4B are combined.
In the figure, the resizing / ME shared circuit 22 includes a selector 609, a selector 615, an adder / subtractor 610, cumulative adders 611 and 612, and a multiplier 613. A selector is provided between the selector 609 and the adder / subtractor 610, and a selector is also provided between the multiplier 613 and the cumulative adders 611 and 612.

In this configuration, when the resizing / ME shared circuit 22 receives an instruction from the processor 40 to function as a resizing circuit, it operates as follows.
The selector 609 selects a filter coefficient used for multiplication and outputs it to the multiplier 613. The selector between the selector 609 and the adder / subtractor 610 selects the right input so that adjacent pixels are input to the adder / subtractor 610. The selector 615 causes adjacent pixels to be input to the adder / subtractor 610. The adder / subtractor 610 functions as an adder, adds adjacent pixels, and outputs the result to the multiplier 613. The multiplier 613 multiplies the filter coefficient and the addition result. The selector between the multiplier 613 and the cumulative adders 611 and 612 selects the left input, that is, the multiplication result is input to the cumulative adders 611 and 612. The cumulative adders 611 and 612 The final result of the resizing circuit is obtained by accumulating the multiplication results.

On the other hand, when the resize / ME shared circuit 22 receives an instruction from the processor 40 to function as a motion prediction circuit, it operates as follows.
A selector 609 selects a pixel in the reference image. The selector between the selector 609 and the adder / subtractor 610 selects the left input so that the selected pixel is input to the adder / subtractor 610. The selector 615 selects a pixel in the image to be encoded. The adder / subtractor 610 functions as a subtracter, and obtains a difference value between the selected pixel and the pixel being encoded. The selector between the multiplier 613 and the cumulative adders 611 and 612 selects the input on the right side, that is, the difference value is input to the cumulative adders 611 and 612. The cumulative adders 611 and 612 The cumulative addition of the difference values is performed.

  As described above, the transcoder 100 performs (1) resize for the receiver and resize for the mobile terminal by sharing one pixel processing unit 20 in a time division manner. (2) In addition, the transcoder 100 performs the resizing and motion prediction processing for the mobile terminal by sharing a circuit included in the pixel processing unit 20. (3) Further, the transcoder 100 performs decoding of MPEG2 compressed video data and local decoding required for motion prediction coding for mobile terminals by sharing the IQ unit 14, IDCT unit 16 and MC unit 18. Do this by dividing.

  By performing all or part of these, there is an effect that the configuration of the resizing circuit can be simplified.

  It is useful as a transcoder mechanism configured in a digital broadcast receiver or a DVD player.

It is a block diagram of the conventional transcoder. It is a block diagram of the transcoder of this embodiment. FIG. 4 is a diagram illustrating timing of each process of the transcoder 100. (A) is a block diagram of a resizing circuit.

(B) is a block diagram of a motion prediction circuit.
FIG. 6C is a configuration diagram of the resizing / ME shared circuit 22.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Decoding unit 12 VLD part 14 IQ part 16 IDCT part 18 MC part 20 Pixel processing unit 22 Resizing / ME shared circuit 30 Re-encoding unit 32 DCT part 34 Q part 36 VLC part 40 Processor 50 Resizing part I
60 Resizing part II
70 Re-encoding unit 80 Decoding unit 100 Transcoder 600 Selector 601 Adder 602 Multiplier 603, 604 Cumulative adder 605 Selector 606 Subtractor 607, 608 Cumulative adder 609 Selector 610 Adder / Subtractor 611, 612 Cumulative adder 613 Multiplier 614 selector 615 selector

Claims (6)

A moving image, which is a set of images, is resized to the first resolution required by the reproducing device and output to a reproducing device that reproduces moving images alternately by repeating a display period in which images are displayed and a non-display period in which images are not displayed. A transcoder,
A resizing unit for resizing a moving image into a moving image having a specified resolution;
A receiving unit for receiving encoded moving image data from the outside;
A decoding unit for decoding moving image data to obtain a moving image;
An encoding unit that encodes a moving image and newly generates moving image data;
The first resolution is designated for each image in the moving image as a result of receiving the moving image data by the receiving unit and decoding the decoding unit so that one image is displayed for each display period. Resizing is performed by the resizing unit, and between the resizing of each image, a second resolution lower than the first resolution is designated by the resizing unit, and each image in the moving image is resized. A control unit that causes the encoding unit to encode a moving image composed of each image obtained as a result of the resizing by specifying a second resolution ;
The resizing unit and the encoding unit are shared, and include a selector, an adder / subtracter, a multiplier, and a cumulative adder, each of which has an output value of the selector and an output value of the adder / subtracter. A shared circuit that is multiplied by the multiplier and connected so that a result of the multiplication or an output value of the adder / subtracter is input to the cumulative adder;
The resize part is
The selector performs selection of a filter coefficient, the adder / subtracter adds adjacent pixels constituting the image, the selected filter coefficient and the addition result of the pixels are multiplied by the multiplier, and the multiplication result Is resized by causing the cumulative adder to cumulatively add,
The encoding unit is
The selector is made to select pixels to be compared between successive images that form a moving image to be encoded, and the adder / subtracter performs subtraction between the selected pixels, and the difference value that is the subtraction result is A prediction error is calculated by causing a cumulative adder to perform cumulative addition, and a moving image is encoded based on the prediction error.
The result of encoding once is decoded using the decoding unit in a period other than the decoding period for resizing by specifying the first resolution, and the decoding result is used for calculating the prediction error. Transcoder characterized by. In the transcoder,
The moving image data that the control unit causes the receiving unit to receive is DCT and quantized,
The decoder
An inverse quantization unit that performs inverse quantization corresponding to the quantization for moving image data;
An inverse DCT unit that performs inverse DCT corresponding to the DCT for moving image data,
2. The transformer according to claim 1 , wherein decoding performed by the control unit to the decoding unit and decoding performed by the encoding unit to the decoding unit are processes including the inverse quantization and the inverse DCT. Coda. In the transcoder,
The transcoder according to claim 1, wherein the one display period is a period for displaying an image corresponding to one field. The first resolution is HDTV or SDTV size,
The transcoder according to claim 1, wherein the second resolution is a CIF size, a QVGA size, or a QCIF size. The resize unit further thins out the images constituting the moving image when the second resolution is specified and each image in the moving image is resized, and is set as a resize target. The transcoder according to 1. The transcoder according to claim 1, wherein the moving image is in an MPEG2 format.

Images