JP2005033136A - Method of designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid the occurrence of another wiring error and timing error as well as a large number of steps of correcting a layout, the errors and steps being caused by restricting parallel wiring on a net affected by a crosstalk, raising the type of a driving cell, and imposing a wiring constraint such as shield wiring and double-width and double-pitch wiring. <P>SOLUTION: A delay change caused by the crosstalk is conversely used for timing convergence. That is, by reversing all the logics of cells belonging to a net affected by the crosstalk or an affecting net, a signal transition is made backward in terms of time on the net affected by the crosstalk. Thus, a timing margin can be obtained in a path whose timing is made critical by the delay change caused by the crosstalk. Further, a layout can be corrected only by changing the type of the cells and thus it is possible to avoid an increase in the number of layout steps and prevent a layout correction from degrading the timing convergence. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and relates to a technique for improving a timing convergence problem caused by crosstalk.

  Along with the recent miniaturization of the process, as the width and pitch of the metal wiring become smaller, the crosstalk phenomenon caused by the delay variation due to the coupling capacitance in the adjacent parallel wiring tends to occur, which affects the timing convergence. .

  Conventionally, as a design flow for this crosstalk phenomenon, a layout method that does not generate crosstalk (see Patent Document 1) and a timing convergence method that considers delay variation due to crosstalk have been proposed.

  The layout method is a crosstalk avoidance method linked with an EDA (Electronic Design Automation) tool as described below.

Type-up of cells that drive nets affected by crosstalk Shield nets affected by crosstalk Suppress the wiring length of nets affected by crosstalk Increase the width and pitch of nets affected by crosstalk or The timing convergence method is a method of calculating a delay in consideration of a delay variation due to crosstalk and removing a timing error by a timing analysis using the result.
JP-A-10-308451 (page 3-5, FIG. 1-5)

  In the above-mentioned layout method for crosstalk countermeasures, not only will layout man-hours increase, but new layout errors (wiring violations), timing errors (timing violations), and crosstalk will be rejected by correcting the layout. There is a possibility of inducing the occurrence.

  Moreover, in the timing convergence method in the above-described crosstalk countermeasure, although the points to be corrected are narrowed down, the same problem as described above is still generated.

  The present invention solves the above-described conventional problems, suppresses an increase in man-hours related to layout correction as seen in the prior art, eliminates the need for repeated correction, and makes small and simple corrections in a short period of time. It aims to improve timing convergence by the method.

  In order to solve the above problems, the present invention takes the following measures. In other words, the delay variation due to crosstalk is actively used to improve timing.

  As a first solving means, the semiconductor integrated circuit design method according to the present invention provides a timing by causing the delay variation to occur in the opposite direction with respect to a portion where the delay varies due to crosstalk and adversely affects timing convergence. It is characterized by improvement.

  The above first solution can be described at a more specific level as follows.

  That is, a step of performing timing analysis without considering crosstalk after layout design, a step of performing timing analysis considering crosstalk, a step of comparing analysis results of the two timing analysis steps, and the comparison result A step of extracting a critical path affected by crosstalk, a step of searching for a net affected by crosstalk in the path extracted in the extraction step or a net affecting the crosstalk, and the influence of the crosstalk. A method for designing a semiconductor integrated circuit, comprising: inverting a logic of a cell belonging to a receiving net or a given net.

  The operation of the first solving means is as follows. In other words, when a crosstalk that causes delay variation in a timing that is more severe in terms of timing is given to a path that is severe in timing, the driver cell in one of both nets And the logic of the receiver cell is inverted. Specifically, the buffer is changed to an inverter, or the inverter is changed to a buffer. As a result, the slope of the waveform is reversed, and the time direction of the delay variation is reversed. As a result, the timing margin can be secured and the timing convergence can be improved. In the improvement of the timing convergence, it is possible to suppress an increase in the number of man-hours related to the layout correction seen in the prior art, and it becomes unnecessary to repeat the correction, and the timing convergence can be improved by a small and simple correction method in a short time.

  As a second solution, the semiconductor integrated circuit design method according to the present invention is the driver in the net affected by the crosstalk in order to control the delay variation to be improved in the first solution. The type of the driver cell in the cell and the net that affects the crosstalk is changed to an optimal combination.

  The second solution described above can be described at a more specific level as follows.

  That is, in the specific description of the first solving means, following the logical inversion step, the step of changing the type of the cell that belongs to the net affected by the crosstalk and the net belonging to the net affected by the crosstalk. It is what has.

  The operation of the second solving means is as follows. In other words, by increasing the type ratio or transition ratio of each driver cell between the net affected by the crosstalk and the net affected by the crosstalk, the influence of the crosstalk is increased to further improve the timing. be able to.

  As a third solution, a semiconductor integrated circuit design method according to the present invention allows a net routed in the vicinity of a critical path with a small timing margin or a path with a timing error to be wired in parallel to the critical path. The timing is improved by causing crosstalk.

  The third solution described above can be described at a more specific level as follows.

  That is, a step of performing timing analysis without considering crosstalk after layout design, a step of extracting a critical path or an error path from the timing analysis result, and a net that is susceptible to crosstalk in the extraction path is extracted. A step of extracting a net whose state transitions around the extracted net at a timing close to the extracted net, a step of wiring the two extracted nets in parallel, and a phase relationship between the two nets of the parallel wiring And a step of adjusting the phase relationship in a direction that helps timing convergence in delay variation due to crosstalk.

  The effect | action by the method of this 3rd solution means is as follows. That is, a target net that is easily affected by crosstalk is extracted from a critical path or a timing error path that is found by timing analysis, and a net that transitions at the same timing in the vicinity thereof is searched. Furthermore, crosstalk is generated by wiring the search net adjacent to the target net, and the logic of the cells in the net is inverted, thereby delay variation in the direction of improving timing. Further, the phase relationship between the two nets of the parallel wiring is examined, and the phase relationship is adjusted in a direction that helps timing convergence in the delay variation due to crosstalk. Specifically, when securing the setup timing, it is better to have an in-phase relationship between both nets, and when securing the hold timing, it is better to have an anti-phase relationship between both nets.

  By this method, it is possible to improve the timing convergence by applying the above method to three or more net groups by preferentially handling two nets in a state transition relationship. Can be extended.

  As described above, according to the present invention, a path whose timing convergence becomes critical due to the influence of crosstalk, or a net that affects the crosstalk or a net that is affected by a path where a timing error occurs. By inverting the logic of the cell to which it belongs, this crosstalk effect occurs in the opposite direction, and a timing margin is ensured for the path.

  As described above, the timing improvement method in the semiconductor integrated circuit design method according to the present invention has a crosstalk phenomenon for a path in which timing convergence becomes critical due to delay variation due to the influence of crosstalk or a timing error occurs. To improve timing. In other words, the timing improvement is made by actively utilizing the delay variation due to crosstalk.

  That is, according to the present invention, the signal transition is reversed without changing the circuit operation only by reversing the logic of the net affected by the crosstalk or the cell belonging to the net affected by the crosstalk. The timing improvement can be realized without increasing the number of layout steps and the need for repeated layout corrections.

  In addition, by using the basic concept of the present invention, a network that is easily affected by crosstalk can be applied to a critical path at a timing that is not affected by crosstalk or a path that has a timing error. If there is a network, search for a net that may be affected by crosstalk that is routed in the vicinity of the net, route both nets adjacent to each other, and if necessary, improve the timing as described above The method can be applied to improve timing using crosstalk. In other words, it is possible to improve the timing convergence by applying the above method to three or more net groups by preferentially dealing with two nets in a state transition relationship, thereby extending the application range. be able to.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor integrated circuit design method according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
A timing improvement method in the semiconductor integrated circuit design method according to the first embodiment of the present invention will be described.

  FIG. 1 is a circuit diagram (physical image) showing a configuration of a target circuit that performs timing improvement by applying the semiconductor integrated circuit design method according to the first embodiment of the present invention.

  In FIG. 1, A indicates a path in which timing convergence including a net affected by crosstalk is critical or a timing error (violation) occurs. In path A, 11A is a net affected by crosstalk, 12A is a driver cell of net 11A, 13A is a receiver cell of net 11A, 14A is a flip-flop that outputs a signal, 15A is a flip-flop that receives a signal, 16A Indicates a combinational circuit in the path, and 17A indicates a clock net for latching the path data. B is a part of the path that affects the cross A, the net 11B is a net that affects the net 11A, 12B is a driver cell of the net 11B, and 13B is a receiver cell of the net 11B. .

  FIG. 2 is a signal waveform diagram of paths A and B in FIG. 1 before the setup timing is improved under certain operating conditions. In FIG. 2, 21A is a signal waveform diagram of the net 11A, and 21B is a signal waveform diagram of the net 11B.

  FIG. 3 is a signal waveform diagram of paths A and B in FIG. 1 after the setup timing is improved under the same operating conditions as in FIG. In FIG. 3, 31A is a signal waveform diagram of the net 11A, and 31B is a signal waveform diagram of the net 11B.

  One example of the timing improvement method of the first embodiment in the circuit configuration as described above will be described below according to the flowchart of FIG.

  In step 41, layout design is performed, and then in step 42, timing analysis not considering the influence of crosstalk is performed, and in step 43, timing analysis considering crosstalk is performed. Next, at step 44, the timing analysis result at step 42 is compared with the timing analysis result at step 43. Next, at step 45, a path whose timing convergence is critical under the influence of crosstalk is extracted. Next, in step 46, the extracted net is searched for a net affected by the crosstalk and a net affecting the net.

  Then, either step 47 or step 48 is executed. In step 47, the logic of the cell belonging to the net having the influence of crosstalk is inverted. In step 48, the logic of the cell belonging to the net affected by the crosstalk is inverted. Specifically, the buffer is changed to an inverter, and the inverter is changed to a buffer.

  Now, assume that the net 11A in FIG. 1 is searched as a net affected by the crosstalk in steps 41 to 46, and the net 11B in FIG. 1 is searched as a net affecting the crosstalk.

  At this time, when the signal waveforms of the net 11A and the net 11B transition from the solid lines 21A and 21B to the dotted lines, respectively, the logic of the cells of the driver cell 12B and the receiver cell 13B is inverted. Thereby, the transition timing of the signal waveforms of the net 11A and the net 11B changes from the solid lines 31A and 31B to the dotted lines.

  Alternatively, the logic of the cell of the driver cell 12A and the receiver cell 13A is inverted with respect to the net 11A affected by the crosstalk as described above.

  By either of the above methods, the total delay value of the path A can be reduced, and as a result, the setup timing can be improved.

  The improvement method of the hold time can be realized by applying the same method in the above-described setup timing improvement method with the relationship between the signal waveforms in FIGS. 2 and 3 reversed.

(Embodiment 2)
A timing improvement method in the semiconductor integrated circuit design method according to the second embodiment of the present invention will be described. In the present embodiment, the cell type belonging to the target net is changed.

  FIG. 5 is a circuit diagram (physical image) showing a configuration of a target circuit that performs timing improvement by applying the semiconductor integrated circuit design method according to the second embodiment of the present invention. In FIG. 5, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components, and detailed description thereof will be omitted.

  One example of the timing improvement method according to the second embodiment will be described below in accordance with the flowchart of FIG.

  In FIG. 6, steps 41 to 48 are the same design flow as steps 41 to 48 in FIG. In step 49, the logic inversion is performed following the step 47 of inverting the logic of cells included in the net affected by the crosstalk, or the step 48 of inverting the logic of the cells included in the net affected by the crosstalk. In order to increase the influence level of the later crosstalk and improve the timing, the driver cell 12B and the receiver cell 13A in FIG. 5 are typed up, and the driver cell 12A and the receiver cell 13B are typed down. Instead of adjusting the type ratio, the transition ratio may be adjusted.

  Thereby, the absolute value of the delay fluctuation value due to crosstalk can be increased, and further timing improvement can be realized.

(Embodiment 3)
A timing improvement method in the semiconductor integrated circuit design method according to the third embodiment of the present invention will be described.

  FIG. 7 is a circuit diagram (physical image) showing a configuration of a target circuit that performs timing improvement by applying the semiconductor integrated circuit design method according to the third embodiment of the present invention. FIG. 7A is a circuit diagram in a state before timing improvement, and FIG. 7B is a circuit diagram in a state after timing improvement. In FIG. 7, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components, and detailed description thereof will be omitted.

  In FIG. 7, A is a path whose timing convergence is critical or a part of a path where a timing error has occurred, and 61A represents a net that is susceptible to crosstalk. In the path B, 61B indicates a net before timing improvement in which state transition is performed at the same timing as the net 61A, and 62B indicates a net after timing improvement. Paths C and D are part of a path including a net wired adjacent to the net 61A, 61C and 61D indicate nets before timing improvement, and 62C and 62D indicate nets after timing improvement, respectively.

  One example of the timing improvement method of the third embodiment in the circuit configuration as described above will be described below according to the flowchart of FIG.

  In step 71, layout design is performed. In step 72, timing analysis is performed without considering the influence of crosstalk. In step 73, a path or timing error in which timing convergence becomes critical based on the timing analysis result. Extract the path where the is occurring. Next, in step 74, a net of a long wiring affected by or possibly affected by crosstalk is extracted in the extracted path. Next, in step 75, a net wired around the extracted net is searched, and a net whose state transition is relatively close to the extracted net is extracted.

Next, in step 76, the route is changed so that the net extracted in step 74 and the net extracted in step 75 are adjacently wired in parallel. Next, in step 77, the phase relationship between the nets is checked,
The phase relationship is adjusted in a direction that helps timing convergence in delay variation due to crosstalk.

  If the setup timing is to be secured, if the phase relationship is reversed, the process proceeds to step 78, and the phase is changed to the same phase (rises or falls) according to the flow of FIG.

  If the net extracted in step 74 is the net 61A in FIG. 7 and the candidate net searched in step 75 is the net 61B in FIG. 7, when securing the setup timing of the path A, the net 61A and the net 62B are In order to perform adjacent parallel wiring, the route is changed from the net 61B in FIG. 7A to the net 62B in FIG. 7B, and accordingly, the net 61C in FIG. 7A is changed to the net 62C in FIG. 7B. 7A, the net 61D in FIG. 7A changes to the net 62D in FIG. 7B.

  Further, the phase relationship between the net 61A and the net 62B is checked, and if the phase relationship is reversed, the phase is changed to the same phase (rising or falling) according to the flow of FIG.

  Similarly, when securing the hold timing, the net 61A and the net 62B are changed to opposite phases (rising and falling, or falling and rising).

  With these methods, the timing variation is actively utilized by making use of the delay variation due to crosstalk, so that the timing margin can be secured without directly sacrificing the wiring resources.

1 is a circuit diagram showing a configuration of a target circuit for improving timing by applying a method for designing a semiconductor integrated circuit according to Embodiment 1 of the present invention; In the first embodiment of the present invention, a signal state transition diagram when a net affected by crosstalk and a given net are in phase In the first embodiment of the present invention, a signal state transition diagram when a net affected by crosstalk and a given net are in phase Design flow diagram for improving timing using the influence of crosstalk in the method of designing a semiconductor integrated circuit according to the first embodiment of the present invention The circuit diagram which shows the structure of the object circuit which improves a timing by applying the design method of the semiconductor integrated circuit in Embodiment 2 of this invention Design flow diagram for improving timing by using occurrence of crosstalk and optimizing cell type change in Embodiment 2 of the present invention The circuit diagram which shows the structure of the object circuit which improves a timing by applying the design method of the semiconductor integrated circuit in Embodiment 3 of this invention Design flow diagram for improving timing by generating crosstalk in Embodiment 3 of the present invention

Explanation of symbols

11A, 61A Net affected by crosstalk 11B, 61B Net affected by crosstalk 12A, 13A Cell belonging to net 11A 12B, 13B Cell belonging to net 11B 14A, 15A Flip-flop on critical path 16A On critical path Combination circuit 17A Clock nets 21A, 31A for latching critical path signals Waveform diagram including fluctuation due to crosstalk of net 11A 21B, 31B Waveform diagram of net 11B

Claims (6)

In a method of designing a semiconductor integrated circuit, the timing is improved by causing the delay variation to occur in the opposite direction with respect to a portion where the delay varies due to crosstalk and adversely affects timing convergence. Design method. A process of performing timing analysis without considering crosstalk after layout design,
A process of performing timing analysis in consideration of crosstalk;
Comparing the analysis results of the two timing analysis steps;
Extracting a critical path affected by crosstalk from the comparison result;
Searching for a net affected by crosstalk or a net affecting the crosstalk in the path extracted in the extraction step;
A method of designing a semiconductor integrated circuit, comprising: inverting a logic of a net affected by the crosstalk or a cell belonging to the given net. Further, in order to control the delay variation to be improved, the driver cell in the net affected by the crosstalk and the type of the driver cell in the net affected by the crosstalk are changed to an optimum combination. The method for designing a semiconductor integrated circuit according to claim 1. 3. The method of designing a semiconductor integrated circuit according to claim 2, further comprising a step of changing a type of a cell belonging to the net affected by the crosstalk and a net affected by the crosstalk after the logic inversion step. . A semiconductor integrated circuit characterized in that for a critical path with a small timing margin or a path with a timing error, a net routed in the vicinity of the path is wired in parallel to the critical path and crosstalk is caused to improve timing. Circuit design method. A process of performing timing analysis without considering crosstalk after layout design,
Extracting a critical path or an error path from the timing analysis result;
Extracting a net susceptible to crosstalk within the extraction path;
Extracting a net that makes a state transition around the extracted net at a timing close to the extracted net;
A step of wiring the two extraction nets in parallel;
A method of designing a semiconductor integrated circuit, comprising: examining a phase relationship between two nets of the parallel wiring and adjusting the phase relationship in a direction that helps timing convergence in a delay variation due to crosstalk.

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