JP2005032975A - Semiconductor device and method of measuring same - Google Patents

Semiconductor device and method of measuring same Download PDF

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Publication number
JP2005032975A
JP2005032975A JP2003196296A JP2003196296A JP2005032975A JP 2005032975 A JP2005032975 A JP 2005032975A JP 2003196296 A JP2003196296 A JP 2003196296A JP 2003196296 A JP2003196296 A JP 2003196296A JP 2005032975 A JP2005032975 A JP 2005032975A
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Prior art keywords
semiconductor device
pad
pad portion
semiconductor
conductor
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JP2003196296A
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Japanese (ja)
Inventor
Hidekatsu Muroi
英勝 室井
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP2003196296A priority Critical patent/JP2005032975A/en
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is smaller in size and lower in price than that requesting a pad for grounding to the conventional pad for radio frequency, and also to provide a method of measuring the same. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate 1 on which a plurality of chip regions 3 including a semiconductor chip 2 are allocated, a scribe region 4 provided between chip regions 3, and a conductive material 5 provided in this scribe region 4. This semiconductor chip 2 includes, in the same side as the forming surface of conductor material 5 provided on the semiconductor substrate 1, at least a first pad 2a for the grounding and a second pad 2b for radio frequency. Since the first pad 2a is electrically connected to the conductor material 5, the conventional second pad is no longer required. Accordingly, a small size and low price semiconductor device can be obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は種々の電子機器等に使用して好適な半導体装置、及びその測定方法に関する。
【0002】
【従来の技術】
従来の半導体装置、及びその測定方法の図面を説明すると、図5は従来の半導体装置の平面図、図6は従来の半導体装置に係る要部の拡大平面図、図7は従来の半導体装置の測定方法を説明するための説明図である。
【0003】
次に、従来の半導体装置の構成を図5,図6に基づいて説明すると、ウエハーからなる平板状の半導体基板51は、複数個の半導体チップ52と、この半導体チップ52を有し、マトリックス状に配設された複数個のチップ領域53と、このチップ領域53間に設けられ、個々の半導体チップ52を形成するためのスクライブ領域54と、このスクライブ領域54に格子状に形成された導電体55を有する。(例えば、特許文献1参照)
【0004】
そして、従来の半導体装置は、スクライブ領域54に導電体55を設けると共に、この半導体55を接地することによって、製造時における半導体チップ52に対する静電破壊を防止するようにしたものである。
【0005】
また、従来の半導体装置の個々の半導体チップ52は、図6に示すように、半導体基板51に設けられた導電体55の形成面と同一側において形成された複数個のパッド部Pを有する。
【0006】
この複数個のパッド部Pは、回路基板(図示せず)に接続される複数個の接地用の第1のパッド部Paと、回路基板(図示せず)に接続不要、或いは接続されない複数個の接地用の第2のパッド部Pbと、回路基板(図示せず)に接続され、第2のパッド部Pbと隣り合わせに配置された高周波用の第3のパッド部Pcと、回路基板(図示せず)に接続されるそれ以外の複数個の第4のパッド部Pdを有する。
【0007】
このような構成を有する従来の半導体装置は、半導体基板51がスクライブ領域54に沿って切断されることによって、互いに分離された個々の半導体チップ52が製造され、この分離された半導体チップ52が電子機器の回路基板に搭載されるようになっている。
【0008】
次に、従来の半導体装置の測定方法を図7に基づいて説明すると、先ず、パッド部P、及び導電体55を上方にした状態で、半導体基板51がテーブル(支持台)(図示せず)上に支持される。
【0009】
次に、測定装置(図示せず)に接続されたプローブ56には、2個のピン状の接触部56a、56bが設けられ、このプローブ56が矢印A方向に移動されて、プローブ56を半導体基板51上に移動し、一方の接触部56aを第3のパッド部Pcに接触させると共に、他方の接触部56bを第2のパッド部Pbに接触させて、高周波の電気的特性を測定するようになっている。
【0010】
また、プローブ56の接触部56a、56bが隣り合う第4のパッド部Pd間に接触させ、この状態で測定すると、低周波等の電気的特性が測定できるようになっている。
【0011】
即ち、従来の半導体装置、及びその測定方法においては、接地用の第1のパッド部Paの他に、高周波用の第3のパッド部Pcに隣り合う接地用の第2のパッド部Pbを必要とし、従って、半導体装置が大型になるばかりか、余分な接地用の第2のパッド部Pbを形成せねばならず、半導体装置の製造がコスト高になるものである。
【0012】
【特許文献1】
特開平5−109641号公報
【0013】
【発明が解決しようとする課題】
従来の半導体装置、及びその測定方法においては、接地用の第1のパッド部Paの他に、高周波用の第3のパッド部Pcに隣り合う接地用の第2のパッド部Pbを必要とし、従って、半導体装置が大型になるばかりか、余分な接地用の第2のパッド部Pbを形成せねばならず、半導体装置の製造がコスト高になるという問題がある。
【0014】
そこで、本発明は小型で、安価な半導体装置、及びその測定方法を提供することを目的とする。
【0015】
【課題を解決するための手段】
上記課題を解決するための第1の解決手段として、半導体チップを有したチップ領域が複数個配設された半導体基板と、前記チップ領域間に設けられたスクライブ領域と、このスクライブ領域に設けられた導電体とを備え、前記半導体チップは、前記半導体基板に設けられた前記導電体の形成面と同一側において、少なくとも接地用の第1のパッド部と、高周波用の第2のパッド部を有し、前記第1のパッド部が前記導電体に電気的に接続された構成とした。
【0016】
また、第2の解決手段として、前記チップ領域がマトリックス状に配設された構成とした。
また、第3の解決手段として、前記第1のパッド部が前記第2のパッド部の隣部から離れた位置に設けられた構成とした。
【0017】
また、第4の解決手段として、半導体装置と、少なくとも2個の接触部を有したプローブとを備え、前記導電体が接地された状態で、前記接触部の一方を前記導電体に接触すると共に、前記接触部の他方を前記第2のパッド部に接触させるようにした測定方法とした。
【0018】
【発明の実施の形態】
本発明の半導体装置、及びその測定方法の図面を説明すると、図1は本発明の半導体装置の平面図、図2は本発明の半導体装置に係る要部の拡大平面図、図3は本発明の半導体装置の測定方法の第1実施例を示し、測定方法を説明するための説明図、図4は本発明の半導体装置の測定方法の第2実施例を示し、測定方法を説明するための説明図である。
【0019】
次に、本発明の半導体装置の構成を図1,図2に基づいて説明すると、ウエハーからなる平板状の半導体基板1は、複数個の半導体チップ2と、この半導体チップ2を有し、マトリックス状に配設された複数個のチップ領域3と、このチップ領域3間に設けられ、個々の半導体チップ2を形成するためのスクライブ領域4と、このスクライブ領域4に格子状に形成された導電体5を有する。
【0020】
また、半導体チップ2は、回路基板(図示せず)に接続される複数個の接地用の第1のパッド部2aと、回路基板(図示せず)に接続され、第1のパッド部2aから離れた位置(隣り合わせでない位置)に配置された高周波用の第2のパッド部2bと、回路基板(図示せず)に接続されるそれ以外の複数個の第3のパッド部2cを有する。
【0021】
また、第1,第2,第3のパッド部2a、2b、2cは、図2に示すように、半導体基板1に設けられた導電体5の形成面と同一側において形成され、第1のパッド部2aは、導電体5と電気的に接続されて、導電体5を介して接地可能となっている。
【0022】
そして、本発明の半導体装置は、スクライブ領域4に導電体5を設けると共に、この半導体5を接地することによって、製造時における半導体チップ2に対する静電破壊を防止するようになっている。
【0023】
このような構成を有する本発明の半導体装置は、半導体基板1がスクライブ領域4に沿って切断されることによって、互いに分離された個々の半導体チップ2が製造され、この分離された半導体チップ2が電子機器の回路基板に搭載されるようになっている。
【0024】
次に、本発明の半導体装置の測定方法の第1実施例を図3に基づいて説明すると、先ず、第1,第2,第3のパッド部2a、2b、2c、及び導電体5を上方にした状態で、半導体基板1がテーブル(支持台)(図示せず)上に支持されると共に、導電体5を接地した状態にする。
【0025】
次に、測定装置(図示せず)に接続されたプローブ6には、異なる長さを有し、矢印A方向に対して前後に配置された2個のピン状の接触部6a、6bが設けられ、このプローブ6が矢印A方向に移動されて、プローブ6が半導体基板1上に移動し、一方の長い接触部6aを第2のパッド部2bに接触させると共に、他方の短い接触部6bを導電体5に接触させる。
【0026】
すると、接触部6bは、導電体5を介して接地用の第1のパッド部2aに導通すると共に、接地状態にある導電体5を介して接触部6bが接地された状態となって、高周波の電気的特性を測定するようになっている。
【0027】
また、プローブ6の接触部6a、6bが隣り合う第3のパッド部2c間に接触させ、この状態で測定すると、低周波等の電気的特性が測定できるようになっている。
【0028】
即ち、本発明の半導体装置、及びその測定方法においては、接地用の導電体5を設けるだけで良く、従来のように、高周波用の第3のパッド部Pcに隣り合う接地用の第2のパッド部Pbを必要とするものに比して、半導体装置を小型化できるばかりか、半導体装置の製造が安価になるものである。
【0029】
また、本発明は、接地用の第1のパッド部2aがパッド部配列中のいかなる位置おいても、容易に導電体5に接続できて、且つ、容易に高周波の電気的特性を測定することができる。
【0030】
また、図4は本発明の半導体装置の測定方法の第2実施例を示し、この第2実施例は、前記第1実施例と接触部6a、6bの構成を異にするが、その他の構成は、前記第1実施例と同様であり、同一部品に同一番号を付し、ここではその説明を省略する。
【0031】
即ち、第2実施例におけるプローブ6は、接触部6a、6bが同じ長さで形成され、矢印A方向に対して前部に配置された接触部6aが第2のパッド部2bに接触すると共に、後部に位置する接触部6bが導電体5に接触するようにしたものである。
【0032】
なお、上記実施例では、半導体チップ2,及びチップ領域3がマトリックス状に配設されたもので説明したが、半導体チップ2,及びチップ領域3がマトリックス状以外の形状に配設されたものでも良いこと勿論である。
【0033】
【発明の効果】
本発明の半導体装置は、半導体チップを有したチップ領域が複数個配設された半導体基板と、チップ領域間に設けられたスクライブ領域と、このスクライブ領域に設けられた導電体とを備え、半導体チップは、半導体基板に設けられた導電体の形成面と同一側において、少なくとも接地用の第1のパッド部と、高周波用の第2のパッド部を有し、第1のパッド部が導電体に電気的に接続されたため、従来の第2のパッド部が不要となり、従って、小型で、安価な半導体装置を提供できる。
【0034】
また、チップ領域がマトリックス状に配設されたため、多数の半導体チップが同時に形成できて、生産性の良好なものが得られる。
【0035】
また、第1のパッド部が第2のパッド部の隣部から離れた位置に設けられたため、接地用の第1のパッド部がパッド部配列中のいかなる位置おいても、容易に導電体に接続できて、且つ、容易に高周波の電気的特性を測定することができる半導体装置を提供できる。
【0036】
また、半導体装置と、少なくとも2個の接触部を有したプローブとを備え、導電体が接地された状態で、接触部の一方を導電体に接触すると共に、接触部の他方を第2のパッド部に接触させるようにしたため、接地用の第1のパッド部がパッド部配列中のいかなる位置おいても、容易に導電体に接続できて、且つ、容易に高周波の電気的特性を測定することができる測定方法を提供できる。
【図面の簡単な説明】
【図1】本発明の半導体装置の平面図。
【図2】本発明の半導体装置に係る要部の拡大平面図。
【図3】本発明の半導体装置の測定方法の第1実施例を示し、測定方法を説明するための説明図。
【図4】本発明の半導体装置の測定方法の第2実施例を示し、測定方法を説明するための説明図。
【図5】従来の半導体装置の平面図。
【図6】従来の半導体装置に係る要部の拡大平面図。
【図7】従来の半導体装置の測定方法を説明するための説明図。
【符号の説明】
1 半導体基板
2 半導体チップ
2a 第1のパッド部
2b 第2のパッド部
2c 第3のパッド部
3 チップ領域
4 スクライブ領域
5 導電体
6 プローブ
6a 接触部
6b 接触部
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device suitable for use in various electronic devices and a measuring method thereof.
[0002]
[Prior art]
FIG. 5 is a plan view of a conventional semiconductor device, FIG. 6 is an enlarged plan view of a main part of the conventional semiconductor device, and FIG. 7 is a diagram of the conventional semiconductor device. It is explanatory drawing for demonstrating the measuring method.
[0003]
Next, the configuration of a conventional semiconductor device will be described with reference to FIGS. 5 and 6. A flat semiconductor substrate 51 made of a wafer includes a plurality of semiconductor chips 52 and the semiconductor chips 52, and is in a matrix form. A plurality of chip regions 53 disposed in the chip region, scribe regions 54 provided between the chip regions 53 for forming the individual semiconductor chips 52, and conductors formed in a lattice shape in the scribe regions 54 55. (For example, see Patent Document 1)
[0004]
In the conventional semiconductor device, a conductor 55 is provided in the scribe region 54, and the semiconductor 55 is grounded to prevent electrostatic breakdown of the semiconductor chip 52 during manufacture.
[0005]
Moreover, each semiconductor chip 52 of the conventional semiconductor device has a plurality of pad portions P formed on the same side as the surface of the conductor 55 provided on the semiconductor substrate 51 as shown in FIG.
[0006]
The plurality of pad portions P include a plurality of grounding first pad portions Pa connected to a circuit board (not shown) and a plurality of pad parts P which are not required to be connected to the circuit board (not shown). The second pad portion Pb for grounding, the third pad portion Pc for high frequency connected to the circuit board (not shown) and arranged adjacent to the second pad portion Pb, and the circuit board (FIG. A plurality of fourth pad portions Pd other than that connected to (not shown).
[0007]
In the conventional semiconductor device having such a configuration, the semiconductor substrate 51 is cut along the scribe region 54 to produce individual semiconductor chips 52 separated from each other. It is mounted on the circuit board of equipment.
[0008]
Next, a conventional method for measuring a semiconductor device will be described with reference to FIG. 7. First, the semiconductor substrate 51 is placed on a table (support) (not shown) with the pad portion P and the conductor 55 facing upward. Supported on top.
[0009]
Next, the probe 56 connected to the measuring device (not shown) is provided with two pin-like contact portions 56a and 56b, and the probe 56 is moved in the direction of arrow A, and the probe 56 is moved to the semiconductor. Moving on the substrate 51, one contact portion 56a is brought into contact with the third pad portion Pc, and the other contact portion 56b is brought into contact with the second pad portion Pb so as to measure high-frequency electrical characteristics. It has become.
[0010]
Further, when the contact portions 56a and 56b of the probe 56 are brought into contact between the adjacent fourth pad portions Pd and measured in this state, electrical characteristics such as a low frequency can be measured.
[0011]
That is, in the conventional semiconductor device and the measuring method thereof, in addition to the first pad portion Pa for grounding, the second pad portion Pb for grounding adjacent to the third pad portion Pc for high frequency is necessary. Therefore, not only the semiconductor device becomes large, but also an extra second pad portion Pb for grounding has to be formed, which increases the manufacturing cost of the semiconductor device.
[0012]
[Patent Document 1]
JP-A-5-109641 [0013]
[Problems to be solved by the invention]
In the conventional semiconductor device and the measuring method thereof, in addition to the first pad portion Pa for grounding, the second pad portion Pb for grounding adjacent to the third pad portion Pc for high frequency is required. Accordingly, there is a problem that not only the semiconductor device becomes large, but also the extra second pad portion Pb for grounding has to be formed, and the manufacturing cost of the semiconductor device becomes high.
[0014]
Therefore, an object of the present invention is to provide a small and inexpensive semiconductor device and a measuring method thereof.
[0015]
[Means for Solving the Problems]
As a first means for solving the above problems, a semiconductor substrate having a plurality of chip regions each having a semiconductor chip, a scribe region provided between the chip regions, and a scribe region. The semiconductor chip has at least a first pad portion for grounding and a second pad portion for high frequency on the same side as the surface of the conductor provided on the semiconductor substrate. And the first pad portion is electrically connected to the conductor.
[0016]
As a second solution, the chip regions are arranged in a matrix.
As a third solution, the first pad portion is provided at a position away from the adjacent portion of the second pad portion.
[0017]
As a fourth solution, a semiconductor device and a probe having at least two contact portions are provided, and one of the contact portions is in contact with the conductor in a state where the conductor is grounded. The measurement method is such that the other of the contact portions is brought into contact with the second pad portion.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a plan view of a semiconductor device of the present invention, FIG. 2 is an enlarged plan view of a main part of the semiconductor device of the present invention, and FIG. 3 is a diagram of the present invention. FIG. 4 shows a first embodiment of the semiconductor device measurement method of the present invention, and is an explanatory diagram for explaining the measurement method. FIG. 4 shows a second embodiment of the semiconductor device measurement method of the present invention, for explaining the measurement method. It is explanatory drawing.
[0019]
Next, the configuration of the semiconductor device of the present invention will be described with reference to FIGS. 1 and 2. A flat semiconductor substrate 1 made of a wafer includes a plurality of semiconductor chips 2 and the semiconductor chips 2, and a matrix. A plurality of chip regions 3 arranged in a shape, a scribe region 4 provided between the chip regions 3 for forming individual semiconductor chips 2, and a conductive material formed in a lattice shape in the scribe region 4 It has a body 5.
[0020]
The semiconductor chip 2 is connected to a plurality of grounding first pad portions 2a connected to a circuit board (not shown) and to the circuit board (not shown). It has a second pad portion 2b for high frequency disposed at a distant position (a position not adjacent to each other) and a plurality of third pad portions 2c other than that connected to a circuit board (not shown).
[0021]
Further, as shown in FIG. 2, the first, second, and third pad portions 2a, 2b, and 2c are formed on the same side as the surface on which the conductor 5 provided on the semiconductor substrate 1 is formed. The pad portion 2 a is electrically connected to the conductor 5 and can be grounded via the conductor 5.
[0022]
In the semiconductor device of the present invention, the conductor 5 is provided in the scribe region 4 and the semiconductor 5 is grounded to prevent electrostatic breakdown of the semiconductor chip 2 during manufacturing.
[0023]
In the semiconductor device of the present invention having such a configuration, the semiconductor substrate 1 is cut along the scribe region 4 to produce individual semiconductor chips 2 separated from each other. It is mounted on the circuit board of electronic equipment.
[0024]
Next, a first embodiment of the semiconductor device measurement method of the present invention will be described with reference to FIG. 3. First, the first, second, and third pad portions 2a, 2b, and 2c, and the conductor 5 are moved upward. In this state, the semiconductor substrate 1 is supported on a table (support) (not shown) and the conductor 5 is grounded.
[0025]
Next, the probe 6 connected to the measuring device (not shown) is provided with two pin-like contact portions 6a and 6b having different lengths and arranged in the front-rear direction with respect to the arrow A direction. The probe 6 is moved in the direction of arrow A, and the probe 6 is moved onto the semiconductor substrate 1 to bring one long contact portion 6a into contact with the second pad portion 2b and the other short contact portion 6b. Contact the conductor 5.
[0026]
Then, the contact portion 6b is electrically connected to the first pad portion 2a for grounding via the conductor 5, and the contact portion 6b is grounded via the conductor 5 in the grounded state. It is designed to measure the electrical characteristics.
[0027]
Further, when the contact parts 6a and 6b of the probe 6 are brought into contact between the adjacent third pad parts 2c and measured in this state, electrical characteristics such as low frequency can be measured.
[0028]
That is, in the semiconductor device and the measuring method thereof according to the present invention, it is only necessary to provide the grounding conductor 5, and the grounding second pad adjacent to the third pad portion Pc for high frequency is provided as in the prior art. The semiconductor device can be reduced in size as compared with the one requiring the pad portion Pb, and the semiconductor device can be manufactured at low cost.
[0029]
Further, according to the present invention, the first pad portion 2a for grounding can be easily connected to the conductor 5 at any position in the pad portion arrangement, and easily measure high-frequency electrical characteristics. Can do.
[0030]
FIG. 4 shows a second embodiment of the method for measuring a semiconductor device according to the present invention. This second embodiment differs from the first embodiment in the configuration of the contact portions 6a and 6b, but the other configurations. Is the same as that of the first embodiment, and the same reference numerals are given to the same parts, and the description thereof is omitted here.
[0031]
That is, in the probe 6 in the second embodiment, the contact portions 6a and 6b are formed with the same length, and the contact portion 6a disposed at the front portion with respect to the direction of the arrow A contacts the second pad portion 2b. The contact portion 6b located at the rear is in contact with the conductor 5.
[0032]
In the above embodiment, the semiconductor chip 2 and the chip region 3 are described as being arranged in a matrix. However, the semiconductor chip 2 and the chip region 3 may be arranged in a shape other than the matrix. Of course it is good.
[0033]
【The invention's effect】
A semiconductor device according to the present invention includes a semiconductor substrate on which a plurality of chip regions each having a semiconductor chip are disposed, a scribe region provided between the chip regions, and a conductor provided in the scribe region. The chip has at least a first pad portion for grounding and a second pad portion for high frequency on the same side as a conductor forming surface provided on a semiconductor substrate, and the first pad portion is a conductor. Therefore, the conventional second pad portion is unnecessary, and thus a small and inexpensive semiconductor device can be provided.
[0034]
Further, since the chip regions are arranged in a matrix, a large number of semiconductor chips can be formed at the same time, and a product with good productivity can be obtained.
[0035]
In addition, since the first pad portion is provided at a position away from the adjacent portion of the second pad portion, the first pad portion for grounding can be easily formed into a conductor at any position in the pad portion array. A semiconductor device that can be connected and can easily measure high-frequency electrical characteristics can be provided.
[0036]
In addition, a semiconductor device and a probe having at least two contact portions are provided, and in a state where the conductor is grounded, one of the contact portions is in contact with the conductor, and the other of the contact portions is a second pad. Since the first pad portion for grounding can be easily connected to the conductor at any position in the pad portion arrangement, the high-frequency electrical characteristics can be easily measured. It is possible to provide a measurement method capable of
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device of the present invention.
FIG. 2 is an enlarged plan view of a main part according to the semiconductor device of the present invention.
FIG. 3 is an explanatory view for explaining the measurement method according to the first embodiment of the measurement method of the semiconductor device of the present invention.
FIG. 4 is an explanatory diagram for explaining a measuring method according to a second embodiment of the measuring method of the semiconductor device of the present invention.
FIG. 5 is a plan view of a conventional semiconductor device.
FIG. 6 is an enlarged plan view of a main part of a conventional semiconductor device.
FIG. 7 is an explanatory diagram for explaining a conventional method for measuring a semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Semiconductor chip 2a 1st pad part 2b 2nd pad part 2c 3rd pad part 3 Chip area 4 Scribe area 5 Conductor 6 Probe 6a Contact part 6b Contact part

Claims (4)

半導体チップを有したチップ領域が複数個配設された半導体基板と、前記チップ領域間に設けられたスクライブ領域と、このスクライブ領域に設けられた導電体とを備え、前記半導体チップは、前記半導体基板に設けられた前記導電体の形成面と同一側において、少なくとも接地用の第1のパッド部と、高周波用の第2のパッド部を有し、前記第1のパッド部が前記導電体に電気的に接続されたことを特徴とする半導体装置。A semiconductor substrate including a plurality of chip regions each having a semiconductor chip, a scribe region provided between the chip regions, and a conductor provided in the scribe region, wherein the semiconductor chip includes the semiconductor On the same side as the conductor forming surface provided on the substrate, at least a first pad portion for grounding and a second pad portion for high frequency are provided, and the first pad portion serves as the conductor. A semiconductor device which is electrically connected. 前記チップ領域がマトリックス状に配設されたことを特徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the chip regions are arranged in a matrix. 前記第1のパッド部が前記第2のパッド部の隣部から離れた位置に設けられたことを特徴とする請求項1、又は2記載の半導体装置。3. The semiconductor device according to claim 1, wherein the first pad portion is provided at a position away from an adjacent portion of the second pad portion. 請求項1から3の何れかに記載の半導体装置と、少なくとも2個の接触部を有したプローブとを備え、前記導電体が接地された状態で、前記接触部の一方を前記導電体に接触すると共に、前記接触部の他方を前記第2のパッド部に接触させるようにしたことを特徴とする半導体装置の測定方法。A semiconductor device according to any one of claims 1 to 3 and a probe having at least two contact portions, wherein one of the contact portions is in contact with the conductor while the conductor is grounded. And a method of measuring a semiconductor device, wherein the other of the contact portions is brought into contact with the second pad portion.
JP2003196296A 2003-07-14 2003-07-14 Semiconductor device and method of measuring same Withdrawn JP2005032975A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012079062A (en) * 2010-09-30 2012-04-19 Toshiba Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012079062A (en) * 2010-09-30 2012-04-19 Toshiba Corp Information processor

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