JP2005026390A - Signal wiring connection method of semiconductor integrated circuit device, signal wiring connection system, and process for fabricating semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for arranging necessary and sufficient via cuts for signal wiring formed on each different wiring layer and interconnected through vias. <P>SOLUTION: For signal wiring formed on each different wiring layer in order to interconnect a first logic element and a second logic element arranged on a semiconductor integrated circuit and interconnected through vias, timing analysis is performed between the first logic element and the second logic element (S02), an a decision is made whether a signal propagation delay time satisfies a specified reference value or not (S03, S04). If that reference value is not satisfied, the number of via cuts is increased to satisfy that reference value (S05). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to signal wiring of a semiconductor integrated circuit, and in particular, in order to connect logic elements to each other, necessary and sufficient via cutting is performed on signal wirings formed in different wiring layers and connected to each other through vias. The present invention relates to a signal wiring connection method suitable for placement, a signal wiring connection system, and a method for manufacturing a semiconductor integrated circuit device.
[0002]
[Prior art]
In recent years, along with the higher integration and higher performance of semiconductor integrated circuit devices, pattern miniaturization and multi-layered signal wiring are rapidly progressing, and the signal propagation delay time between logic elements is controlled to the optimum timing. In addition, there is a demand for a signal wiring connection method that can suppress electromigration.
[0003]
In the conventional semiconductor integrated circuit device, the signal wirings respectively formed in the first wiring layer and the second wiring layer are connected to each other through one via cut.
[0004]
However, since the contact area between the signal wiring of the first layer and the signal wiring of the second layer is small, the electrical resistance at the via connection portion is large, and there is a problem that the signal propagation delay time becomes large in the signal wiring passing through many vias. It was.
[0005]
On the other hand, a method of connecting the first-layer signal wiring and the second-layer signal wiring through a plurality of vias is known (for example, see Patent Document 1).
[0006]
The signal wiring connection method disclosed in Patent Document 1 will be described with reference to the drawings. 11A is a plan view showing the main part of the via, and FIG. 11B is a cross-sectional view taken along the line CC in FIG. 11A and viewed in the direction of the arrow.
[0007]
As shown in FIG. 11, the first-layer signal wiring 113 and the second-layer signal wiring 114 are electrically connected to each other by two via cuts 115 and 116 via an interlayer insulating film 112 on a semiconductor substrate 111. . Due to the two via cuts 115 and 116, the contact area between the first layer signal wiring 113 and the second layer signal wiring 114 is doubled as compared to one via cut. Thereby, the electric resistance of the signal wiring is reduced, and the signal propagation delay time is improved.
[0008]
However, although Patent Document 1 discloses that increasing the number of via cuts reduces the electrical resistance of the connection portion, there is no connection method for signal wiring between logic elements that require complicated timing control. Not disclosed.
[0009]
For example, the signal propagation delay time between logic elements includes a setup time that requires a signal to propagate within a predetermined time and a hold time during which a signal must not propagate within a predetermined time. Both of these must be met.
[0010]
That is, if a via cut that is more than necessary is used, a hold error may occur where the timing of the signal propagation delay time is too early, resulting in a defect.
[0011]
As a result, there is a problem that the number of repetitions in the layout increases in order to correct the signal wiring in which the defect has occurred. There is also a problem of increasing the congestion degree of the wiring.
[0012]
[Patent Document 1]
Japanese Patent Laid-Open No. 4-118968 (page 2, FIG. 3)
[0013]
[Problems to be solved by the invention]
With the above-described wiring connection method using only a plurality of via cuts disclosed in Patent Document 1, it is difficult to obtain a signal propagation delay time sufficient for timing control between logic elements.
[0014]
The present invention has been made to solve the above-described problems, and by arranging a necessary and sufficient number of via cuts in a predetermined via, a signal that can provide a signal propagation delay time sufficient for timing control between logic elements. An object is to provide a wiring connection method, a signal wiring connection system, and a method for manufacturing a semiconductor integrated circuit device.
[0015]
Another object of the present invention is to provide a signal wiring connection method, a signal wiring connection system, and a semiconductor integrated circuit that suppress electromigration in a via by arranging a necessary and sufficient number of via cuts in a predetermined via. An object is to provide a method for manufacturing a device.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, according to the signal wiring connection method of one embodiment of the present invention, when the first logic element and the second logic element arranged in the semiconductor integrated circuit device are connected to each other, different wiring layers are respectively provided. A first step of obtaining a signal propagation delay time between the first logic element and the second logic element for the signal wirings formed and connected to each other through the via connection portion; and the obtained signal propagation delay time. A second step of determining whether or not the set time is within the set time, and the via connection section so that the set time is within the set time when the obtained signal propagation delay time is not within the set time And a third step of connecting the first logic element and the second logic element by increasing the number of via cuts.
[0017]
In order to achieve the above object, according to another aspect of the signal wiring connection method of the present invention, different wiring layers are used to connect the first logic element and the second logic element arranged in the semiconductor integrated circuit. And a second step for determining whether or not the electromigration satisfies a predetermined reference value. And a third step of increasing the number of via cuts of the vias so as to satisfy the reference value when the reference value is not satisfied.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
(First embodiment)
FIG. 1 shows a signal wiring connection method according to a first embodiment of the present invention. A signal wiring is connected to a logic element from layout data of a semiconductor integrated circuit device, and signal wirings of different wiring layers are connected to vias (also referred to as via connection parts). It is a flowchart which shows the process until the wiring pattern connected through is created.
[0020]
The layout data includes logic element arrangement information, wiring path information, and timing constraint information of the semiconductor integrated circuit device.
[0021]
In other words, functions required for a semiconductor integrated circuit device to be manufactured are clarified, and a function design is performed in which the functions of each part such as a logic memory and an input / output interface for generating the functions are designed and connected to each other.
[0022]
Next, logic design is performed to design a specific electronic circuit from the functions and mutual relationships of the respective units.
[0023]
Then, logic element arrangement information indicating where to place the logic element on the semiconductor chip, wiring path information indicating through which area on the chip the logic element is connected, and synchronization between the logic elements are synchronized. Layout data composed of timing constraint information to be taken is created.
[0024]
As shown in FIG. 1, first, layout data of this semiconductor integrated circuit device is read (step S01).
[0025]
Next, timing is applied to signal wirings in which the output terminals of the first logic elements and the input terminals of the second logic elements arranged in the read semiconductor integrated circuit are formed in different wiring layers and connected to each other through vias. Analysis is performed (also referred to as obtaining a signal propagation delay time) (step S02).
[0026]
This timing analysis is to calculate the cell delay specific to each logic element, the wiring delay of the distributed constant circuit composed of the resistance and additional capacitance of the wiring connecting each logic element, and the signal propagation delay time is This is represented by the sum of the cell delay and the wiring delay.
[0027]
Next, it is determined whether or not the signal propagation delay time satisfies a hold time during which a signal should not propagate from the first logic element to the second logic element within a predetermined time (hereinafter referred to as a hold error). (Step S03).
[0028]
If there is a hold error, there is no need to increase the number of via cuts further, and the process jumps to step S06. In order to eliminate this hold error, a method of delaying the signal propagation time by adding a delay element to the signal wiring to increase the cell delay (not shown) is used.
[0029]
On the other hand, if there is no hold error, whether or not the signal propagation delay time satisfies a setup time in which a signal needs to propagate from the first logic element to the second logic element within a predetermined time (hereinafter referred to as setup). Error)) (step S04).
[0030]
If there is a setup error, the number of via cuts is increased in order to shorten the signal propagation time (step S05), and steps S02 to S05 are repeated until a predetermined reference value is satisfied.
[0031]
On the other hand, if there is no setup error, the process jumps to step S06, and the via connection wiring is connected to the signal wiring in which the first logic element and the second logic element are formed in different wiring layers and connected to each other through the via. Pattern data is created (step S06) and the process ends.
[0032]
2 and 3 specifically show these methods, FIG. 2 is a diagram showing the main part of the logic design, FIG. 3 is a layout diagram of FIG. 2, and FIG. 3 (a) is an arrangement of logic elements. FIG. 3B is a cross-sectional view taken along the line AA in FIG. 3A, developed, and viewed in the direction of the arrow.
[0033]
As shown in FIG. 2, in this logic design, the first logic element and the second logic element are connected to each other through signal lines formed in different wiring layers via other logic elements in the middle of the wiring path. This is an example.
[0034]
That is, the first logic element 11, for example, the flip-flop and the second logic element 12, for example, the flip-flop, has three signals via the third logic element 13, for example, an AND gate, and the fourth logic element 14, for example, a buffer. The wirings 15a, 15b and 15c are connected.
[0035]
The input signal input to the input terminal 17 of the first logic element 11 is latched by the first logic element 11 in synchronization with the clock signal supplied to the clock signal input terminal 18 through the clock signal wiring 16. 11 is input to the input terminal 19 of the second logic element 12 via the signal wiring 15a, the third logic element 13, the signal wiring 15b, the fourth logic element 14, and the signal wiring 15c.
[0036]
The input signal input to the input terminal 19 of the second logic element 12 is latched by the second logic element 12 in synchronization with the clock signal supplied to the clock signal input terminal 20 through the clock signal wiring 16.
[0037]
When this input signal has a signal propagation delay time from when the clock signal is input to the clock signal input terminal 18 to when it is latched at the next input terminal 19, the normal logic operation is guaranteed. Disappears and a setup error occurs.
[0038]
As shown in FIG. 3, the signal wiring connecting the first logic element 11 and the second logic element 12 has six via cuts 21, 22, 23, 24, via the third logic element 13 and the fourth logic element 14. The signal wirings 15a1, 15b1, and 15c1 of the first wiring layer and the signal wirings 15a2, 15b2, and 15c2 of the second wiring layer that are connected through 25 and 26 are configured.
[0039]
That is, the signal wiring 15a2 of the second wiring layer connected to the output terminal 31 of the first logic element 11 through the via cut 21 is connected to the signal wiring 15a1 of the first wiring layer through the via cut 22, and the signal wiring 15a1 is connected to the third logic element. 13 input terminals 32.
[0040]
The signal wiring 15b1 of the first wiring layer connected to the output terminal 33 of the third logic element 13 is connected to the signal wiring 15b2 of the second wiring layer through the via cut 23, and the signal wiring 15b2 is connected to the signal wiring 15b2 of the fourth logic element 14 through the via cut 24. It is connected to the input terminal 34.
[0041]
The signal wiring 15c1 of the first wiring layer connected to the output terminal 35 of the fourth logic element 14 is connected to the signal wiring 15c2 of the second wiring layer through the via cut 25, and the signal wiring 15c2 is connected to the signal wiring 15c2 of the second logic element 12 through the via cut 26. It is connected to the input terminal 19.
[0042]
Timing analysis is performed on this layout to determine cell delay and wiring delay.
[0043]
When the cell delay of the first logic element 11 is, for example, 2 ns, the cell delay of the third logic element 13 is, for example, 2 ns, and the cell delay of the fourth logic element 14 is, for example, 1 ns, the cell delay is The sum is 5 ns.
[0044]
For the wiring delay, the total additional capacitance of the signal wirings 15a, 15b, and 15c is 10 pF, for example, the total resistance of the signal wiring is 10Ω, and the resistance of the via cuts 21, 22, 23, 24, 25, and 26 is 4Ω per one. Thus, the total resistance of the via is calculated as a distributed constant circuit consisting of 24Ω, for example, 7 ns.
[0045]
Thus, the signal propagation delay time until the signal propagates from the input terminal 17 to the next input terminal 19 is 12 ns, which is the sum of both.
[0046]
For this reason, when the clock signal period is, for example, 10 ns, the signal propagation delay time becomes longer than the clock signal period, and a setup error occurs.
[0047]
Accordingly, in order to eliminate the setup error, the number of via cuts is increased in accordance with the flowchart shown in FIG. 1, for example, until the sum of the wiring resistance and the via resistance becomes 18Ω or less in order to reduce the wiring delay to 5 ns or less. What is necessary is just to add and arrange a via cut in a predetermined location.
[0048]
FIG. 4 is a layout diagram in which these three via cuts are added to predetermined locations. FIG. 4A is a diagram showing the arrangement and wiring paths of logic elements, and FIG. 4B is a cross-sectional view of FIG. It is sectional drawing cut | disconnected along the B line, expand | deployed and looked at the arrow direction.
[0049]
As shown in FIG. 4, for example, a via cut 51 is added to the via cut 22 that connects the first wiring layer 15a1 and the second wiring layer 15a2, and the via cut 51 connects the first wiring layer 15b1 and the second wiring layer 15b2. 23, via cuts 52 are added and juxtaposed, and via cuts 53 are added and juxtaposed to via cuts 25 connecting the first wiring layer 15c1 and the second wiring layer 15c2, thereby forming double cut vias.
[0050]
As described above, according to the signal wiring connection method according to the first embodiment, the timing analysis is performed on the signal wirings formed in different wiring layers and connected to each other through vias, and a setup error is generated. Since a necessary and sufficient number of via cuts are arranged in predetermined vias of the generated signal wiring, a signal propagation delay time sufficient for complex timing control between logic elements can be obtained. Therefore, the timing control accuracy is improved and the design of the semiconductor integrated circuit device is facilitated.
[0051]
The timing analysis described above can be performed on the schematic wiring for estimating the wiring length after the arrangement of the first to fourth logic elements is determined by the floor plan. Moreover, it can carry out with respect to the actual wiring in which the actual wiring length was determined from the schematic wiring. It can also be done for both.
[0052]
In the above-described embodiment, the signal wiring having the third logic element 13 and the fourth logic element 14 in the middle of the wiring path as the signal wiring, formed in different wiring layers, and connected to each other through vias has been described. However, signal wiring that does not pass other logic elements in the middle of the wiring path may be used.
[0053]
Further, the case where the signal propagation delay time between the input terminal 17 of the first logic element 11 and the input terminal 19 of the second logic element 12 is obtained has been described. However, the output terminal 31 and the second logic element of the first logic element 11 are described. The signal propagation delay time between the twelve output terminals 36 may be obtained.
[0054]
Next, these modifications will be described.
[0055]
(Modification 1 of the first embodiment)
FIG. 5 is a flowchart showing a first modification of the first embodiment of the present invention. This modification is different from the first embodiment in that timing analysis is performed for each of the schematic wiring and the actual wiring.
[0056]
That is, as shown in FIG. 5, first, layout data is read as in FIG. 1, timing analysis is performed, and the presence or absence of a hold error is checked (steps S21 to S23).
[0057]
If there is no hold error, check if there is a setup error (step S24). If there is a setup error, place double cut vias in all vias used in the signal wiring net where the setup error occurred. The actual wiring is performed (step S26).
[0058]
On the other hand, if there is a hold error or no setup error, actual wiring is performed by placing single-cut vias in all the vias used in the signal wiring net where there was no setup error (step S25). .
[0059]
Next, the timing analysis is performed again on the actual wiring obtained in step S25 or step S26, and the presence or absence of a hold error is checked (step S27 to step S28).
[0060]
If there is no hold error, the presence or absence of a setup error is checked (step S29). If there is a setup error, the number of via cuts of a predetermined via used in the signal wiring net in which the setup error has occurred is increased by one. (Step S30), and steps S27 to S30 are repeated until the setup error is resolved.
[0061]
On the other hand, if there is a hold error or if there is no setup error, the via connection wiring pattern data is created and the process ends (step S31).
[0062]
In the timing analysis for the schematic wiring, it is possible to quickly estimate the signal propagation delay time using the approximate value of the additional capacitance and the wiring resistance depending on the wiring length of the signal wiring.
[0063]
In the timing analysis for the actual wiring, the signal propagation delay time can be accurately estimated using appropriate values of the additional capacitance, the wiring resistance, and the via resistance depending on the wiring length of the signal wiring.
[0064]
As a result, double cut vias can be placed in vias where setup errors are expected during rough wiring. Therefore, if the wiring path after actual wiring is significantly different from the wiring path during rough wiring, depending on the degree of congestion, the single There is no fear that a via that cannot be changed from a cut via to a double cut via.
[0065]
As described above, in the first modification described above, it is possible to quickly and accurately determine the necessary and sufficient number of via cuts by performing timing analysis on both the schematic wiring and the actual wiring. Therefore, the timing control accuracy is improved and the manufacture of the semiconductor integrated circuit device is facilitated.
[0066]
(Modification 2 of the first embodiment)
FIG. 6 is a flowchart showing a second modification of the first embodiment of the present invention. This modification is different from the first embodiment in that the number of necessary via holes is predicted based on the timing analysis result for the schematic wiring.
[0067]
That is, as shown in FIG. 6, first, layout data is read in the same manner as in FIG. 1, timing analysis is performed, and the presence or absence of a hold error is checked (step S41 to step S43).
[0068]
If there is no hold error, the presence or absence of a setup error is checked (step S44). If there is a setup error, the number of via cuts required to eliminate the setup error is calculated, and the signal wiring network where the setup error has occurred is calculated. The actual wiring is performed by distributing the single cut via to all the vias used in 1 and the double cut via (step S46).
[0069]
On the other hand, if there is a hold error or if there is no setup error, a single cut via is placed on all vias used in the signal wiring net where there was no setup error and actual wiring is performed (step S45). .
[0070]
Next, the timing analysis is performed again on the actual wiring obtained in step S45 or step S46 to check for a hold error (from step S47 to step S48).
[0071]
If there is no hold error, the presence of a setup error is checked (step S49). If there is a setup error, the number of via cuts of a predetermined via used in the signal wiring net in which the setup error has occurred is increased by one. (Step S50), and step S47 to step S50 are repeated until the setup error is resolved.
[0072]
On the other hand, if there is a hold error or if there is no setup error, the via connection wiring pattern data is created and the process ends (step S51).
[0073]
In this way, predict how many double cut vias should be placed in the vias on the signal wiring net, and reduce the congestion of the signal wiring by limiting the use of the minimum required double cut vias. Is possible.
[0074]
As described above, in Modification 2 described above, since the number of necessary via holes is predicted in advance based on the timing analysis result for the schematic wiring, the necessary and sufficient number of via cuts can be determined more quickly and accurately. Is possible. Therefore, the timing control accuracy is improved and the manufacture of the semiconductor integrated circuit device is facilitated.
[0075]
(Second Embodiment)
Next, a signal wiring connection system according to a second embodiment of the present invention will be described with reference to FIG. The signal wiring connection system of the present embodiment is for realizing the signal wiring connection method described in the first embodiment. FIG. 7 is a block diagram showing a signal wiring connection system according to the present embodiment.
[0076]
As shown in the figure, the signal wiring connection system 61 of this embodiment includes a logic design data storage unit 62 that stores logic design data of a semiconductor device, and a new via connection wiring pattern by analyzing the timing of signal wiring. A program storage unit 63 that stores a program to be created, a placement and wiring information storage unit 64 that stores logic element placement and wiring path information, and a timing information storage unit that stores timing analysis information related to signal propagation delay time of signal wiring 65, a via information storage unit 66 for storing via information relating to signal wirings formed in different wiring layers and connected to each other through vias, and processing control provided with means for executing a series of signal wiring connection processing Unit 67, output device 69 that outputs the processing result via input / output control unit 68, instructions to processing control unit 67, etc. It is composed of an input device 70 for inputting.
[0077]
The logic design data storage unit 62, the program storage unit 63, the placement and routing information storage unit 64, the timing information storage unit 65, and the via information storage unit 66 may be partially configured by a main storage device inside the computer. You may comprise with memory | storage devices, such as a semiconductor memory connected to a computer, a magnetic disk, a magnetic tape, and an optical disk.
[0078]
The processing control unit 67 constitutes a part of a central processing unit of a computer system, and is executed by a centralized processing system or a distributed processing system computer system.
[0079]
The processing control unit 67 reads the signal wiring from the logic design data storage unit 62 and extracts the signal wiring in which the first and second logic elements are formed in different wiring layers and connected to each other through the via. An extraction unit 71, a timing analysis unit 72 for determining a signal propagation delay time between the first and second logic elements, a timing determination unit 73 for determining whether the signal propagation delay time satisfies a predetermined reference value, A via changing unit 74 is arranged to increase the number of via cuts of vias of signal wirings that are determined not to satisfy the reference value, and a signal wiring unit 75 generates wiring pattern data by changing vias.
[0080]
The signal wiring extraction unit 71, timing analysis unit 72, timing determination unit 73, via change unit 74, and signal wiring unit 75 are stored in advance in the program storage unit 63 as software. Although it is executed by the processing device, it may be executed by dedicated hardware.
[0081]
As described above, according to the signal wiring connection system of the second embodiment, the timing analysis of the signal wiring is performed, and the via of the signal wiring that does not satisfy the predetermined reference value is changed. A signal wiring connected through vias having a signal transmission delay time sufficient for timing control is obtained.
[0082]
(Third embodiment)
Next, a method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention will be described with reference to FIG. The method for manufacturing a semiconductor integrated circuit device of this embodiment is an example of manufacturing a semiconductor integrated circuit device using the signal wiring connection system shown in the second embodiment. FIG. 8 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device of the present invention.
[0083]
First, layout data including logic element placement information, wiring path information, and timing constraint information is created by functional design and logic design of the semiconductor integrated circuit device to be manufactured (step S61).
[0084]
In other words, functions required for a semiconductor integrated circuit device to be manufactured are clarified, and a function design is performed in which the functions of each part such as a logic memory and an input / output interface for generating the functions are designed and connected to each other.
[0085]
Next, logic design is performed to design a specific electronic circuit from the functions and mutual relationships of the respective units.
[0086]
Then, logic element arrangement information indicating where the logic element is arranged on the semiconductor chip, wiring path information indicating which area on the chip the logic element is connected to, and synchronization between the logic elements are obtained. Layout data consisting of timing constraint information is created and stored as logic design data.
[0087]
Next, the layout data of the semiconductor integrated circuit device is read, and the first logic element and the second logic element arranged in the semiconductor integrated circuit are formed in different wiring layers, and are connected to each other through vias. Are extracted (step S62).
[0088]
Next, a signal propagation delay time between the first logic element and the second logic element is obtained and a timing analysis is performed (step S63).
[0089]
Next, it is determined whether or not the signal propagation delay time is a predetermined reference value, for example, a setup error (step S64). If the reference is not satisfied, the number of via cuts is increased and vias are arranged (step S65).
[0090]
Next, it is determined whether or not all signal wirings of the logic design data are checked (step S66), and steps S62 to S65 are repeated until all the signal wirings are checked. When all the signal wirings are checked, via connection wiring pattern data is created (step S67).
[0091]
Next, exposure mask drawing data for forming a via connection wiring pattern on the exposure mask is created, and an exposure mask is manufactured based on the exposure mask drawing data (step S68).
[0092]
Next, a series of wafer manufacturing processes (previous process) that repeats a film forming process such as an insulating film, a semiconductor film, and a metal film on a semiconductor substrate, a lithography process using the above-described exposure mask, an etching process, and an ion implantation process. Thus, semiconductor devices are collectively formed on the semiconductor wafer. Then, a semiconductor device is manufactured through a dicing process, a bonding process, and an inspection process (post-process) (step S69).
[0093]
As described above, according to the method of manufacturing a semiconductor integrated circuit device according to the third embodiment, a propagation delay time sufficient for timing control between logic elements can be obtained, so that a semiconductor integrated circuit device is manufactured with a high yield. can do.
[0094]
(Fourth embodiment)
FIG. 9 shows a signal wiring connection method according to the fourth embodiment of the present invention. In the signal wiring connection method, logic elements are respectively formed in different wiring layers from layout data of the semiconductor integrated circuit device, and are connected to each other through vias. For example, it is a flowchart showing a process until electromigration analysis is performed on a clock signal wiring having a particularly high signal frequency and final via connection wiring pattern data is completed.
[0095]
This layout data includes logic element arrangement information indicating where the logic elements of the semiconductor integrated circuit device are arranged on the semiconductor chip, and wiring path information indicating through which area on the chip the logic elements are connected. And electromigration constraint information related to current density, operating temperature, guaranteed operation years, and the like.
[0096]
As shown in FIG. 9, first, layout data of this semiconductor integrated circuit device is read (step S81).
[0097]
Next, the output terminal of the first logic element and the input terminal of the second logic element arranged in the read semiconductor integrated circuit are formed in different wiring layers, respectively, and the signal wiring having the highest resistance is connected to each other through the via For part, for example, via, electromigration analysis is performed to calculate the current flowing through the signal wiring from the wiring material, wiring dimensions, operating voltage, signal frequency, wiring capacity, etc., and to obtain the reliability period from the current density and operating temperature ( Step S82).
[0098]
Next, it is determined whether or not the reliability period satisfies a predetermined reference value, for example, an operation guarantee year (hereinafter referred to as an electromigration error) (step S83).
[0099]
Next, when there is an electromigration error, the via cut number of the via having the highest resistance is increased and arranged so as to satisfy a predetermined reference value (step S84), and via connection wiring pattern data is created (step S85). finish.
[0100]
As described above, according to the signal wiring connection method according to the fourth embodiment, the electromigration analysis is performed on the vias, and a necessary and sufficient number of via cuts are arranged in the vias that cause an electromigration error. .
[0101]
Accordingly, a reliability period sufficient to satisfy the operation guarantee years can be obtained, and the semiconductor integrated circuit device can be easily manufactured.
[0102]
(Modification of the fourth embodiment)
FIG. 10 is a flowchart showing a modification of the first embodiment of the present invention. This modification is different from the fourth embodiment in that electromigration analysis is performed on the schematic wiring and the actual wiring.
[0103]
That is, as shown in FIG. 10, first, layout data is read as in FIG. 9, electromigration analysis is performed, and the presence or absence of an electromigration error is checked (step S91 to step S93).
[0104]
If there is no electromigration error, a single cut via is placed in the via on the signal wiring net and actual wiring is performed (step S94). If there is an electromigration error, the net of the signal wiring in which the electromigration error has occurred An actual wiring is performed by arranging a double cut via in the upper via (step S95).
[0105]
Next, the electromigration analysis is performed again on the actual wiring obtained in step S94 or step S95, and the presence or absence of an electromigration error is checked (step S96 to step S97).
[0106]
If there is an electromigration error, the number of via cuts of a predetermined via on the signal wiring net is increased by 1 (step S98), and steps S96 to S98 are repeated until the electromigration error is eliminated.
[0107]
On the other hand, if there is no electromigration, the via connection wiring pattern data is created (step S99), and the process ends.
[0108]
As a result, double cut vias can be arranged in advance in vias where electromigration errors are expected during rough wiring, so if the wiring route after actual wiring is significantly different from the wiring route during rough wiring, depending on the degree of congestion There is no possibility that a via that cannot be changed from a single cut via to a double cut via after actual wiring is generated.
[0109]
As described above, in the above-described modification example, the necessary and sufficient number of via cuts are determined quickly and accurately by performing electromigration analysis on both the schematic wiring and the actual wiring. Accordingly, a reliability period sufficient to satisfy the operation guarantee years can be obtained, and the semiconductor device can be easily manufactured.
[0110]
Next, a signal wiring connection system for realizing the signal wiring connection method shown in the fourth embodiment of the present invention is the same as the signal wiring connection system in FIG. 7 shown in the second embodiment. Since an electromigration analysis unit for performing electromigration analysis and an electromigration determination unit can be added in the same manner, description thereof will be omitted.
[0111]
Further, in the semiconductor device manufacturing method using the above-described signal wiring connection system, it is determined whether or not the process of performing electromigration analysis and a predetermined reference value are satisfied in the flowchart of FIG. 8 shown in the third embodiment. Since it can implement similarly by adding a process, the description is abbreviate | omitted.
[0112]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a signal wiring connection method and a signal wiring connection system capable of obtaining a signal propagation delay time sufficient for timing control between logic elements.
[0113]
Moreover, according to the method for manufacturing a semiconductor integrated circuit device using the signal wiring, high reliability can be provided.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a signal wiring connection method according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a main part of logic design according to the first embodiment of the present invention.
3A and 3B are layout diagrams according to the first embodiment of the present invention, in which FIG. 3A is a diagram showing the arrangement and wiring paths of logic elements, and FIG. 3B is AA in FIG. 3A; Sectional drawing which cut | disconnected along the line and expanded and looked at the arrow direction.
4A and 4B are layout diagrams according to the first embodiment of the present invention, in which FIG. 4A is a diagram showing the arrangement and wiring paths of logic elements, and FIG. 4B is a line BB in FIG. Sectional drawing which cut | disconnected along the line and expanded and looked at the arrow direction.
FIG. 5 is a flowchart showing a first modification of the first embodiment of the present invention.
FIG. 6 is a flowchart showing a second modification of the first embodiment of the present invention.
FIG. 7 is a block diagram showing a signal wiring connection system according to a second embodiment of the present invention.
FIG. 8 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 9 is a flowchart showing a signal wiring connection method according to a fourth embodiment of the present invention;
FIG. 10 is a flowchart showing a modification of the fourth embodiment of the present invention.
FIG. 11 is a diagram showing a conventional signal wiring connection;
[Explanation of symbols]
11 First logic element
12 Second logic element
13 Third logic element
14 Fourth logic element
15a, 15b, 15c Signal wiring
15a1, 15b1, 15c1 Signal wiring of the first wiring layer
15a2, 15b2, 15c2 Signal wiring of second wiring layer
16 Clock signal wiring
17, 19, 32, 34 Input terminal
18, 20 Clock signal input terminal
21, 22, 23, 24, 25, 26, 51, 52, 53 Via cut
31, 33, 35, 36 Output terminal
61 Signal wiring connection system
62 Logic design data storage
63 Program storage
64 Placement and wiring information storage unit
65 Timing information storage unit
66 Via information data storage
67 Processing control unit
68 I / O controller
69 Output device
70 Input device
71 Signal wiring extractor
72 Timing analyzer
73 Timing determination unit
74 Via Change Department
75 Signal wiring section

Claims (15)

When the first logic element and the second logic element arranged in the semiconductor integrated circuit device are connected to each other, the first logic element is connected to the signal wirings formed in different wiring layers and connected to each other through the via connection portion. A first step of determining a signal propagation delay time between an element and the second logic element;
A second step of determining whether or not the obtained signal propagation delay time is within a set time;
When the obtained signal propagation delay time is not within the set time, the number of via cuts of the via connection portion is increased so that the first logic element and the second logic element are within the set time. A third step of connecting;
A signal wiring connection method for a semiconductor integrated circuit device, comprising: 2. The signal wiring connection method for a semiconductor integrated circuit device according to claim 1, wherein in the first step, a signal propagation delay time is obtained by simulation. When the first logic element and the second logic element arranged in the semiconductor integrated circuit device are connected to each other, the first logic element is formed with respect to a schematic signal wiring formed in a different wiring layer and connected to each other through a via. And a first step of obtaining a signal propagation delay time between the second logic elements;
A second step of determining whether or not the signal propagation delay time is within a set time;
A third step of performing actual wiring when the obtained signal propagation delay time is within a set time; and
A fourth step of performing actual wiring by increasing the number of via cuts of the via connection portion by 1 when the obtained signal propagation delay time is not within the set time;
A fifth step of performing timing analysis on the actual wiring;
A sixth step of determining whether or not the signal propagation delay time based on the timing analysis of the actual wiring is within a set time;
A seventh step of increasing and arranging the number of via cuts of the via connection until the signal propagation delay time obtained is not within the set time, and being within the set time;
A signal wiring connection method for a semiconductor integrated circuit device, comprising: In the fourth step, when the reference value is not satisfied, the necessary number of via cuts is calculated from the signal propagation delay time, and the vias are distributed to the single cut via and the double cut via. 4. The signal wiring connection method for a semiconductor integrated circuit device according to claim 3, wherein actual wiring is performed. 5. The signal wiring connection method according to claim 1, wherein the signal wiring for connecting the first logic element and the second logic element has another logic element in the middle of the wiring path. . The signal propagation delay time is a signal propagation delay time between the input terminal of the first logic element and the input terminal of the second logic element or between the output terminal of the first logic element and the output terminal of the second logic element. The signal wiring connection method according to claim 1, wherein the signal wiring is connected. The signal wiring connection method according to claim 1, wherein the set time is a setup time. The signal wiring connection method according to claim 7, wherein the set time further includes a hold time. A signal wiring extraction unit for extracting signal wirings formed in different wiring layers and connected to each other through via connection parts in order to connect the first logic element and the second logic element arranged in the semiconductor integrated circuit;
A timing analyzer for obtaining a signal propagation delay time between the first logic element and the second logic element;
A timing determination unit that determines whether the signal propagation delay time is within a set time; and
A via for connecting the first logic element and the second logic element by increasing the number of via cuts in the via connection portion so that the set time is reached when the signal propagation delay time is not within the set time. Change part,
A signal wiring portion for performing signal wiring based on the via change information;
A signal wiring connection system for a semiconductor integrated circuit device, comprising: In order to connect the first logic element and the second logic element arranged in the semiconductor integrated circuit to each other, the first logic element is formed on signal wirings formed in different wiring layers and connected to each other through a via connection portion. And a first step of performing a timing analysis for obtaining a signal propagation delay time between the second logic elements;
A second step of determining whether or not the signal propagation delay time is within a set time;
A third step of creating a signal wiring pattern in which the number of via cuts of the via connection portion is increased so as to be within the set time when not within the set time;
A fourth step of manufacturing an exposure mask based on the signal wiring pattern and manufacturing a semiconductor integrated circuit device by a predetermined semiconductor integrated circuit manufacturing step including an exposure step;
A method for manufacturing a semiconductor integrated circuit device, comprising: In order to connect the first logic element and the second logic element arranged in the semiconductor integrated circuit to each other, electromigration analysis of the signal wiring is performed on the signal wirings formed in different wiring layers and connected to each other through vias. A first step of performing
A second step of determining whether the electromigration satisfies a predetermined reference value;
A third step of disposing the via cut number of the vias so as to satisfy the reference value when the reference value is not satisfied;
A signal wiring connection method comprising: In order to connect the first logic element and the second logic element arranged in the semiconductor integrated circuit to each other, an electromigration of the signal wiring with respect to the schematic signal wiring formed in different wiring layers and connected to each other through a via A first step of analyzing,
A second step of determining whether the electromigration satisfies a predetermined reference value;
A third step of performing actual wiring using the via as a single-cut via when the reference value is satisfied;
A fourth step of performing actual wiring using the via as a double-cut via when the reference value is not satisfied;
A fifth step of performing electromigration analysis on the actual wiring; a sixth step of determining whether or not the electromigration satisfies a predetermined reference value;
When the reference value is not satisfied, a seventh step of arranging by increasing the number of via cuts of the via connection portion by 1,
Comprising
The signal wiring connection method, wherein the fourth to seventh steps are repeated until the reference value is satisfied. The signal wiring connection method according to claim 11, wherein the signal wiring is a clock signal wiring. A signal wiring extraction unit for extracting schematic signal wirings formed in different wiring layers and connected to each other through vias in order to connect the first logic element and the second logic element arranged in the semiconductor integrated circuit;
An electromigration analysis unit for performing electromigration analysis of the signal wiring;
When the reference value is not satisfied, a via changing unit arranged to increase the number of via cuts of the via, and
A signal wiring connection system comprising: In order to connect the first logic element and the second logic element arranged in the semiconductor integrated circuit to each other, an electromigration of the signal wiring with respect to the schematic signal wiring formed in different wiring layers and connected to each other through a via A first step of analyzing,
A second step of determining whether the electromigration satisfies a predetermined reference value;
A third step of creating a signal wiring pattern in which the number of via cuts of the via is increased when the reference value is not satisfied;
A fourth step of manufacturing an exposure mask based on the signal wiring pattern and manufacturing a semiconductor integrated circuit device by a predetermined semiconductor integrated circuit manufacturing step including an exposure step;
A method for manufacturing a semiconductor integrated circuit device, comprising:

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