JP2005025214A - Active matrix liquid crystal display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a voltage shift of an image signal written to a liquid crystal pixel. <P>SOLUTION: The liquid crystal display device comprises liquid crystal pixels which are arrayed in matrix and pixel transistors for driving the individual liquid crystal pixels. A gate pulse GP is applied to the gate electrode of a pixel transistor in a selection period to write an image signal Vsig to the liquid crystal pixel. Then the gate pulse GP is stopped from being applied in a non-selection period and the written image signal Vsig is held. In transition from the selection period to the non-selection period, an inverter in asymmetrical structure is used to smoothly lower the gate pulse GP and then the written image signal Vsig is deterred from having a voltage shift ΔV. Instead of this method, the voltage level of the gate pulse GP may temporarily be lowered to a halfway point right before the transition from the selection period to the non-selection period and then lowered to suppress the voltage shift ΔV of the written image signal Vsig. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix liquid crystal display device and a driving method thereof. More specifically, the present invention relates to a method for applying a gate pulse to a pixel transistor connected to each liquid crystal pixel.

A general configuration of a conventional active matrix liquid crystal display device will be briefly described with reference to FIG. FIG. 5 is a schematic equivalent circuit diagram of one pixel portion. Each pixel is provided at the intersection of the gate line X and the signal line Y. A liquid crystal pixel is equivalently represented by a liquid crystal capacitance _CLC . Usually, an auxiliary capacitor C _S is connected to the liquid crystal capacitor C _LC in parallel. One end of the liquid crystal capacitance C _LC, together with being connected to the driving transistor Tr, the other end a predetermined reference voltage Vcom is connected to the counter electrode is applied. The pixel transistor Tr is formed of an insulated gate field effect thin film transistor. The drain electrode D of the pixel transistor Tr is connected to the signal line Y and receives the supply of the image signal Vsig. The source electrode S is connected to one end of the liquid crystal capacitor _CLC , that is, the pixel electrode. Further, the gate electrode G is connected to the gate line X, and a gate pulse having a predetermined gate voltage Vgate is applied. A coupling capacitor C _GS is formed between the liquid crystal capacitor C _LC and the gate electrode G. The coupling capacitance _CGS is a combination of the stray capacitance component between the pixel electrode and the gate line X and the parasitic capacitance component between the source region and the gate region inside the pixel transistor Tr. The latter parasitic capacitance component is dominant, and its value varies depending on individual pixel transistors Tr. With respect to this background art, Patent Documents 1 and 2 below can be cited.
Japanese Patent Laid-Open No. 1-219827 Japanese Patent Laid-Open No. 3-158830

Next, a problem to be solved by the present invention will be briefly described with reference to FIG. When the gate pulse of the voltage Vgate is applied to the gate electrode G during the selection period, the pixel transistor Tr is turned on. At this time, the image signal Vsig supplied from the signal line Y is written into the liquid crystal pixel through the transistor Tr, and so-called sampling is performed. Next, in the non-selection period, the application of the gate pulse is stopped, and the written image signal is held in the liquid crystal capacitor _CLC . When shifting from the selection period to the non-selection period, the rectangular wave gate pulse falls rapidly from the high level to the low level. At this time, the electric charge stored in the liquid crystal capacitor _CLC by the coupling through the coupling capacitor _CGS described above is instantaneously discharged. For this reason, a voltage shift ΔV occurs in the image signal Vsig written in the liquid crystal pixel. Since the value of the coupling capacitance _CGS varies _among individual pixels, the voltage shift ΔV also varies, so-called roughness appears on the display screen, and there is a problem or problem that the display quality is significantly deteriorated.

An image signal is written into the liquid crystal pixel during the selection period, and one field is formed by holding the image signal written during the subsequent non-selection period. The transmittance of the liquid crystal pixel in one field is determined by the effective voltage applied to the liquid crystal during that time. As a characteristic of the pixel transistor Tr, it is necessary to ensure an on-current necessary for completing writing within a selection period. Further, in order to obtain a sufficient effective voltage for lighting the liquid crystal pixels during one field period, the leakage current during the non-selection period or the holding period is made as small as possible. As the effective voltage, the influence during the non-selection period which is much longer than the selection period is large. For this reason, the above-described voltage shift ΔV that occurs when the pixel capacitor _CLC is turned off after being charged greatly affects the effective voltage applied to the liquid crystal, thereby degrading the display quality.

Conventionally, in order to suppress the absolute amount and variation of the voltage shift ΔV, a countermeasure has been taken in which the auxiliary capacitor C _S connected in parallel to the liquid crystal capacitor C _LC is formed larger. That is, a charge sufficient to supplement the amount of charge discharged through the coupling capacitor C _GS is stored in the auxiliary capacitor C _S in advance. However, the auxiliary capacitor C _S is formed in the liquid crystal pixel region. If this dimension is set large, the pixel aperture ratio is sacrificed and there is a problem or problem that sufficient display contrast cannot be obtained.

In view of the above-described problems of the conventional technology, an object of the present invention is to suppress a voltage shift of an image signal caused by a gate / source coupling capacitance without sacrificing a pixel aperture ratio. In order to achieve this object, measures were taken to improve the gate pulse application method. According to the first means of the present invention, a liquid crystal pixel arranged in a matrix, a pixel transistor for driving each liquid crystal pixel, and an auxiliary capacitor are provided, and the liquid crystal pixel and the auxiliary capacitor are connected to the pixel transistor. The pixel transistor has a source electrode connected to the liquid crystal pixel and the auxiliary capacitor, a drain electrode connected to the signal line, a gate electrode connected to the gate line, and a gate line connected to the gate electrode of each pixel transistor. Active-matrix liquid crystal display device comprising: a vertical scanning circuit that sequentially applies a gate pulse through a gate to perform a selection operation; and a horizontal drive circuit that writes an image signal to each liquid crystal pixel through a signal line and a selected pixel transistor In contrast, during the selection period, a gate pulse is applied to the gate electrode of the pixel transistor to send an image signal to each liquid crystal pixel. In the driving method for displaying an image by holding the image signal written by stopping the application of the gate pulse during the non-selection period, the vertical scanning circuit outputs the gate pulse to each gate line. It has an output inverter composed of an N-channel transistor and a P-channel transistor, the output inverter has an asymmetric structure, and the ratio of the channel width to the channel length of the N-channel transistor is higher than that of the P-channel transistor. Using the asymmetric structure of the output inverter, the gate pulse is sharply raised when shifting from the non-selection period to the selection period, and smoothed when shifting from the selection period to the non-selection period. It is characterized in that the voltage shift of the written image signal is suppressed by falling to.
According to the second means of the present invention, a liquid crystal pixel arranged in a matrix, a pixel transistor for driving each liquid crystal pixel, and an auxiliary capacitor are provided, and the liquid crystal pixel and the auxiliary capacitor are connected to the pixel transistor. The pixel transistor has a source electrode connected to the liquid crystal pixel and an auxiliary capacitor, a drain electrode connected to a signal line, a gate electrode connected to a gate line, and a gate electrode connected to the gate electrode of each pixel transistor. An active matrix type liquid crystal display comprising a vertical scanning circuit that sequentially applies a gate pulse through a line and performs a selection operation, and a horizontal drive circuit that writes an image signal to each liquid crystal pixel through a signal line and a selected pixel transistor For the device, a gate pulse is applied to the gate electrode of the pixel transistor during the selection period, and the image signal is sent to each liquid crystal pixel. In the driving method for performing image display by stopping application of a gate pulse during writing and holding a written image signal during a non-selection period, the vertical scanning circuit includes a voltage dividing resistor for switching a power supply voltage level, A switching transistor is provided, and when switching from the non-selection period to the selection period, the gate pulse is sharply raised, and the voltage dividing resistor and switching transistor for switching the power supply voltage level are controlled, so that the non-selection from the selection period It is characterized in that the voltage shift of the written image signal is suppressed by lowering the voltage level of the gate pulse once and then lowering it immediately before shifting to the period.

The means will be described below with reference to FIG. As described above, two measures were taken to achieve the same purpose. 1A includes liquid crystal pixels arranged in a matrix, pixel transistors for driving the individual liquid crystal pixels, and auxiliary capacitors. The liquid crystal pixels and the auxiliary capacitors are An active matrix liquid crystal display device having a source electrode connected to the liquid crystal pixel and an auxiliary capacitor, a drain electrode connected to a signal line, and a gate electrode connected to a gate line. On the other hand, the gate pulse GP is applied to the gate electrode of the pixel transistor during the selection period, the image signal Vsig is written to each liquid crystal pixel, and the application of the gate pulse GP is stopped during the non-selection period to hold the written image signal Vsig. In the driving method for displaying an image by performing the above operation, the gate pulse GP is applied when shifting from the non-selection period to the selection period. Up to Shun, it was set to suppress the voltage shift ΔV of the image signals Vsig written by lowering smoothly up the gate pulse GP at the transition from the selection period to the non-selection period.
In the active matrix liquid crystal display device, AC driving is performed to invert the polarity of the image signal Vsig for each field in order to extend the life of the liquid crystal. In the figure, a positive image signal Vsig is written to the pixel with respect to a predetermined reference voltage Vcom applied to the counter electrode in the first field, and a negative image signal Vsig is written in the second field. Focusing on a certain gate line, a gate pulse GP of a predetermined gate voltage Vgate is applied to the gate electrode of the pixel transistor during the selection period in the first field. The falling edge of the gate pulse GP is smooth. For this reason, the voltage shift ΔV is smaller than in the conventional case where the voltage falls sharply, and it becomes possible to maintain a predetermined level during the non-selection period. Similarly in the second field, the fall of the gate pulse GP is smooth, and the voltage shift ΔV is suppressed. Unlike the falling edge, even if the rising edge of the gate pulse GP is steep, the image quality is not affected.

  In the second means shown in FIG. 1B, immediately before the transition from the selection period to the non-selection period, the voltage level of the image signal Vsig written by once decreasing the voltage level Vgate1 of the gate pulse GP to Vgate2 and then decreasing it. The shift ΔV is suppressed. Note that the timing for lowering the voltage level of the gate pulse GP is set so as not to affect the writing operation to the liquid crystal pixels during the selection period. That is, when the writing is completed, the gate voltage Vgate1 is lowered to Vgate2. This second means is particularly effective when writing and holding negative image signals. For example, a large potential difference is generated between the gate voltage Vgate1 and the image signal Vsig in the second field. When the gate voltage Vgate1 is once lowered to Vgate2 and then lowered, the potential difference between the gate line and the source electrode becomes small at the transition from the selection period to the non-selection period. For this reason, the voltage shift ΔV can be effectively suppressed.

As described with reference to FIG. 5, the voltage shift ΔV of the image signal increases in proportion to the coupling capacitance C _GS between the gate and the source. Conversely, the larger the liquid crystal capacitance C _LC and the auxiliary capacitance C _{S, the} smaller. Furthermore, it increases in proportion to the potential difference V _GS between the gate and the source. This V _GS corresponds to the potential difference between the gate voltage Vgate and the written image signal Vsig at the transition from the selection period to the non-selection period. When the relationship described above is expressed by a mathematical formula, ΔV = C _GS / (C _LC + C _GS + C _S ) × V _GS is obtained. By the way, the impedance of the coupling capacitor C _GS has frequency dependence and is easy to pass through as high frequency components. Therefore, in the first means shown in FIG. 1A, the high-frequency component is removed by smoothing the falling edge of the gate pulse, and the voltage shift due to the coupling through the coupling capacitance is suppressed.

As apparent from the relational expression described above, the voltage shift ΔV can be suppressed by reducing the gate-source potential difference V _GS . Therefore, in the second means shown in FIG. 1B, the voltage shift ΔV is suppressed by decreasing the V _GS by once decreasing the gate voltage immediately before the gate pulse falls.
As described above, according to the present invention, the voltage shift of the image signal can be suppressed by shaping the waveform of the gate pulse, and the display quality can be improved by reducing the roughness of the display screen. Further, when the waveform shaping is performed by an external circuit, the active matrix type liquid crystal display device alone has the effect that it is not necessary to sort out the rough defects and the manufacturing yield can be greatly improved. Further, since the voltage shift can be suppressed by the waveform shaping method, there is an effect that the display contrast can be improved without sacrificing the pixel aperture ratio because it is not necessary to increase the auxiliary capacity as in the prior art.

  Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 shows a circuit configuration example for carrying out the first driving method according to the present invention. The active matrix type liquid crystal display device includes a display unit including liquid crystal pixels LP arranged in a matrix and pixel transistors Tr that drive the individual liquid crystal pixels LP. In the figure, only one column of liquid crystal pixels is shown. A vertical scanning circuit 1 is connected to the gate electrode G of each pixel transistor Tr through gate lines X1, X2, X3, X4,..., And a gate pulse GP is applied in a line sequential manner to select the pixel transistor Tr. Do. Further, the horizontal drive circuit 2 is connected to the drain electrode of each pixel transistor Tr via a signal line Ym, and the image signal Vsig is written to each liquid crystal pixel LP via the selected pixel transistor Tr.

  The vertical scanning circuit 1 includes a shift register 3. This shift register 3 has a structure in which D-type flip-flops 4 are connected in multiple stages. Each D-type flip-flop 4 is composed of a pair of inverters 5 and 6 whose output terminals are commonly connected. Each inverter is connected to the power supply VVDD side via a P-channel type drive transistor 7 and is connected to the ground side via an N-channel type drive transistor 8. The pair of drive transistors 7 and 8 are turned on in response to the shift clock pulses VCK1 and VCK2 and their inverted pulses to drive the inverter. The inverters 5 and 6 driven in this way are called so-called clocked inverters. The input terminal of the third inverter 9 is connected to the commonly connected output terminal of the pair of inverters 5 and 6. At the output terminal of the third inverter 9, the output pulse of the D flip-flop at each stage appears. This output pulse is also used as an input to the D flip-flop at the next stage. By inputting the start signal VST to the D-type flip-flop at the first stage, the shift register 3 outputs an output pulse whose phase is shifted by a half cycle sequentially for each stage. A gate pulse GP is obtained by logically processing the output pulse of the stage and the output pulse of the previous stage by the NAND gate element 10 and then inverting it by the inverter 11.

  In this embodiment, the output inverter 11 has an asymmetric structure. That is, the ratio W / L of the channel width W and the channel length L of the N-channel transistor 12 is set smaller than that of the P-channel transistor 13. In other words, the current capacity of the N-channel transistor 12 is smaller than the current capacity of the P-channel transistor 13. When the gate pulse GP rises from a low level to a high level, the P-channel transistor 13 is turned on, so that it rises sharply. On the other hand, when the gate pulse GP falls, the N-channel transistor 12 becomes conductive, but since the current capacity is small, the fall is smooth. Accordingly, the vertical scanning circuit 1 includes means for suppressing a voltage shift of the image signal Vsig written in the pixel LP by smoothly lowering the gate pulse GP.

  FIG. 3 shows a circuit configuration for carrying out the second driving method according to the present invention. Basically, it is similar to the circuit configuration shown in FIG. 2 described above, and corresponding parts are denoted by the same reference numerals and reference numerals for easy understanding. The difference is that the P-channel driving transistor 7 of each D-type flip-flop 4 is not directly connected to the power supply line VVDD, but is connected to the middle point of a pair of voltage-dividing resistors R1 and R2 connected in series. It is. One end of the series-connected voltage dividing resistors R1 and R2 is connected to the power supply line VVDD, and the other end is connected to the ground side via the switching transistor 14. A control voltage VCKX is periodically applied to the gate electrode of the switching transistor 14. When the switching transistor 14 is in the OFF state, the power supply voltage is supplied to the shift register 3 as it is, and the voltage level of each gate pulse GP becomes equal to the power supply voltage. On the other hand, when the switching transistor 14 is turned on, the voltage divided by the ratio of R1 and R2 is supplied to the shift register 3, and the voltage level of the gate pulse GP is lowered accordingly.

  In this embodiment, the gate driver portion including the shift register 3, the NAND gate circuit 10 and the inverter 11 in the entire configuration of the vertical scanning circuit 1 is formed in the substrate of the active matrix type liquid crystal display device. On the other hand, a power supply circuit for supplying a power supply voltage to the shift register 3 and a clock driver for supplying clock pulses VCK1, VCK2, etc. are provided outside the substrate of the active matrix liquid crystal display device. In addition, in this embodiment, the switching transistor 14 and the voltage dividing resistors R1 and R2 for switching the power supply voltage are formed in the substrate. However, the present invention is not limited to such a structure. In some cases, the power supply voltage of an externally connected power supply circuit may be switched periodically.

  Finally, the operation of the circuit shown in FIG. 3 will be described in detail with reference to FIG. The control voltage VCKX applied to the gate electrode of the switching transistor 14 changes in level in a pulse shape according to the horizontal synchronization signal. In this example, the horizontal period is set to 63.5 μs, which corresponds to the selection period per gate line. The control voltage VCKX changes to a high level for 6 to 8 μs in the final part of each horizontal period. This time is set so as not to affect the image signal writing operation within the selection period. That is, the control voltage VCKX is switched to the high level when the image signal has been written to the pixels on the selected gate line in a dot sequential manner. Since the switching transistor 14 is turned on when the control voltage VCKX becomes a high level, the level of the power supply voltage supplied to the shift register 3 is lowered from, for example, VVDD set to 13.5V to about 8.5V. This amount of decrease is set by appropriately determining the ratio of the pair of voltage dividing resistors R1 and R2.

  In accordance with the fluctuation of the power supply voltage, for example, the level of the nth gate pulse GP (n) changes stepwise from 13.5V to 8.5V within one horizontal period. In the next horizontal period, a gate pulse GP (n + 1) corresponding to the (n + 1) th gate line is generated, and its level changes in a stepwise manner. During this time, the polarity of the image signal Vsig is alternately inverted with respect to the potential Vcom of the counter electrode every horizontal period. So-called 1H inversion driving is performed. According to such an operation, the vertical scanning circuit suppresses the voltage shift of the image signal Vsig written in the pixel by lowering the voltage level of the gate pulse and then lowering it immediately before stopping the application of the individual gate pulses GP. I can do it.

  As described above, the voltage shift of the image signal can be suppressed by smoothing the fall of the gate pulse or making it stepwise. Such waveform shaping of the gate pulse can be achieved by devising the configuration of the vertical scanning circuit. In this case, the circuit portion formed in the substrate of the active matrix liquid crystal display device may be modified, or the external circuit portion may be adjusted. However, when the waveform shaping of the gate pulse is performed in the external circuit portion, the method of changing in a staircase pattern is simpler in circuit and has better controllability than the method of dulling the fall.

It is a schematic diagram showing a driving method of the active matrix type liquid crystal display device according to the present invention. It is a circuit diagram which shows the structural example for enforcing the drive method concerning this invention. It is a circuit diagram which shows the other structural example for similarly implementing the drive method concerning this invention. 4 is a timing chart for explaining the operation of the circuit shown in FIG. 3. It is an equivalent circuit diagram which shows the structure of the conventional active matrix type liquid crystal display device. It is a schematic diagram for demonstrating the subject of the drive method of the conventional active matrix type liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Vertical scanning circuit, 2 ... Horizontal scanning circuit, 3 ... Shift register, 4 ... D type flip-flop, 11 ... Inverter, 12 ... N channel type transistor, 13 ... .P-channel type transistors, 14 ... switching transistors

Claims (4)

A liquid crystal pixel arranged in a matrix, a pixel transistor for driving each liquid crystal pixel, and an auxiliary capacitor,
The liquid crystal pixel and the auxiliary capacitor are connected to the pixel transistor;
The pixel transistor has a source electrode connected to the liquid crystal pixel and the auxiliary capacitor, a drain electrode connected to the signal line, and a gate electrode connected to the gate line.
Further, a vertical scanning circuit that performs a selection operation by sequentially applying a gate pulse to the gate electrode of each pixel transistor via a gate line, and a horizontal drive circuit that writes an image signal to each liquid crystal pixel via the signal line and the selected pixel transistor For an active matrix liquid crystal display device with
Driving to display an image by applying a gate pulse to the gate electrode of the pixel transistor during the selection period and writing the image signal to each liquid crystal pixel and holding the written image signal by stopping the application of the gate pulse during the non-selection period In the method
The vertical scanning circuit has an output inverter composed of an N-channel transistor and a P-channel transistor for outputting the gate pulse to each gate line,
The output inverter has an asymmetric structure, and the ratio of the channel width to the channel length of the N-channel transistor is set smaller than that of the P-channel transistor,
By using the asymmetric structure of the output inverter, the gate pulse is sharply raised when transitioning from the non-selection period to the selection period, and the gate pulse is smoothly lowered when transitioning from the selection period to the non-selection period, A driving method of an active matrix type liquid crystal display device, characterized by suppressing a voltage shift of a written image signal. A liquid crystal pixel arranged in a matrix, a pixel transistor for driving each liquid crystal pixel, and an auxiliary capacitor,
The liquid crystal pixel and the auxiliary capacitor are connected to the pixel transistor;
The pixel transistor has a source electrode connected to the liquid crystal pixel and an auxiliary capacitor, a drain electrode connected to a signal line, a gate electrode connected to a gate line,
Further, a vertical scanning circuit that performs a selection operation by sequentially applying a gate pulse to the gate electrode of each pixel transistor via a gate line, and a horizontal drive circuit that writes an image signal to each liquid crystal pixel via the signal line and the selected pixel transistor For an active matrix liquid crystal display device with
Driving to display an image by applying a gate pulse to the gate electrode of the pixel transistor during the selection period and writing the image signal to each liquid crystal pixel and holding the written image signal by stopping the application of the gate pulse during the non-selection period In the method
The vertical scanning circuit includes a voltage dividing resistor and a switching transistor for switching a power supply voltage level.
When transitioning from the non-selection period to the selection period, the gate pulse rises sharply,
The image signal written by controlling the voltage dividing resistor and switching transistor for switching the level of the power supply voltage, and immediately lowering the voltage level of the gate pulse immediately before shifting from the selection period to the non-selection period. A method of driving an active matrix liquid crystal display device, characterized in that the voltage shift of the active matrix liquid crystal display device is suppressed. Having liquid crystal pixels arranged in a matrix, pixel transistors for driving the individual liquid crystal pixels, and auxiliary capacitors;
The liquid crystal pixel and the auxiliary capacitor are connected to the pixel transistor;
The pixel transistor has a source electrode connected to the liquid crystal pixel and an auxiliary capacitor, a drain electrode connected to a signal line, a gate electrode connected to a gate line,
A vertical scanning circuit that sequentially applies a gate pulse to the gate electrode of each pixel transistor via a gate line and performs a selection operation; and a horizontal drive circuit that writes an image signal to each liquid crystal pixel via the signal line and the selected pixel transistor; In an active matrix liquid crystal display device comprising:
The vertical scanning circuit sharply raises the gate pulse when applying the gate pulse, and smoothly lowers the gate pulse when stopping the application of the gate pulse, thereby shifting the voltage shift of the written image signal. Has a means to suppress,
The suppression means is an output inverter composed of an N-channel transistor and a P-channel transistor for outputting the gate pulse to each gate line, and the output inverter has an asymmetric structure, and the N-channel transistor An active matrix liquid crystal display device characterized in that the ratio of the channel width to the channel length is set smaller than that of a P-channel transistor. Having liquid crystal pixels arranged in a matrix, pixel transistors for driving the individual liquid crystal pixels, and auxiliary capacitors;
The liquid crystal pixel and the auxiliary capacitor are connected to the pixel transistor;
The pixel transistor has a source electrode connected to the liquid crystal pixel and an auxiliary capacitor, a drain electrode connected to a signal line, a gate electrode connected to a gate line,
A vertical scanning circuit that sequentially applies a gate pulse to the gate electrode of each pixel transistor via a gate line and performs a selection operation; and a horizontal drive circuit that writes an image signal to each liquid crystal pixel via the signal line and the selected pixel transistor; In an active matrix liquid crystal display device comprising:
The vertical scanning circuit sharply raises the gate pulse when applying the gate pulse, and
Immediately before stopping the application of the gate pulse, it has means for suppressing the voltage shift of the written image signal by lowering the voltage level of the gate pulse and then lowering it.
The active matrix liquid crystal display device characterized in that the suppressing means comprises a voltage dividing resistor and a switching transistor for switching the level of a power supply voltage supplied to the vertical scanning circuit.

Images