JP2005020028A - Method of connecting between terminals and connection structure between terminals - Google Patents

Method of connecting between terminals and connection structure between terminals Download PDF

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JP2005020028A
JP2005020028A JP2004293299A JP2004293299A JP2005020028A JP 2005020028 A JP2005020028 A JP 2005020028A JP 2004293299 A JP2004293299 A JP 2004293299A JP 2004293299 A JP2004293299 A JP 2004293299A JP 2005020028 A JP2005020028 A JP 2005020028A
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terminals
terminal
conductive particles
semiconductor chip
conductive film
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Kazutaka Shibata
和孝 柴田
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a simple method of electrically connecting between both terminals more surely, in the state that terminals are opposed to each other. <P>SOLUTION: A connection structure between terminals in which a first terminal 11 and a second terminal 21, which are opposed to each other, are electrically connected through an anisotropy conductive film 30 which is constituted by distributing conductive particles 32 in heat adhesive resin film, wherein first and second terminals 11, 21 have surfaces made of, at least, gold, nickel, tin, aluminum or cooper, and a conductive particles 32 have surface made of, at least, gold or nickel, and bonding the conductive particles 32 and the first terminal 11 and/or bonding the conductive particles 32 and the second terminal 21 are made by alloying. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、端子間の接続構造に関し、たとえば、能動面に複数の端子が形成されたＩＣなどの半導体チップをいわゆるチップ・オン・ボード実装方式でプリント配線基板上に実装する場合などに好適に採用しうるものである。   The present invention relates to a connection structure between terminals, and is suitable for, for example, mounting a semiconductor chip such as an IC having a plurality of terminals formed on an active surface on a printed wiring board by a so-called chip-on-board mounting method. It can be adopted.

図８は、チップ・オン・ボード方式で半導体チップ１０を基板２０上に実装した状態の拡大断面図である。半導体チップ１０の能動面には、複数の端子パッド１１がやや突出状に形成されている。一方、プリント配線基板２０の表面には、上記半導体チップ１０の各端子パッド１１の配置と対応して、複数の端子２１が露出形成されている。チップ・オン・ボード方式とは、上記半導体チップ１０の能動面を異方性導電膜３０を介して基板２０に対向させてこれに加熱圧接させ、対向する端子１１，２１どうしを導電接続し、その余の領域を絶縁性をたもったまま相互接着する方式である。   FIG. 8 is an enlarged cross-sectional view of the semiconductor chip 10 mounted on the substrate 20 by the chip-on-board method. On the active surface of the semiconductor chip 10, a plurality of terminal pads 11 are formed in a slightly protruding shape. On the other hand, a plurality of terminals 21 are exposed and formed on the surface of the printed wiring board 20 corresponding to the arrangement of the terminal pads 11 of the semiconductor chip 10. In the chip-on-board method, the active surface of the semiconductor chip 10 is opposed to the substrate 20 via the anisotropic conductive film 30 and heated and pressed against it, and the opposing terminals 11 and 21 are conductively connected. This is a method in which the remaining regions are bonded to each other while maintaining insulation.

上記異方性導電膜３０は、接着性の樹脂膜３１中に導電性の粒子３２を分散させた構造をもっている。導電性の粒子３２としては、金属球のほか、たとえば樹脂製ボールの表面にニッケルメッキを施したもの、あるいはニッケルメッキの上にさらに金メッキを施したものなどが使用される。   The anisotropic conductive film 30 has a structure in which conductive particles 32 are dispersed in an adhesive resin film 31. As the conductive particles 32, in addition to metal spheres, for example, the surface of a resin ball with nickel plating or the nickel plating with further gold plating is used.

加熱状態において相互間に上記の異方性導電膜３０を介在させた上で上記半導体チップ１０と基板２０間に所定の圧力を加えると、図８に表れているように、半導体チップ１０の端子１１と基板２０上の端子２１間で軟化させられた異方性導電膜３０が圧し潰され、上記導電性の粒子３２が両端子１１，２１間に接触させられ、これにより両端子１１，２１間の電気的接続が図られる。異方性導電膜３０のうち、上記のようにして圧し潰されない領域は、依然として導電性の粒子３２は分散状態にあるため、この領域での絶縁性は維持される。同時に、半導体チップ１０の能動面と基板２０間は、上記異方性導電膜３０のもつ接着力によって相互に接着される。このように、上記した実装方式においては、異方性導電膜３０を介在させた状態で半導体チップ１０と基板２０間を押圧するという簡単な操作をするだけで、必要な箇所のみの電気的導通をはかりながら、半導体チップ１０を基板２０に実装することができるのであり、いわゆるチップボンディングとワイヤボンディングとによって基板上に半導体チップを実装する場合に比較して、著しく簡便な実装方式である。   When a predetermined pressure is applied between the semiconductor chip 10 and the substrate 20 with the anisotropic conductive film 30 interposed between them in a heated state, as shown in FIG. The anisotropic conductive film 30 softened between the terminal 11 and the terminal 21 on the substrate 20 is crushed, and the conductive particles 32 are brought into contact between the terminals 11 and 21, whereby the both terminals 11 and 21 are contacted. Electrical connection between them is achieved. In the anisotropic conductive film 30, in the region that is not crushed as described above, the conductive particles 32 are still in a dispersed state, so that the insulation in this region is maintained. At the same time, the active surface of the semiconductor chip 10 and the substrate 20 are bonded to each other by the adhesive force of the anisotropic conductive film 30. As described above, in the above-described mounting method, electrical conduction only at necessary portions can be achieved by simply performing a simple operation of pressing between the semiconductor chip 10 and the substrate 20 with the anisotropic conductive film 30 interposed. The semiconductor chip 10 can be mounted on the substrate 20 while measuring, which is a remarkably simple mounting method compared to the case where the semiconductor chip is mounted on the substrate by so-called chip bonding and wire bonding.

ところで、上記した従来の手法による異方性導電膜３０を用いた端子間の接続方法においては、単に異方性導電膜３０を介して接続するべき両者間を熱圧迫させるだけであるため、とくに電気的接続の安定性に欠けるという問題がある。   By the way, in the connection method between the terminals using the anisotropic conductive film 30 according to the above-described conventional method, since only the two to be connected via the anisotropic conductive film 30 is merely thermally compressed, There is a problem that the electrical connection is not stable.

すなわち、加熱温度の管理、および、圧接力の管理を適正に行わないと、異方性導電膜３０内の導電性粒子３２が導通を図るべき両端子１１，２１に適正に接触しない状態が生まれるおそれがある。また、半導体チップを実装するべき基板がガラスエポキシをベースとするプリント配線基板である場合等には、この基板に撓みや反りが生じている場合があり、このような場合には、上記のような電気的接続不良がより起こりやすい。   That is, unless the management of the heating temperature and the pressure contact force are properly performed, a state in which the conductive particles 32 in the anisotropic conductive film 30 do not properly contact the terminals 11 and 21 to be conducted is created. There is a fear. In addition, when the substrate on which the semiconductor chip is to be mounted is a printed wiring board based on glass epoxy, the substrate may be bent or warped. In such a case, as described above Electrical connection failure is more likely to occur.

特開平５−９４８４４号公報Japanese Patent Laid-Open No. 5-94844

本発明は、このような事情のもとで考え出されたものであって、端子どうしを対向させた状態において、両端子間のより確実な電気的接続を図ることができるあらたな接続構造を提供することをその課題としている。   The present invention has been conceived under such circumstances, and has a new connection structure capable of achieving a more reliable electrical connection between both terminals in a state where the terminals are opposed to each other. The issue is to provide.

上記の課題を解決するため、本発明では、次の技術的手段を講じている。   In order to solve the above problems, the present invention takes the following technical means.

本発明の第１の側面によって提供される端子間の接続方法は、第１の端子と、第２の端子とを互いに対向させ、これら端子間に異方性導電膜を介装するとともに、上記第１の端子と第２の端子を互いに圧し付けるとともに、両端子間に超音波振動を付与する端子間の接続方法であって、上記第１及び第２の端子は、少なくともその表面が、金、ニッケル、錫、アルミまたは銅により形成されており、かつ上記導電性粒子は、少なくともその表面が金またはニッケルにより形成されていることを特徴としている。   According to the connection method provided between the terminals provided by the first aspect of the present invention, the first terminal and the second terminal are opposed to each other, and an anisotropic conductive film is interposed between the terminals. The first terminal and the second terminal are pressed against each other, and are connected to each other by applying ultrasonic vibration between the two terminals, and at least the surface of the first and second terminals is made of gold. The conductive particles are formed of nickel, tin, aluminum, or copper, and at least the surface thereof is formed of gold or nickel.

上記異方性導電膜は、従来のチップ・オン・ボード方式で半導体チップを基板に実装する場合に用いるものと基本的に同じである。すなわち、接着性の樹脂膜中に導電性の粒子を分散させた構造をもったものである。導電性の粒子は、樹脂膜中に分散されているが故に、自然状態においては、各導電性の粒子は絶縁性の樹脂によって互いに隔絶されており、したがって、この異方性導電膜の両面間は、絶縁状態にある。しかし、この異方性導電膜の選択された領域に好ましくは加熱状態において厚み方向の圧迫力を加えてこの膜を圧し潰すと、上記導電性の粒子の表面が圧し潰されて厚みが減少した膜の両面に露出するようになり、この粒子を挟むように対向する面が互いに電気的に導通させられる。   The anisotropic conductive film is basically the same as that used when a semiconductor chip is mounted on a substrate by a conventional chip-on-board method. That is, it has a structure in which conductive particles are dispersed in an adhesive resin film. Since the conductive particles are dispersed in the resin film, in the natural state, the conductive particles are isolated from each other by the insulating resin. Is in an insulated state. However, when the film is crushed by applying a compressive force in the thickness direction to the selected region of the anisotropic conductive film, preferably in the heated state, the surface of the conductive particles is crushed and the thickness is reduced. The film is exposed on both surfaces of the film, and the surfaces facing each other so as to sandwich the particles are electrically connected to each other.

本発明においては、第１の端子と第２の端子とを電気的に接続するにあたって、両端子間に介在させられる上記の異方性導電膜を両端子間で圧迫させるだけでなく、超音波振動を加えている。好ましくは、この場合、上記第１および第２の端子とその間に介装させられる異方性導電膜は、加熱状態におかれる。第１の端子と第２の端子の相互間に超音波振動を与えると、これらの間に圧し潰された格好で介在する異方性導電膜中の導電性粒子と各端子間は、振動摩擦によって確実な電気的接続が図られるとともに、両端子および導電性粒子の被膜金属を選択することにより、これらの相互接触部には共晶合金が生成され、これにより、両端子と導電性粒子間のより確実な電気的接続が図られる。第１の端子が形成された面と、第２の端子が形成された面との間は、異方性導電膜による接着により、相互に固定される。その結果、本発明に係る端子間の接続方法によれば、従来の異方性導電膜を用いた接続法に比較し、端子間の電気的接続の安定性が高まる。このことは、半導体チップをチップ・オン・ボード実装法によって基板上に実装する場合、リードフレーム上に半導体チップをボンディングする場合等に等しくあてはまる効果である。なお、異方性導電膜を介在させた状態での両端子の圧迫操作および超音波付与操作中、好ましくは加熱状態とすることが好ましいが、加熱をすることなくとも、圧迫操作と超音波付与操作をするだけで、そのエネルギを適正に選択することにより、振動摩擦による昇温が得られ、両端子が形成された面どうしが実質的に熱接着されることが確認されている。さらに、本発明によれば、上記第１または第２の端子と上記導電性粒子とを合金化結合させるのに好適である。   In the present invention, when the first terminal and the second terminal are electrically connected, the anisotropic conductive film interposed between the two terminals is not only compressed between the two terminals, but also the ultrasonic wave. Adding vibration. Preferably, in this case, the first and second terminals and the anisotropic conductive film interposed therebetween are placed in a heated state. When ultrasonic vibration is applied between the first terminal and the second terminal, there is vibration friction between the conductive particles in the anisotropic conductive film interposed between the first terminal and the second terminal. As a result, a reliable electrical connection can be achieved, and by selecting a coating metal of both terminals and conductive particles, a eutectic alloy is formed at these mutual contact portions, and thereby, between the two terminals and the conductive particles. A more reliable electrical connection can be achieved. The surface on which the first terminal is formed and the surface on which the second terminal is formed are fixed to each other by adhesion with an anisotropic conductive film. As a result, according to the connection method between the terminals according to the present invention, the stability of the electrical connection between the terminals is enhanced as compared with the connection method using the conventional anisotropic conductive film. This is an effect that is equally applicable when a semiconductor chip is mounted on a substrate by a chip-on-board mounting method, or when a semiconductor chip is bonded on a lead frame. In addition, it is preferable to be in a heated state during the compression operation and ultrasonic application operation of both terminals with an anisotropic conductive film interposed therebetween, but the compression operation and ultrasonic application are performed without heating. It has been confirmed that, by simply selecting the energy, by appropriately selecting the energy, a temperature rise due to vibration friction can be obtained, and the surfaces on which both terminals are formed are substantially thermally bonded. Furthermore, according to the present invention, it is suitable for alloying and bonding the first or second terminal and the conductive particles.

本発明の第２の側面によって提供される端子間の接続構造は、互いに対向する第１の端子と第２の端子とが、熱接着性樹脂膜中に導電性粒子を分散させてなる異方性導電膜を介して導電接続されている端子間の接続構造であって、上記第１及び第２の端子は、少なくともその表面が、金、ニッケル、錫、アルミまたは銅により形成されており、かつ上記導電性粒子は、少なくともその表面が金またはニッケルにより形成されているとともに、上記導電性粒子と第１の端子間および／または上記導電性粒子と第２の端子間は、合金化結合されていることを特徴としている。   In the connection structure between terminals provided by the second aspect of the present invention, the first terminal and the second terminal facing each other are anisotropically formed by dispersing conductive particles in the thermal adhesive resin film. A connection structure between terminals that are conductively connected via a conductive conductive film, wherein the first and second terminals have at least a surface formed of gold, nickel, tin, aluminum, or copper, The conductive particles have at least a surface formed of gold or nickel, and the conductive particles and the first terminal and / or the conductive particles and the second terminal are alloyed and bonded. It is characterized by having.

このような構成によれば、端子金属と異方性導電膜中の導電性粒子の金属を適当に選択するとともに、導電接続するべき両端子間に超音波振動を与えることによって達成される。したがって、第１の端子と第２の端子間の導電接続の安定性が高度に達成される。   According to such a configuration, it is achieved by appropriately selecting the terminal metal and the metal of the conductive particles in the anisotropic conductive film, and applying ultrasonic vibration between both terminals to be conductively connected. Therefore, the stability of the conductive connection between the first terminal and the second terminal is highly achieved.

本発明のその他の特徴および利点は、図面を参照して以下に行う詳細な説明から、より明らかとなろう。   Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the drawings.

以下、本発明の好ましい実施の形態につき、図面を参照して具体的に説明する。   Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

図１ないし図３は、本発明をプリント配線基板上に半導体チップをチップ・オン・ボード実装方式によって実装する場合に適用する場合を示している。なお、これらの図において、図８に示した従来例と同等の部材および部分には同一の符号を付してある。   1 to 3 show a case where the present invention is applied to a case where a semiconductor chip is mounted on a printed wiring board by a chip-on-board mounting method. In these drawings, members and portions equivalent to those of the conventional example shown in FIG. 8 are denoted by the same reference numerals.

ＩＣチップなどの半導体チップ１０の能動面には、アルミニウムパッド上に金メッキまたはニッケルメッキによるバンプ１１が形成された恰好で、複数の第１の端子１１が形成されている。この半導体チップ１０の能動面における上記第１の端子１１以外の領域は、パシペーションによって絶縁されている。   On the active surface of the semiconductor chip 10 such as an IC chip, a plurality of first terminals 11 are preferably formed by forming bumps 11 made of gold plating or nickel plating on an aluminum pad. The region other than the first terminal 11 on the active surface of the semiconductor chip 10 is insulated by the passivation.

一方、上記半導体チップ１０が搭載されるべきプリント配線基板２０は、ガラスエポキシなどの基材の表面に銅被膜を形成するとともにこれに対して所定のパターンエッチングを施すなどして配線パターンが形成されており、この配線パターン２１に導通するようにして、ニッケルメッキおよび金メッキが施された恰好で、上記第１の端子１１と対応する複数の第２の端子２１が形成されている。このように露出させられる第２の端子２１以外の基板２０上の領域は、通常、グリーンレジストと呼ばれる絶縁性の樹脂被膜によって覆われる。第２の端子２１は、ニッケルメッキおよび金メッキが施されているが故に、基板表面に対してやや突出状となる。   On the other hand, the printed wiring board 20 on which the semiconductor chip 10 is to be mounted has a wiring pattern formed by forming a copper film on the surface of a base material such as glass epoxy and performing a predetermined pattern etching on the copper film. A plurality of second terminals 21 corresponding to the first terminals 11 are formed so as to be electrically connected to the wiring pattern 21 and plated with nickel and gold. The regions on the substrate 20 other than the second terminals 21 exposed in this way are usually covered with an insulating resin film called a green resist. Since the second terminal 21 is nickel-plated and gold-plated, it has a slightly protruding shape with respect to the substrate surface.

上記プリント配線基板２０には、図１および図２に示すようにして、異方性導電膜３０を介して、能動面を下向きにした半導体チップ１０が、第１の端子１１と上記基板２０上の第２の端子２１とが対応するように位置決めされながら、所定の圧力で押圧される。このとき、プリント配線基板２０が載置される支持台４０は、その内部に組み込まれたヒータ（図示略）によって、たとえば１８０℃程度に加熱させられる。   As shown in FIGS. 1 and 2, the printed circuit board 20 includes a semiconductor chip 10 with an active surface facing downward through an anisotropic conductive film 30, and the first terminal 11 and the substrate 20. The second terminal 21 is pressed with a predetermined pressure while being positioned so as to correspond to the second terminal 21. At this time, the support base 40 on which the printed wiring board 20 is placed is heated to, for example, about 180 ° C. by a heater (not shown) incorporated therein.

上記半導体チップ１０の基板２０への押圧は、図２に示すように、超音波ホーン５０を用いて行われる。すなわち、実施形態においては、上記半導体チップ１０は、基板２０に対して、単に熱圧着されるだけではなく、超音波振動を与えられる。   The semiconductor chip 10 is pressed against the substrate 20 using an ultrasonic horn 50 as shown in FIG. That is, in the embodiment, the semiconductor chip 10 is not only simply thermocompression bonded to the substrate 20 but is also subjected to ultrasonic vibration.

上記異方性導電膜３０は、たとえば、エポキシ系の樹脂膜３１中に導電性粒子３２を分散させたものである。導電性粒子３２としては、金属粒子が用いられるほか、樹脂粒子の表面に金メッキまたはニッケルメッキが施されたものなどが使用される。導電膜の自然状態での厚みは、たとえば３０〜５０μｍ、導電性粒子の球径はたとえば５μｍである。   The anisotropic conductive film 30 is obtained by, for example, dispersing conductive particles 32 in an epoxy resin film 31. As the conductive particles 32, metal particles are used, and the resin particles whose surfaces are plated with gold or nickel are used. The thickness of the conductive film in the natural state is, for example, 30 to 50 μm, and the spherical diameter of the conductive particles is, for example, 5 μm.

異方性導電膜３０は、その選択されさた領域が厚み方向に加熱圧迫させられると、樹脂成分が軟化して圧し潰される。上記の例においては、半導体チップ１０側の第１の端子１１および基板２０側の第２の端子２１がともに突出状となっているので、異方性導電膜３０のうち、上記対向状の第１の端子１１と第２の端子２１との間に挟まれる領域が選択的に圧し潰され、その結果、樹脂中に分散させられている導電性粒子３２が半導体チップ１０側の第１の端子１１と、基板２０側の第２の端子２１に接触させられる。それだけではなく、本発明においては、基板２０と半導体チップ１０との間に所定のエネルギによる超音波振動を与えている。そのため、上記導電性粒子３２と第１の端子１１間、および上記導体粒子３２と第２の端子２１間に振動摩擦による確実な導電接触状態が得られる。異方性導電膜３０のうち、上記第１の端子１１と第２の端子２１とに挟まれない領域は、押し潰されないか、または、圧し潰される程度が低いため、内部の導電性粒子３２は依然として異方性導電膜３０の厚み方向に分散された状態となり、したがって、半導体チップ１０と基板２０の両表面における上記両端子１１，２１以外の領域間の絶縁性が維持される。   When the selected region of the anisotropic conductive film 30 is heated and pressed in the thickness direction, the resin component is softened and crushed. In the above example, since the first terminal 11 on the semiconductor chip 10 side and the second terminal 21 on the substrate 20 side are both protruding, the anisotropic conductive film 30 includes the opposing first terminal 11. The region sandwiched between the first terminal 11 and the second terminal 21 is selectively crushed, and as a result, the conductive particles 32 dispersed in the resin become the first terminal on the semiconductor chip 10 side. 11 and the second terminal 21 on the substrate 20 side. In addition, in the present invention, ultrasonic vibration with a predetermined energy is applied between the substrate 20 and the semiconductor chip 10. Therefore, a reliable conductive contact state by vibration friction is obtained between the conductive particles 32 and the first terminals 11 and between the conductive particles 32 and the second terminals 21. In the anisotropic conductive film 30, a region not sandwiched between the first terminal 11 and the second terminal 21 is not crushed or is not crushed. Is still dispersed in the thickness direction of the anisotropic conductive film 30, and therefore, insulation between regions other than the terminals 11 and 21 on both surfaces of the semiconductor chip 10 and the substrate 20 is maintained.

上記の例では、第１の端子１１、第２の端子２１および異方性導電膜３０中の導電性粒子３２の表面がともに金またはニッケルであるため、上記のような超音波エネルギの付与により、これらの金表面が原子レベルで再結晶し、相互間に高度な電気的導通性が得られる。   In the above example, the surfaces of the conductive particles 32 in the first terminal 11, the second terminal 21, and the anisotropic conductive film 30 are all gold or nickel. These gold surfaces recrystallize at the atomic level, and a high electrical conductivity is obtained between them.

さらに、上記第１の端子１１または第２の端子２１の表面を錫、アルミ、または銅とすると、導電性粒子３２の金表面との間に共晶合金部分が形成され、この場合もまた、相互の高度な電気的導通性が得られる。   Furthermore, when the surface of the first terminal 11 or the second terminal 21 is made of tin, aluminum, or copper, a eutectic alloy portion is formed between the gold surfaces of the conductive particles 32. In this case, too, A high degree of mutual electrical continuity is obtained.

上記の例は、半導体チップ１０をプリント配線基板２０上に実装する場合に本発明を適用したものであるが、本発明はこれに限らず、図４および図５に示すように、半導体チップ１０をリードフレーム６０上にボンディングする場合にも適用できる。リードフレーム６０には、上記半導体チップ１０上に形成した第１の端子１１と接続するべき第２の端子２１としての内部リード６１が形成されており、その表面には、好ましくは、金メッキまたはニッケルメッキが施される。このリードフレーム６０は、たとえば、ヒータブロック７０上に支持され、その上に上記の異方性導電膜３０を介在させた格好で半導体チップ１０がその能動面を下にして位置決め載置され、そして、図５に示すように、上記と同様にこの半導体チップ１０が、超音波ホーン５０によって超音波振動を与えられながら、上記リードフレーム６０に向けて所定の圧力で押圧される。   In the above example, the present invention is applied when the semiconductor chip 10 is mounted on the printed wiring board 20, but the present invention is not limited to this, and as shown in FIGS. It can also be applied to bonding on the lead frame 60. The lead frame 60 is formed with internal leads 61 as the second terminals 21 to be connected to the first terminals 11 formed on the semiconductor chip 10, and the surface thereof is preferably gold-plated or nickel. Plating is applied. For example, the lead frame 60 is supported on the heater block 70, and the semiconductor chip 10 is positioned and mounted with the anisotropic conductive film 30 interposed therebetween, with its active surface facing down. As shown in FIG. 5, the semiconductor chip 10 is pressed toward the lead frame 60 with a predetermined pressure while being subjected to ultrasonic vibration by the ultrasonic horn 50 as described above.

この場合においても、上記と同様に、リードフレーム６０の内部リード６１と半導体チップ１０の端子との間が、異方性導電膜３０を介してより確実に導通させられる。   Even in this case, similarly to the above, the internal lead 61 of the lead frame 60 and the terminal of the semiconductor chip 10 are more reliably connected via the anisotropic conductive film 30.

上記の各例は、いずれも、異方性導電膜３０を介して対向する第１の端子１１と第２の端子２１間を選択的に導通接続するものであるが、本発明は、これに限られない。実験によれば、図６および図７に示すように、単に第１の端子１１（たとえば半導体チップ１０上の端子１１）と第２の端子２１（たとえばプリント配線基板２０上の端子２１）間にたとえばエポキシ系の樹脂膜３５を介在させ、適度に加熱させた状態において、超音波を付与しつつ両端子間を圧接させることにより、対向する第１の端子１１と第２の端子２１との間が適正に導通させられうることが判明している。この場合、両端子１１，２１以外の領域は、圧し潰されない樹脂膜によって絶縁性が保持される。   In each of the above examples, the first terminal 11 and the second terminal 21 facing each other through the anisotropic conductive film 30 are selectively conductively connected. Not limited. According to the experiment, as shown in FIGS. 6 and 7, simply between the first terminal 11 (for example, the terminal 11 on the semiconductor chip 10) and the second terminal 21 (for example, the terminal 21 on the printed wiring board 20). For example, in a state where the epoxy resin film 35 is interposed and heated moderately, the two terminals 21 and 21 are opposed to each other by pressing the terminals while applying ultrasonic waves. Has been found to be able to conduct properly. In this case, the insulating properties of the regions other than the terminals 11 and 21 are maintained by the resin film that is not crushed.

すなわち、図７に詳示するように、第１の端子１１と第２の端子２１間を加熱圧接させながら、両者間に超音波振動を与えると、両端子１１，２１間の樹脂膜が超音波振動による摩擦熱によってより流動性が高められるとともに、両端子が相互にスライド方向に振動することによって上記流動性が高められた樹脂が両端子１１，２１間のすきまから押し出され、その結果、第１の端子１１と第２の端子２１との直接接触が達成されるのである。   That is, as shown in detail in FIG. 7, when ultrasonic vibration is applied between the first terminal 11 and the second terminal 21 while being heated and pressed, the resin film between the terminals 11 and 21 becomes super The fluidity is further enhanced by frictional heat due to the sonic vibration, and the resin whose fluidity is enhanced by the vibration of both terminals in the sliding direction is pushed out from the gap between the terminals 11 and 21, as a result. Direct contact between the first terminal 11 and the second terminal 21 is achieved.

そして、この方法は、上記のように、半導体チップ１０をプリント配線基板２０上に搭載する場合のみならず、半導体チップ１０をリードフレーム上にボンディングする場合にも同様に適用できる。   This method can be applied not only when the semiconductor chip 10 is mounted on the printed wiring board 20 as described above, but also when the semiconductor chip 10 is bonded on the lead frame.

また、上記の各例では、第１の端子１１と第２の端子２１間を超音波振動をあたえつつ相互に圧接するに際して、外部加熱を併用しているが、外部加熱は、必要に応じて行えばよい。   In each of the above examples, external heating is used together when the first terminal 11 and the second terminal 21 are pressed against each other while applying ultrasonic vibration. However, external heating is performed as necessary. Just do it.

もちろん、この発明の範囲は上述した各実施形態に限定されるものではなく、対向する第１の端子と第２の端子間の電気的接続をする場合のすべてに適用しうる。   Of course, the scope of the present invention is not limited to the above-described embodiments, and can be applied to all cases where electrical connection is made between the first terminal and the second terminal that face each other.

本発明に係る端子間の接続方法の一例の説明図である。It is explanatory drawing of an example of the connection method between the terminals which concerns on this invention. 本発明に係る端子間の接続方法の一例の説明図である。It is explanatory drawing of an example of the connection method between the terminals which concerns on this invention. 本発明に係る端子間の接続構造の一例の拡大断面図である。It is an expanded sectional view of an example of the connection structure between the terminals concerning the present invention. 本発明に係る端子間の接続方法の他の例の説明図である。It is explanatory drawing of the other example of the connection method between the terminals which concerns on this invention. 本発明に係る端子間の接続方法の他の例の説明図である。It is explanatory drawing of the other example of the connection method between the terminals which concerns on this invention. 本発明に係る端子間の接続方法の他の例の説明図である。It is explanatory drawing of the other example of the connection method between the terminals which concerns on this invention. 本発明に係る端子間の接続方法の他の例の説明図である。It is explanatory drawing of the other example of the connection method between the terminals which concerns on this invention. 従来例の説明図である。It is explanatory drawing of a prior art example.

符号の説明Explanation of symbols

１０ 半導体チップ
１１ 第１の端子
２０ 基板
２１ 第２の端子
３０ 異方性導電膜
３１ 樹脂膜
３２ 導電性粒子
３５ 樹脂膜
５０ 超音波ホーン
６０ リードフレーム
７０ ヒータブロック 10 Semiconductor chip 11 First terminal 20 Substrate 21 Second terminal 30 Anisotropic conductive film 31 Resin film 32 Conductive particles 35 Resin film 50 Ultrasonic horn 60 Lead frame 70 Heater block

Claims (2)

第１の端子と、第２の端子とを互いに対向させ、これら端子間に異方性導電膜を介装するとともに、上記第１の端子と第２の端子を互いに圧し付けるとともに、両端子間に超音波振動を付与する端子間の接続方法であって、
上記第１及び第２の端子は、少なくともその表面が、金、ニッケル、錫、アルミまたは銅により形成されており、かつ上記導電性粒子は、少なくともその表面が金またはニッケルにより形成されていることを特徴とする、端子間の接続方法。 The first terminal and the second terminal are opposed to each other, an anisotropic conductive film is interposed between the terminals, the first terminal and the second terminal are pressed against each other, and between the two terminals A connection method between terminals for applying ultrasonic vibration to
The first and second terminals have at least a surface formed of gold, nickel, tin, aluminum, or copper, and the conductive particles have at least a surface formed of gold or nickel. The connection method between the terminals characterized by this. 互いに対向する第１の端子と第２の端子とが、熱接着性樹脂膜中に導電性粒子を分散させてなる異方性導電膜を介して導電接続されている端子間の接続構造であって、
上記第１及び第２の端子は、少なくともその表面が、金、ニッケル、錫、アルミまたは銅により形成されており、かつ上記導電性粒子は、少なくともその表面が金またはニッケルにより形成されているとともに、
上記導電性粒子と第１の端子間および／または上記導電性粒子と第２の端子間は、合金化結合されていることを特徴とする、端子間の接続構造。 A connection structure between terminals in which a first terminal and a second terminal facing each other are conductively connected via an anisotropic conductive film in which conductive particles are dispersed in a heat-adhesive resin film. And
The first and second terminals have at least a surface formed of gold, nickel, tin, aluminum, or copper, and the conductive particles have at least a surface formed of gold or nickel. ,
A connection structure between terminals, wherein the conductive particles and the first terminal and / or the conductive particles and the second terminal are bonded by alloying.
JP2004293299A 2004-10-06 2004-10-06 Method of connecting between terminals and connection structure between terminals Pending JP2005020028A (en)

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JP8349669A Division JPH10189657A (en) 1996-12-27 1996-12-27 Connection between terminals, mounting of semiconductor chip, bonding of semiconductor chip and connection structure between terminals

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192984A (en) * 2007-02-07 2008-08-21 Elpida Memory Inc Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008192984A (en) * 2007-02-07 2008-08-21 Elpida Memory Inc Semiconductor device and method of manufacturing the same

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