JP2005005860A - Switch circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switch circuit apparatus whose cost is suppressed by using a DPDT switch not employing a logic circuit for an antenna changeover switch. <P>SOLUTION: A shunt attached DPDT switch circuit apparatus is controlled by three control terminals CTL 1 to CTL 3 without the need for provision of a logic circuit. Since it is not required to provide the logic circuit, the chip size is decreased, the parts count and the manufacturing cost can be reduced and the manufacturing process can be simplified. Further, provision of a shunt FET and a FET 3 can greatly contribute to the improvement of the isolation. Moreover, provision of a means for isolating first and second switching elements in terms of DC, a means for connecting a gate of the second switching element to ground and a means for connecting a drain or a source of the second switching element to ground or the like can solve a problem of deterioration in the switch circuit apparatus due to an electrostatic breakdown voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a switch circuit device used for high-frequency switching applications, and more particularly to a switch circuit device having one control terminal.
[0002]
[Prior art]
In switch circuit devices for antenna switching mainly for wireless LANs, the DPDT (Double Pole Double Throw) type has begun to be widely used. From the two terminals of the input terminal Rx and the output terminal Tx, the reception ANT port ANT1 and the transmission / reception ANT The connection to the two terminals of the port ANT2 is switched by a control signal.
[0003]
FIG. 7A is a circuit block diagram as an example of a DPDT switch circuit device for antenna switching use.
[0004]
The switching operation is performed by five FETs (F1 to F5). The external terminals are an input terminal Rx, an output terminal Tx, a reception ANT port (antenna) ANT1, a transmission / reception ANT port (antenna) ANT2, and two control terminals CTL1 and CTL2. There are three GND terminals GND1 to GND3 and 10 terminals of the power supply terminal VDD.
[0005]
In this switch circuit device, a logic circuit called a decoder is provided to control switching between Tx / Rx and ANT1 / ANT2 as shown in the truth table of FIG. 7B by a 2-bit parallel input control signal. It is. Further, a shunt switch is provided to improve isolation. (For example, refer nonpatent literature 1.)
[0006]
[Non-Patent Document 1]
2 × 2 Antenna Switch GaAs MMIC NJG1544HC3 Catalog JRC Mar. 11, 2002 Ver. 4
[0007]
[Problems to be solved by the invention]
The switch circuit device described above incorporates a logic circuit called a decoder in order to perform switching control between Tx / Rx and ANT1 / ANT2 by a 2-bit parallel input control signal. However, extra FETs constituting the logic circuit are required, and there are problems such as increase in power consumption, package size, and man-hour.
[0008]
Further, since the gate width of the logic circuit is small, it is vulnerable to electrostatic breakdown, and there is a serious problem that the electrostatic breakdown voltage of the switch circuit device is lowered.
[0009]
[Means for Solving the Problems]
The present invention has been made in view of the various circumstances described above, and realizes an antenna changeover switch without using a logic circuit.
[0010]
That is, first, first and second switching elements, a first terminal connected to the sources or drains of both switching elements, a second terminal connected to the drains or sources of the first switching elements, A control terminal connected to the gate of the first switching element, a first connection means connected to the control terminal and a source or drain of the second switching element, and the first and second switching elements connected to a direct current First separating means for separating the first switching means, first grounding means for grounding the gate of the second switching element, and second grounding means for grounding the drain or source of the second switching element. To solve this problem.
[0011]
Second, the first and second switching elements, a first terminal connected to the source or drain of both the switching elements, a second terminal connected to the drain or source of the first switching element, and the first A first control terminal connected to the gate of the first switching element; a first connection means connected to the source or drain of the first control terminal and the second switching element; First grounding means for grounding the gate, second grounding means for grounding the drain or source of the second switching element, third and fourth switching elements, and the third and fourth switching elements A third terminal connected to the source or drain of the third switching element, a fourth terminal connected to the drain or source of the third switching element, and the second terminal A second control terminal connected to the gate of the switching element; a second connection means connected to the second control terminal and a source or drain of the fourth switching element; and a gate of the fourth switching element. A third grounding means for grounding, a fourth grounding means for grounding a drain or a source of the fourth switching element, and a first grounding means for separating the first switching element and the second switching element in a DC manner. A source and a drain connected to the first separation means, the second separation means for DC-separating the third switching element and the fourth switching element, and the second terminal and the fourth terminal; A fifth switching element connected to a gate by a third control terminal, and applying a control signal to the three control terminals to connect the first terminal to the second terminal and the second terminal Between the fourth terminal, solves by a signal path to one of between the third terminal and the fourth terminal.
[0012]
Further, the present invention is characterized by further comprising first bias means for applying a predetermined bias to the source or drain of the first switching element.
[0013]
Further, the present invention is characterized in that second bias means for applying a predetermined bias to the source or drain of the third switching element is provided.
[0014]
In addition, each of the first to fourth switching elements is an FET in which a source electrode and a drain electrode are provided on the surface of a channel layer, and a gate electrode is disposed between the source and drain electrodes. .
[0015]
Of the first to fifth switching elements, at least one switching element is a group of FETs in which a plurality of FETs are connected in series.
[0016]
Of the first to fifth switching elements, at least one of the switching elements is a multi-gate FET in which a plurality of gate electrodes are disposed between a source electrode and a drain electrode, respectively. It is.
[0017]
Further, the first and second bias means always supply a constant positive DC voltage.
[0018]
Further, the first separating means is formed by a capacitor.
[0019]
Further, the second separation means is formed by a capacitor.
[0020]
Further, the second and fourth grounding means are grounded via a capacitor.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS.
[0022]
FIG. 1 is a circuit diagram illustrating the switch circuit device according to the first embodiment. The switching circuit device includes five switching elements FET1 to 5, a transmission port Tx as a first terminal, a transmission / reception ANT port ANT1 as a second terminal, a reception ANT port ANT2 as a third terminal, and a fourth terminal. Receiving port Rx, first to third control terminals CTL1 to CTL3, first separation means, first bias means, first connection means, first and second grounding means, second separation means, second bias means , Second connecting means, third and fourth grounding means.
[0023]
Each of FET1 to FET5 is a GaAs MESFET in which a source electrode, a gate electrode, and a drain electrode are provided on the surface of the channel layer. That is, as shown in the cross-sectional view of FIG. 1B, the N-type channel region 2 is formed by doping the surface portion of the non-doped GaAs substrate 1 with the N-type impurity, and the gate electrode is in Schottky contact with the surface of the channel region 2. 3 and source / drain electrodes 4 and 5 in ohmic contact with the GaAs surface are arranged on both sides of the gate electrode 3. This transistor is a depletion type FET, and forms a depletion layer in the channel region 2 immediately below by the potential of the gate electrode 3, thereby controlling the channel current between the source electrode 4 and the drain electrode 5.
[0024]
In this circuit, the blocks α and β indicated by broken lines have the same circuit configuration, and are arranged symmetrically with respect to the FET 5 connected to the circuits of the two blocks.
[0025]
Therefore, the switch circuit device of the block α of the present invention will be described with reference to FIG. First, the circuit of the block α is a switch circuit device called SPST (Single Pole Single Throw) in which the FET 1 is switched to use the signal path between Tx and ANT1. In this circuit, an FET 2 is further provided and used as a shunt FET. As a result, an SPST switch circuit device with improved isolation is realized. Furthermore, in order to control two FETs, two control terminals are usually required, but the SPST switch shown in the figure can control the switching FET and the shunt FET with one control terminal, This can contribute to the reduction of the number of pins.
[0026]
Hereinafter, components and operations of the SPST circuit of the block α will be described. However, since the source electrode and the drain electrode are equivalent, the following description will be made using either one of them.
[0027]
In the SPST switch of the block α, the FET (FET1) that performs the switching operation and the shunt FET (FET2) that improves the isolation can be controlled by one control terminal CTL1.
[0028]
The source electrodes of FET1 and FET2 are both connected to Tx, the gate electrode of FET1 is connected to the control terminal CTL1 through the resistor Ra1, and a control signal is applied.
[0029]
The first bias means is means for always applying a predetermined bias V1 to the drain electrode of the FET1. Specifically, a positive constant DC voltage, for example, 3V, is applied via the resistor Rc1.
[0030]
The first grounding means is a means for grounding the gate electrode of the FET2 by the resistor Rb1. Thereby, the gate electrode of the FET 2 is always fixed to the ground potential.
[0031]
The first connection means is means for connecting the control terminal CTL1 and the drain electrode of the FET2 by a resistor Rd1.
[0032]
The first separation means is a capacitor Ca1 connected between the source electrodes of FET1 and FET2, and separates the FET1 and FET2 in a DC manner.
[0033]
The second grounding means grounds the side (drain electrode) of the FET 2 that is not connected to the Tx terminal via the capacitor Cb1.
[0034]
Thus, the resistors Ra1, Rb1, Rc1, and Rd1 are connected to the gate electrode of the FET 1, the first grounding means, the first biasing means, and the first connecting means, respectively, and with respect to a DC potential that becomes AC grounding. The high-frequency signal is prevented from leaking from each connection point.
[0035]
Next, the operation principle of the switch circuit device of the present invention will be described with reference to FIG.
[0036]
Since it is an SPST switch, one FET is operated by applying a control voltage of 0 V or a positive voltage to one control terminal. At the same time, the other FET is operated as a shunt FET to improve isolation. That is, when the control voltage applied to the control terminal is 0 V, one of the FETs is in an on state, the other FET is in an off state, and when the control voltage is a positive voltage, the opposite state is sufficient.
[0037]
FIG. 2A shows a circuit portion corresponding to FET2. Since the gate electrode of the FET 2 is grounded by the first grounding means via the resistor Rb1, the gate voltage is fixed at 0V. The bias condition for turning on the FET 2 is that the potential difference between the gate and the drain and between the gate and the source is 0V. That is, V _g = V _d = V _s And the gate voltage V _g Is 0V, so V _g = V _d = V _s When = 0V, FET2 is turned on.
[0038]
On the contrary, the bias condition for turning off the FET 2 when the gate voltage is 0V may be a potential difference that turns off the FET between the gate and the drain and between the gate and the source. In this circuit, since the control electrode CTL1 and the source electrode or drain electrode of the FET2 are connected by the first connecting means via the resistor Rd1, the FET2 is turned on when 0V is applied to the control terminal CTL1, and the positive voltage is applied. If (for example, 3 V) is applied, the FET 2 is turned off.
[0039]
Here, since the drain electrode of the FET 2 is grounded via the capacitor Cb1, the signal escapes to the ground when the FET 2 is on.
[0040]
FIG. 2B shows a circuit portion corresponding to FET1. The bias condition for turning off the FET 1 at a gate voltage of 0 V may be a potential difference that turns off between the gate and the drain and between the gate and the source. Therefore, a circuit (bias means) that always applies a positive voltage (for example, 3 V) bias may be connected to the source or drain side of the FET 1.
[0041]
Conversely, when a potential equal to the bias voltage is applied from the control terminal CTL1 to the gate electrode of the FET1, the FET1 is turned on. Accordingly, in this circuit, when the control terminal CTL1 is 0V, the FET1 is turned off, and when 3V, the FET1 is turned on.
[0042]
The switch circuit device shown in FIG. 1 (C) is a combination of FIG. 2 (A) and FIG. 2 (B). FET1 and FET2 are DC separated by the capacitor Ca1 as the first separating means to prevent interference between the bias conditions.
[0043]
Thus, when 0 V is applied to the control terminal CTL1, the FET 1 is turned off and the FET 2 is turned on. When 3V is applied to the control terminal CTL1, the FET1 is turned on and the FET2 is turned off. That is, when the signal path of Tx-ANT1 is turned off, the FET 2 is turned on. Therefore, the leakage of the input signal passing through the FET 2 escapes to the ground through the grounded capacitor C, and the isolation can be improved. .
[0044]
That is, in the circuit shown in the block α, a shunt FET is provided in the SPST switch circuit device to improve isolation, and this can be realized with one control terminal.
[0045]
Next, the switch circuit device of the block β will be described. The switch circuit device of the block β has the same circuit configuration as that of the block α, and is arranged in line symmetry with the FET 5 as the center as described above. That is, the SPST switch of the block β can also control the two FETs 3 and 4 with one control terminal CTL2 as described above.
[0046]
The source electrodes of FET3 and FET4 are both connected to ANT2, and the gate electrode of FET3 is connected to the control terminal CTL2 via the resistor Ra2, and a control signal is applied.
[0047]
The second bias means is means for always applying a predetermined bias V2 to the drain electrode of the FET3. Specifically, a positive constant DC voltage, for example, 3V is applied through the resistor Rc2.
[0048]
The third grounding means is a means for grounding the gate electrode of the FET 4 by the resistor Rb2. Thereby, the gate electrode of the FET 4 is always fixed to the ground potential.
[0049]
The second connection means is means for connecting the control terminal CTL2 and the drain electrode of the FET 4 by a resistor Rd2.
[0050]
The second separation means is a capacitor Ca2 connected between the FET3 and FET4, and separates the source electrodes of the FET3 and FET4 in a DC manner.
[0051]
The fourth grounding means grounds the side (drain electrode) of the FET 4 that is not connected to the ANT2 terminal via the capacitor Cb2.
[0052]
In this way, the resistors Ra2, Rb2, Rc2, and Rd2 are connected to the gate electrode, the third grounding means, the second biasing means, and the second connecting means of the FET 3, respectively, so that each of the DC potentials that become AC grounding is provided. High frequency signals are prevented from leaking from the connection point.
[0053]
Here, since detailed circuit operation is the same as that of the block α, the description thereof is omitted, but when 0 V is applied to the control terminal CTL2, the FET 3 is turned off and the FET 4 is turned on. When 3V is applied to the control terminal CTL2, the FET 3 is turned on and the FET 4 is turned off. That is, when the signal path of Rx-ANT2 is turned off, the FET 4 is turned on. Therefore, the leakage of the input signal passing through the FET 4 escapes to the ground through the grounded capacitor C, and the isolation can be improved. .
[0054]
In the DPDT switch circuit device of the present embodiment, the ANT1 terminal of the block α and the Rx terminal of the block β are connected to the source electrode and the drain electrode of the FET 5, and the third electrode is connected to the gate electrode of the FET 5 via the resistor Re. The control terminal CTL3 is connected. The FET 5 forms an SPST that turns on and off the signal path of Rx-ANT1, and since the source electrode and drain electrode of the FET 5 are fixed at 3V as described above, the FET 5 is turned on when the potential of CTL3 is 3V, and Rx-ANT1 A signal flows between them, and when CTL3 is 0V, FET5 is turned off and the signal flow between Rx and ANT1 is interrupted.
[0055]
Basically, this circuit consists of SPST for turning on / off FET1 which is a signal path of Tx-ANT1, SPST for turning on / off FET3 which is a signal path of Rx-ANT2, and SPST which turns on / off FET5 which is a signal path of Rx-ANT1. A total of three SPSTs are integrated. In addition to the basic function, FET2 for improving isolation when Tx-ANT1 is OFF and FET4 for improving isolation when Rx-ANT2 is OFF are added.
[0056]
Therefore, with this circuit, when the control terminal CTL1 is 3V and the other control terminals are 0V as shown in the truth table of FIG. 3, the connection between Tx and ANT1 is turned on. When the control terminal CTL2 is 3V and the other control terminals are 0V, the area between Rx and ANT2 is turned on. When the control terminal CTL3 is 3V and the other control terminals are 0V, the area between Rx and ANT1 is turned on.
[0057]
Further, when the area between Tx and ANT1 is off, the FET 2 is turned on, and the leakage of the input signal passing through the FET 2 escapes to the ground. Further, when the area between Rx and ANT2 is off, the FET 4 is on, so that the leakage of the input signal passing through the FET 4 escapes to the ground via the capacitor.
[0058]
Here, FIG. 7C showing a conventional structure shows a portion corresponding to the block α and the block β in FIG. The switching elements FET1 to FET5 of this embodiment correspond to the FET1 to FET5 in FIG. 7A (the same applies to FIG. 7C), respectively.
[0059]
As described above, the switch circuit device having a conventional structure is provided with a logic circuit called a decoder, performs switching control of Tx / Rx and ANT1 / ANT2 by a 2-bit parallel input control signal, and further provides a shunt switch to provide isolation. It is intended to improve. However, in this embodiment, as shown in FIG. 1A, a DPDT switch with improved isolation can be realized without providing a logic circuit.
[0060]
Next, FIG. 4 shows an application example of the switch circuit device of the present invention. The separation means, the connection means, and the bias means are not limited to the connection example shown in FIG. 1, but can be connected as shown in FIG. That is, the first separating means only needs to be connected between the FETs 1 and 2 (FIG. 4A), and the first connecting means can be connected to either the source or drain electrode of the FET 2. Good (FIG. 4B). Further, the first bias means may be connected to either the source or drain electrode of the FET 1 (FIG. 4C). Further, the bias means may be omitted (FIG. 4D). However, the provision of the bias means stabilizes the potential and improves the isolation. The reason why the bias means may be omitted is that in this circuit operation, one of the control terminals CTL1 to CTL3 is always 3V, and even if the FET5 is in an OFF state, it is caused by the leakage current between the source and drain of the FET5. This is because the source and drain of the FET 5 are always at the same potential, and the potential of the source electrode and the drain electrode of the FET 1 is always at an H level close to 3V. Further, the connection changes from FIG. 4A to FIG. 4D can be performed independently, and the same effect can be obtained in all combinations. The same applies to the block β side.
[0061]
Next, second and third embodiments of the present invention will be described with reference to FIGS.
[0062]
In the DPDT switch, when Tx is an output exceeding 20 dBm, a FET exposed to a large power on the Tx side cannot withstand a large RF signal when turned off in one stage, and may not be completely turned off. For this reason, it is common to use a multi-stage FET in which a plurality of FETs are connected in series, or a multi-gate FET in which a plurality of gate electrodes are arranged between source and drain electrodes.
[0063]
FIG. 5 is a circuit diagram showing a DPDT switch circuit device according to a second embodiment of the present invention. In the first, second, and fifth switching elements of the second embodiment, first, second, and fifth switching elements in which FETs each having a source electrode, a gate electrode, and a drain electrode on the surface of the channel layer are connected in series in three stages. It is composed of a fifth FET group. As described above, the first, second, and fifth FET groups require the three switching elements F1, F2, and F5 to have a structure that can withstand high power because the source or drain is exposed to a large transmission power on the Tx side. Is done. Conversely, a FET that is only exposed to a power as small as the reception power on the Rx side does not cause a problem that it cannot be completely turned off even with a normal single gate FET single-stage structure. Therefore, in the circuit device of the present embodiment, the block α side and the fifth switching element connected to the block α side are FETs of multistage connection, and the block β side is a switching element of the same FET single stage as in the first embodiment.
[0064]
Each FET is a GaAs MESFET (depletion type FET), which is the same as that in FIG. In the present specification, three stages are described as an example of a multistage switch, but the number of stages can be appropriately selected according to desired power.
[0065]
In the circuit of the block α, the source electrode of the FET 1-1 at one end of the first FET group F1 and the source electrode of the FET 2-1 at one end of the second FET group F2 are connected to Tx. Further, the drain electrode of the FET 1-3 at the other end of the first FET group F1 is connected to ANT1, and the drain electrode of the FET 2-3 at the other end of the second FET group F2 is connected via the second grounding means Cb1. Grounded. Note that the source electrode and the drain electrode are equivalent, and either one will be described below. Here, the source electrode of the FET (eg, FET1-1 or FET1-3) connected to one end of the FET group (eg, F1) is referred to as the source of the FET group, and the FET (eg, FET1) connected to the other end of the FET group. -3 or FET1-1) is referred to as the drain of the FET group. Furthermore, since the block β has the same circuit configuration as that of the first embodiment, only the block α will be described.
[0066]
The SPST switch of the block α can control two FET groups, that is, a first FET group that performs a switching operation at one control terminal CTL1 and a second FET group on the shunt side.
[0067]
The sources of the first FET group F1 and the second FET group F2 are both connected to the Tx terminal, and the three gate electrodes of the first FET group F1 are connected via resistors Ra1-1, Ra1-2, and Ra1-3, respectively. The control signal is applied to the control terminal CTL1.
[0068]
The first bias means is means for always applying a predetermined bias V1 to the drain of the first FET group F1. Specifically, a positive constant DC voltage, for example, 3V, is applied via the resistor Rc1.
[0069]
The first grounding means is means for grounding the gate electrodes of the second FET group F2 by the resistors Rb1-1, Rb1-2, and Rb1-3, respectively. As a result, the gate electrode of the second FET group F2 is always fixed to the ground potential.
[0070]
The first connection means is means for connecting the drain of the second FET group F2, that is, the drain electrode of the FET 2-3, and the control terminal CTL1 with a resistor Rd1.
[0071]
The first separation means is a capacitor Ca1 connected between the first FET group and the second FET group, and dc-separates between the sources of the first FET group F1 and the second FET group. It is.
[0072]
The second grounding means grounds the side (drain electrode) not connected to the Tx terminal of the second FET group F2 via the capacitor Cb1.
[0073]
As described above, the resistors Ra1-1 to 1-3, Rb1-1 to 1-3, Rb1-1 to 1-3, and the gate electrodes, the first grounding unit, the first biasing unit, and the first connecting unit of each FET group F1, respectively. Rc1 and Rd1 are connected to prevent high-frequency signals from leaking out from the respective connection points with respect to each DC potential serving as AC grounding.
[0074]
Thereby, when 0 V is applied to the control terminal CTL1, the first FET group F1 is turned off and the second FET group F2 is turned on. When 3V is applied to the control terminal CTL1, the first FET group F1 is turned on and the second FET group F2 is turned off. That is, when the signal path of Tx-ANT1 is turned off, the second FET group F2 is turned on, so that the leakage of the input signal passing through the second FET group F2 is grounded via the grounded capacitor Cb1. Escape and isolation can be improved.
[0075]
In the DPDT switch circuit device of the second embodiment, the ANT1 terminal of the block α and the Rx terminal of the block β are connected to the source and drain of the third FET group F3 serving as the fifth switching element. A third control terminal CTL3 is connected to each gate of the three FET groups F3 via resistors Re1, Re2, and Re3, respectively.
[0076]
With this circuit, when the control terminal CTL1 is 3V and the other control terminals are 0V, the connection between Tx and ANT1 is turned on. When the control terminal CTL2 is 3V and the other control terminals are 0V, the area between Rx and ANT2 is turned on. When the control terminal CTL3 is 3V and the other control terminals are 0V, the area between Rx and ANT1 is turned on.
[0077]
Further, when the interval between Tx and ANT1 is off, the second FET group F2 is turned on, and the leakage of the input signal passing through the second FET group F2 escapes to the ground. Further, when the area between Rx and ANT2 is off, the FET 4 is on, so that the leakage of the input signal passing through the FET 4 escapes to the ground through the capacitor.
[0078]
Even if the number of stages of the FET group is increased, only the number of resistors Ra1, Rb1, and Re connected to each gate electrode is increased, and other circuit configurations are the same as those in FIG.
[0079]
Further, the separation means, the connection means, and the bias means are not limited to the connection example shown in FIG. 5, and an application circuit as shown in FIG. 4 can also be applied. In other words, the first separating means only needs to be connected between the first and second FET groups (see FIG. 4A), and the first connecting means is the source of the second FET group or Any of the drains may be connected (see FIG. 4B). Furthermore, the first bias means may be connected to either the source or the drain of the first FET group F1 (see FIG. 4C). Further, the bias means may be omitted (see FIG. 4D), but the provision of the bias means stabilizes the potential and improves the isolation. Moreover, the above connection changes can be performed independently, and the same effect can be obtained in all combinations. An application circuit similar to that of the first embodiment can be applied to the block β side.
[0080]
Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, FETs having a multi-gate structure are used as the first, second, and fifth switching elements.
[0081]
In the second embodiment, a plurality of FETs are connected in multiple stages in order to obtain high power, and the number of FETs simply increases, so that the chip area increases. If a multi-gate FET is used to avoid this, the maximum allowable linear input power can be increased while suppressing an increase in chip area. In the multi-gate FET, as shown in FIG. 6A, a GaAs MESFET (depletion type FET) in which, for example, three gate electrodes 3 are arranged between the source electrode 4 and the drain electrode 5 to constitute one FET. It is.
[0082]
The source electrode 4 and the drain electrode 5 in which the metal layer forms an ohmic junction are alternately arranged with the three gate electrodes 3 interposed therebetween, but actually the channel regions 2 on both sides of the gate electrodes 3 are the source. Since it functions as the electrode 4 and the drain electrode 5, it has the same effect as three FETs each having one gate electrode connected in series. That is, the maximum allowable linear input power that is three times the maximum allowable linear voltage amplitude and nine times the square of the power is obtained as compared with the switch circuit device using the FET with one gate electrode.
[0083]
FIG. 6B is a circuit diagram for realizing a DPDT switch using a multi-gate FET. In the figure, a triple gate structure having three gate electrodes is described as an example. However, the present invention is not limited to this, and the number of gate electrodes is appropriately selected according to the required power.
[0084]
The first, second, and fifth FET1, FET2, and FET5 in the switch circuit device of the third embodiment all have a multi-gate structure with three gate electrodes. In these multi-gate FETs, three gate electrodes The high-frequency potentials are different. In other words, when these multi-gate FETs become off-side FETs, and when high-frequency maximum power is applied to the source electrode or drain electrode of these FETs, the gate is located immediately below the gate electrode closest to the maximum power among the three gate electrodes. The channel is not always closed by a depletion layer due to bias. Although the channel is in a further closing direction just below the gate electrode close to the maximum power just below the middle gate electrode, the situation that the channel is always closed is not reached. The channel is always closed for the first time just below the gate electrode farthest from the third maximum power, and the multi-gate FET can be turned off. As described above, the fact that the high-frequency potentials of the channels immediately below the three gate electrodes are different means that the high-frequency potentials of the three gate electrodes are different. Therefore, when a DC potential as a DC bias is applied to each gate electrode of the multi-gate FET, it is connected to the DC potential through a resistor in order to prevent a high frequency signal from leaking from each gate electrode to a DC potential serving as a high frequency ground. However, as a method for connecting to the DC potential, it is necessary to connect to the DC potential via different resistors. This is because if all three gate electrodes are directly connected and then connected to a DC potential through one resistor, all the high frequency potentials of the three gate electrodes are set to the same potential. The same operation as a single gate FET results in an FET that cannot withstand high power.
[0085]
As for the gate electrode of FET1, the first gate electrode, the second gate electrode, and the third gate electrode are connected to the control terminal CTL1 through the resistors Ra1, Ra2, and Ra3, respectively, outside the operation region, and a control signal is applied.
[0086]
The first grounding means is means for grounding all the gate electrodes of the FET 2 by the resistors Rb1-1, Rb1-2, and Rb1-3. Thereby, all the gate electrodes of the FET 2 are always fixed to the ground potential.
[0087]
Further, all the gate electrodes of the FET 5 are connected to the control terminal CTL3 through the resistors Re1, Re2, Re3, respectively, outside the operating region, and the control signal is applied. .
[0088]
Since the block β is exactly the same as that in the first embodiment, description thereof is omitted.
[0089]
The principle of operation of the DPDT switch using a multi-gate FET is the same as that of the first embodiment, so that the description thereof will be omitted. However, according to this embodiment, isolation is improved with three control terminals without providing a logic circuit. A high power DPDT switch can be realized. Furthermore, the area occupied on the chip can be reduced as compared with the multi-stage FET structure.
[0090]
Further, the separation means, the connection means, and the bias means are not limited to the connection example shown in FIG. 6, but can be connected as shown in FIG. In other words, the first separating means only needs to be connected between FET1 and FET2 (see FIG. 4A), and the first connecting means may be connected to either the source or drain electrode of FET2. Good (see FIG. 4B). Furthermore, the first bias means may be connected to either the source or drain electrode of the FET 1 (see FIG. 4C). Further, the bias means may be omitted (see FIG. 4D), but the provision of the bias means stabilizes the potential and improves the isolation. Moreover, the above connection changes can be performed independently, and the same effect can be obtained in all combinations. An application circuit similar to that of the first embodiment can be applied to the block β side. Moreover, the above connection changes can be performed independently, and the same effect can be obtained in all combinations.
[0091]
Even if the number of gate electrodes between a pair of source and drain electrodes increases, the number of resistors Ra1, Rb1, and Re connected to each gate electrode only increases, and the other circuit configuration is the same as in FIG. Become.
[0092]
Further, the second and third embodiments are asymmetric circuits in which the number of FET stages and the number of gate electrodes of the switching elements constituting the block α side and the block β side are different. Since the block β side does not require a large amount of power and only adopts a single-stage FET or a single gate structure, the same switching elements as those on the block α side are used, and the fifth switching element is the center of symmetry. It may be a circuit.
[0093]
【The invention's effect】
As described above in detail, according to the present invention, the following effects can be obtained.
[0094]
First, a DPDT switch can be realized without using a logic circuit. Thereby, circuit arrangement is simplified and the mounting area of a printed circuit board can be made small. Further, since the FET for the logic circuit becomes unnecessary, the number of parts can be reduced and the manufacturing process can be simplified. Also, since the FET for logic circuit has a narrow gate width and is vulnerable to electrostatic breakdown, omitting this can provide a switch circuit device that is resistant to electrostatic breakdown. In addition, power consumption can be reduced.
[0095]
Second, by providing the shunt FET (group) in addition to the FET (group) that performs the switching operation, the leakage of the input signal to the shunt FET (group) when the FET (group) that performs the switching operation is turned off. Since the ground escapes to the ground via the grounded capacitor, the isolation characteristic is greatly improved.
[0096]
Third, the SPST switch that is a unit of the DPDT switch may have only one control terminal even if a shunt FET (group) is provided, and a DPDT having a shunt FET can be realized with three control terminals. The chip size can be greatly reduced and mounting on a set becomes very easy.
[0097]
Thirdly, when a multi-stage connection FET or a multi-gate FET is used, higher power can be realized as compared with the case where a single-stage FET or a single-gate FET is used. In particular, when the multi-gate structure is adopted, the area occupied on the chip can be reduced as compared with the multi-stage connection FET structure while being high power.
[Brief description of the drawings]
1A is a circuit diagram, FIG. 1B is a cross-sectional view, and FIG. 1C is a circuit diagram for explaining the present invention.
FIG. 2 is a circuit diagram for explaining the present invention.
FIG. 3 is a truth table for explaining the present invention.
FIG. 4 is a circuit diagram for explaining the present invention.
FIG. 5 is a circuit diagram for explaining the present invention.
6A is a sectional view and FIG. 6B is a circuit diagram for explaining the present invention.
7A is a circuit block diagram, FIG. 7B is a truth table, and FIG. 7C is a circuit block diagram for explaining a conventional example.

Claims (12)

First and second switching elements;
A first terminal connected to the source or drain of the switching elements;
A second terminal connected to the drain or source of the first switching element;
A control terminal connected to the gate of the first switching element;
First connection means for connecting to the control terminal and the source or drain of the second switching element;
First separation means for DC-separating the first and second switching elements;
First grounding means for grounding a gate of the second switching element;
A switch circuit device comprising: a second grounding means for grounding a drain or a source of the second switching element. First and second switching elements;
A first terminal connected to the source or drain of the switching elements;
A second terminal connected to the drain or source of the first switching element;
A first control terminal connected to the gate of the first switching element;
First connection means for connecting to the first control terminal and the source or drain of the second switching element;
First grounding means for grounding a gate of the second switching element;
Second grounding means for grounding a drain or a source of the second switching element;
Third and fourth switching elements;
A third terminal connected to the source or drain of the third and fourth switching elements;
A fourth terminal connected to the drain or source of the third switching element;
A second control terminal connected to the gate of the third switching element;
Second connection means for connecting to the second control terminal and the source or drain of the fourth switching element;
Third grounding means for grounding a gate of the fourth switching element;
A fourth grounding means for grounding a drain or a source of the fourth switching element;
First separation means for DC-separating the first and second switching elements;
Second separating means for separating the third and fourth switching elements in a DC manner;
A fifth switching element having a source and a drain connected to the second terminal and the fourth terminal, and a third control terminal connected to the gate;
A control signal is applied to the three control terminals to set a signal path between the first terminal and the second terminal, between the second terminal and the fourth terminal, or between the third terminal and the fourth terminal. A switch circuit device characterized by that. 3. The switch circuit device according to claim 1, further comprising a first bias unit that applies a predetermined bias to a source or a drain of the first switching element. 4. 4. The switch circuit device according to claim 3, wherein the first bias means always supplies a constant positive DC voltage. 3. The switch circuit device according to claim 2, further comprising second bias means for applying a predetermined bias to the source or drain of the third switching element. 6. The switch circuit device according to claim 5, wherein the second bias means always supplies a constant positive DC voltage. The switch circuit device according to claim 1, wherein the first separation unit is formed of a capacitor. The switch circuit device according to claim 2, wherein the second separation unit is formed of a capacitor. 3. The FET according to claim 2, wherein each of the first to fifth switching elements is a FET in which a source electrode and a drain electrode are provided on a channel layer surface, and a gate electrode is disposed between the source and drain electrodes. Switch circuit device. 3. The switch circuit device according to claim 2, wherein at least one of the first to fifth switching elements is an FET group in which a plurality of FETs are connected in series in a multistage manner. The at least one switching element among the first to fifth switching elements is a multi-gate FET in which a plurality of gate electrodes are arranged between a source electrode and a drain electrode, respectively. The switch circuit device according to 1. The switch circuit device according to claim 2, wherein the second and fourth grounding means are grounded via a capacitor.

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