JP2005005858A - Switch circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DPDT switch circuit apparatus employing one control terminal without providing a logic circuit. <P>SOLUTION: A gate electrode of an FET 1 (4) is connected to the control terminal CTL respectively via a resistor Ra (Rh), a drain electrode of an FET 2 (3) is connected to the control terminal CTL respectively via a resistor Rd (Re), and the single control terminal controls the four FETs. When a control voltage applied to the control terminal is 0V, the two FETs are brought into an on state and the remaining two FETs are brought into an off state at the same time, and when the control voltage is a positive voltage, the FETs are brought into the opposite state to above. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a switch circuit device used for high-frequency switching applications, and more particularly to a switch circuit device having one control terminal.
[0002]
[Prior art]
As a switch circuit device often used in a mobile phone terminal, there is a switch circuit device called DPDT (Double Pole Double Throw). This is a circuit having four FETs or FET groups, two input terminals, and two output terminals.
[0003]
FIG. 10A shows a cross-sectional view of a GaAs FET. The surface portion of the non-doped GaAs substrate 1 is doped with an N-type impurity to form an N-type channel region 2, and a gate electrode 3 that forms a Schottky contact or a PN junction is disposed on the surface of the channel region 2. On both sides, source / drain electrodes 4 and 5 are placed in ohmic contact with the GaAs surface. This transistor is a depletion type FET, and forms a depletion layer in the channel region 2 immediately below by the potential of the gate electrode 3, thereby controlling the channel current between the source electrode 4 and the drain electrode 5.
[0004]
FIG. 10B shows a circuit block diagram of a switch circuit device called DPDT (Double Pole Double Throw) using GaAs FETs or FET groups.
[0005]
The DPDT has four FETs (or FET groups) F1 to F4 that serve as switches. RF1, RF2, RF3, and RF4 RF terminals and four GND terminals so that the combination method of connecting the two RF terminals RF1 and RF3 to the other two RF terminals RF2 and RF4 can be switched between two types. It has one control terminal CTL and one power supply terminal VDD. This circuit simultaneously turns off F2 and F4 when F1 and F3 are on simultaneously. When F1 and F3 are simultaneously off, F2 and F4 are simultaneously turned on to switch the signal path. In general, since two FETs or FET groups are operated simultaneously, two control terminals are required with the gate electrodes of the two FETs or FET groups in common. However, in the circuit shown in FIG. Four FETs or FET groups are controlled by one control terminal (see, for example, Non-Patent Document 1).
[0006]
[Non-Patent Document 1]
Logic control built-in high power DPDT switch MMIC CXG1144EN catalog, SONY
[0007]
[Problems to be solved by the invention]
In the above switch circuit device, by providing a logic circuit, the circuit operation shown in the truth table of FIG. 10C is performed with one control terminal. However, such a circuit device requires extra FETs constituting a logic circuit, and has problems such as an increase in power consumption and package size, an increase in the number of parts, and an increase in man-hours.
[0008]
Further, since the FET constituting the logic circuit has a small gate width, it is vulnerable to electrostatic breakdown, and there has been a serious problem that the electrostatic breakdown voltage of the switch circuit device is lowered.
[0009]
[Means for Solving the Problems]
The present invention has been made in view of the various circumstances described above. First, the first and second switching elements, the first common input terminal connected to the source or drain of both the switching elements, First and second output terminals connected to the drains or sources of both switching elements, one control terminal connected to the gate of the first switching element, and a source or drain of the first switching element First bias means for applying a bias, first connection means for connecting the one control terminal to the source or drain of the second switching element, and first gate for grounding the gate of the second switching element. Grounding means, a third switching element connected to the first output terminal, and a gate connected to the second output terminal, the gate being the control A fourth switching element connected to the child, a second connecting means for connecting a source or drain of the third switching element and the control terminal, and the first switching element and the second switching element. A first separation means for direct current separation; a second separation means for direct current separation of the first switching element and the third switching element; the second switching element; and the fourth switching element. A third separation means for separating the switching element in a DC manner; a fourth separation means for separating the third switching element and the fourth switching element in a DC manner; and a gate of the third switching element. Second grounding means for grounding, second bias means for applying a predetermined bias to the source or drain of the fourth switching element, and the third and fourth Solves by and a second common input terminal connected to the source or drain of the switching element.
[0010]
In addition, each of the first to fourth switching elements is an FET in which a source electrode and a drain electrode are provided on the surface of a channel layer, and a gate electrode is disposed between the source and drain electrodes. .
[0011]
The first to fourth switching elements are a first FET group, a second FET group, a third FET group, and a fourth FET group in which a plurality of FETs are connected in series in multiple stages, respectively. It is characterized by.
[0012]
Each of the first to fourth switching elements is a multi-gate FET in which a plurality of gate electrodes are arranged between a source electrode and a drain electrode.
[0013]
Further, the first and second bias means always supply a constant positive DC voltage.
[0014]
The first, second, third and fourth separating means are each formed by a capacitor.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS.
[0016]
FIG. 1 is a circuit diagram showing a switch circuit device according to a first embodiment of the present invention. The switch circuit device includes four FET1 to FET4, a first common input terminal IN1, a second common input terminal IN2, first and second output terminals OUT1 and OUT2, a control terminal CTL, a first separation unit, 2 separation means, 3rd separation means, 4th separation means, 1st grounding means, 2nd grounding means, 1st connection means, 2nd connection means, 1st bias means, 2nd And bias means.
[0017]
Each of FET1 to FET4 is a depletion type GaAs MESFET in which a source electrode, a gate electrode, and a drain electrode are provided on the surface of the channel layer, and is the same as FIG.
[0018]
In the DPDT switch circuit device of the present invention, the source electrode (or drain electrode) of FET1 and the source (or drain electrode) of FET2 are connected to the first common input terminal IN1, and the source electrode (or drain electrode) of FET3 is connected to the source electrode (or drain electrode) of FET3. The source electrode (or drain electrode) of the FET 4 is connected to the second common input terminal IN2. Further, the drain electrode (or source electrode) of the FET1 is connected to the first output terminal OUT1, and the drain electrode (or source electrode) of the FET2 is connected to the second output terminal OUT2. In addition, since the source electrode and the drain electrode are equivalent, it demonstrates using either one below.
[0019]
In the present embodiment, four FETs can be controlled by one control terminal CTL, the gate electrodes of FET1 and FET4 are connected to the control terminal CTL via resistors Ra and Rh, respectively, and the drain electrodes of FET2 and FET3 are connected. Are connected to the control terminal CTL via resistors Rd and Re, respectively, and a control signal is applied.
[0020]
The first bias means is means for always applying a predetermined bias Va to the source electrode of the FET 1. Specifically, a positive constant DC voltage, for example, 3V is applied via the resistor Rc.
[0021]
The first grounding means is a means for grounding the gate electrode of the FET 2 by the resistor Rb. Thereby, the gate electrode of the FET 2 is always fixed to the ground potential.
[0022]
The first connection means is means for connecting the control terminal CTL and the drain electrode of the FET 2 by a resistor Rd.
[0023]
The first separating means is a capacitor Ca connected between the source electrode of FET1 and the source electrode of FET2, and separates the FET1 and FET2 in a DC manner.
[0024]
In this embodiment, as shown in FIG. 1, resistors Ra, Rb, Rc, and Rd are connected to the gate electrode of the FET 1, the first grounding means, the first biasing means, and the first connecting means, respectively. The high-frequency signal is prevented from leaking from each connection point with respect to the DC potential.
[0025]
In this circuit, the drain electrodes of FET3 and FET4 are connected to the output terminals OUT1 and OUT2 of FET1 and FET2 that perform switching. Further, the source electrodes of FET3 and FET4 are connected to the second common input terminal IN2.
[0026]
The second bias means is means for constantly applying a predetermined bias Vb to the drain electrode of the FET 4. Specifically, a positive constant DC voltage, for example, 3V is applied via the resistor Rg.
[0027]
The second grounding means is means for grounding the gate electrode of the FET 3 with the resistor Rf. Thereby, the gate electrode of the FET 3 is always fixed to the ground potential.
[0028]
The second connection means is means for connecting the control terminal CTL and the drain electrode of the FET 3 by a resistor Re.
[0029]
The second separation means is a capacitor Cb connected between the FET1 and FET3, and separates the FET1 and FET3 in a DC manner.
[0030]
The third separation means is a capacitor Cc connected between FET2 and FET4, and separates between FET2 and FET4 in a DC manner.
[0031]
The fourth separation means is a capacitor Ce connected between the FET 3 and the FET 4, and separates the FET 3 and the FET 4 in a DC manner.
[0032]
Resistors Re, Rf, Rg, and Rh are connected to the second connecting means, the second grounding means, the second biasing means, and the gate electrode of the FET 4, respectively. Prevents high-frequency signals from leaking out.
[0033]
Next, the operating principle of the switch circuit device of the present invention will be described with reference to FIGS.
[0034]
In the case of a DPDT switch, in order to have one control terminal, when the control voltage applied to the control terminal is 0 V, the two FETs are turned on simultaneously, the other two FETs are turned off, and the control voltage is positive. In the case of voltage, the reverse state should be satisfied.
[0035]
FIG. 2 shows a circuit portion corresponding to FET2. Since the gate electrode of the FET 2 is grounded by the first grounding means via the resistor Rb, the gate voltage is fixed at 0V. The bias condition for turning on the FET 2 is that the potential difference between the gate and the drain and between the gate and the source is 0V. That is, V _g = V _d = V _s And the gate voltage V _g Is 0V, so V _g = V _d = V _s When = 0V, FET2 is turned on.
[0036]
On the contrary, the bias condition for turning off the FET 2 when the gate voltage is 0V may be a potential difference that turns off the FET between the gate and the drain and between the gate and the source. In this circuit, the control terminal CTL and the source electrode or drain electrode of the FET 2 are connected by the first connecting means via the resistor Rd. Therefore, if 0 V is applied to the control terminal CTL, the FET 2 is turned on, and the positive voltage If (for example, 3 V) is applied, the FET 2 is turned off.
[0037]
FIG. 3 shows a circuit portion corresponding to FET1. The bias condition for turning off the FET 1 at a gate voltage of 0 V may be a potential difference that turns off between the gate and the drain and between the gate and the source. Therefore, a circuit (bias means) that always applies a positive voltage (for example, 3 V) bias may be connected to the source or drain side of the FET 1.
[0038]
Conversely, when a potential equal to the bias voltage is applied from the control terminal CTL to the gate electrode of the FET 1, the FET 1 is turned on. Accordingly, in this circuit, the FET 1 is turned off when the control terminal CTL is 0V, and the FET 1 is turned on at 3V.
[0039]
FIG. 4 shows a circuit portion corresponding to the FET 3. Since the gate electrode of the FET 3 is grounded by the second grounding means via the resistor Rf, the gate voltage is fixed at 0V. The bias condition for turning on the FET 3 is that the potential difference between the gate and the drain and between the gate and the source is 0V. That is, since Vg = Vd = Vs and the gate voltage Vg is 0 V, V _g = V _d = V _s When = 0V, the FET 3 is turned on.
[0040]
On the contrary, the bias condition for turning off the FET 3 when the gate voltage is 0 V may be a potential difference that turns off the FET between the gate and the drain and between the gate and the source. In this circuit, the control terminal CTL and the source electrode or drain electrode of the FET 3 are connected by the second connection means via the resistor Re. Therefore, if 0 V is applied to the control terminal CTL, the FET 3 is turned on, and the positive voltage If (for example, 3V) is applied, the FET 3 is turned off.
[0041]
FIG. 5 shows a circuit portion corresponding to the FET 4. The bias condition for turning off the FET 4 at a gate voltage of 0 V may be a potential difference that turns off between the gate and the drain and between the gate and the source. Therefore, a circuit (bias means) that always applies a positive voltage (for example, 3 V) bias may be connected to the source or drain side of the FET 4.
[0042]
Conversely, when a potential equal to the bias voltage is applied from the control terminal CTL to the gate electrode of the FET 4, the FET 4 is turned on. Therefore, in this circuit, when the control terminal CTL is 0V, the FET 4 is turned off, and at 3V, the FET 4 is turned on.
[0043]
The switch circuit device shown in FIG. 1 is a combination of the circuits shown in FIGS. FET1 and FET2 are separated in a DC manner by a capacitor Ca which is the first separation means to prevent interference between the bias conditions. Further, the FET 1 and the FET 3 are DC separated by the capacitor Cb as the second separating means, and the FET 2 and the FET 4 are separated DC by the capacitor Cc as the third separating means, which is the fourth separating means. The capacitor Ce separates the FET 3 and the FET 4 in a DC manner.
[0044]
As described above, in this embodiment, the gate electrodes of FET2 and FET3 are grounded through the resistors Rb and Rf, respectively, and the drain of FET2 and FET3 whose gate electrodes are grounded are biased to the gates of the other FET1 and FET4. It is connected to the control terminal CTL in common with the electrode. Further, the bias of the source electrode or the drain electrode of the FET1 and FET4 is always supplied with the constant voltages Va and Vb. Further, FET1 and FET2 are galvanically separated by the capacitor Ca, FET1 and FET3, FET2 and FET4 are galvanically separated by the capacitors Cb and Cc, respectively, and FET3 and FET4 are separated by Ce.
[0045]
Here, the gate electrode of the FET 4 is connected to the control terminal CTL, and the control signal of the control terminal to the FET 1 is applied. As a result, when FET1 is ON, FET4 is turned ON. On the other hand, FET3 and FET4 are DC separated by the fourth separation means, so that FET2 and FET3 are turned off.
[0046]
Thus, as shown in the truth table of FIG. 6, when 0 V is applied to the control terminal CTL, the signals of the first common input terminal IN1-second output terminal OUT2 and the second common input terminal IN2-first output terminal OUT1. When the path is turned on and 3V is applied to the control terminal CTL, the signal path of the first common input terminal IN1-first output terminal OUT1 and second common input terminal IN2-second output terminal OUT2 is turned on. .
[0047]
That is, a DPDT switch circuit device having one control terminal can be realized without providing a logic circuit.
[0048]
FIG. 7 shows an application example of the switch circuit device of the present invention. The first and fourth separating means, the first and second connecting means, and the first and second biasing means are not limited to the connection example shown in FIG. 1, but can be connected as shown in FIG. In other words, the first separating means may be connected between FET1 and FET2 (see FIG. 7A), and the first connecting means may be connected to either the source or drain electrode of FET2. Good (see FIG. 7B). Further, the first bias means may be connected to either the source or drain electrode of FET 1 (see FIG. 7C), and the second bias means is connected to either the source or drain electrode of FET 4. It is also possible (see FIG. 7D). The second connecting means may be connected to either the source or drain electrode of the FET 3 (see FIG. 7E), and the fourth separating means only needs to be connected between the FET 3 and the FET 4 (see FIG. 7). 7 (F)). Further, the connection changes from FIG. 7A to FIG. 7F can be performed independently, and the same effect can be obtained in all combinations. Further, although not shown, the second and third separating means only have to separate between FET1 and FET3, and FET2 and FET4, respectively, so that they move to the FET1 and FET2 side with respect to the output terminals OUT1 and OUT2, respectively. It doesn't matter.
[0049]
Next, referring to FIGS. 8 and 9, second and third embodiments of the present invention will be described.
[0050]
In the DPDT switch circuit device currently used in the third generation portable terminal having the GPS function, the power required to pass a signal of about 26 dBm is required, and in order to realize such a high power, a multistage in which a plurality of FETs are connected in series. In general, a connection FET or a multi-gate FET in which a plurality of gate electrodes are arranged between a source electrode and a drain electrode is used.
[0051]
FIG. 8 is a circuit diagram showing a switch circuit device according to a second embodiment of the present invention. The first to fourth switching elements of the second embodiment are first to fourth FET groups in which FETs each having a source electrode, a gate electrode, and a drain electrode on the surface of the channel layer are connected in series in three stages. Composed. Each FET is a GaAs MESFET (depletion type FET), which is the same as that shown in FIG. In the present specification, three stages are described as an example of a multistage switch, but the number of stages can be appropriately selected according to desired power.
[0052]
The source electrode of the FET 1-1 at one end of the first FET group F1 and the source electrode of the FET 2-1 at one end of the second FET group F2 are connected to the first common input terminal IN1, and the third FET group F3 The source electrode of the FET 3-3 at one end and the source electrode of the FET 4-3 at one end of the fourth FET group F4 are connected to the second common input terminal IN2. Also, the drain electrode of the FET 1-3 at the other end of the first FET group F1 and the drain electrode of the FET 3-1 at the other end of the third FET group F3 are connected to the first output terminal OUT1, and the second FET The drain electrode of the FET 2-3 at the other end of the group F2 and the drain electrode of the FET 4-1 at the other end of the fourth FET group F4 are connected to the second output terminal OUT2. Hereinafter, the source electrode of the FET (for example, FET1-1 or FET1-3) connected to one end of the FET group (for example, F1) is referred to as the source of the FET group, and the FET (for example, FET1-3 or the like) connected to the other end of the FET group. The drain electrode of the FET 1-1) is called a drain of the FET group.
[0053]
In the present embodiment, four FET groups can be controlled by one control terminal CTL. The three gate electrodes of the first FET group F1 are connected to the control terminal CTL via the resistors Ra1, Ra2, and Ra3, respectively, and all the gate electrodes of the fourth FET group F4 are connected to the resistors Rh1, Rh2, and Rh3, respectively. The control signal is applied to the control terminal CTL.
[0054]
The first bias means is means for always applying a predetermined bias Va to the source of the first FET group F1. Specifically, a positive constant DC voltage, for example, 3V is applied via the resistor Rc.
[0055]
The first grounding means is means for grounding each gate electrode of the second FET group F2 by the resistors Rb1, Rb2, and Rb3. As a result, the gate electrode of the second FET group F2 is always fixed to the ground potential.
[0056]
The first connection means is means for connecting the drain of the second FET group F2, that is, the drain electrode of the FET 2-3, and the control terminal CTL with a resistor Rd.
[0057]
The first separation means is a capacitor Ca connected between the source of the first FET group and the source of the second FET group, and separates the first FET group and the second FET group in a DC manner. It is.
[0058]
In this embodiment, as shown in FIG. 1, resistors Ra1 to R3, Rb1 to Rc, Rc, and Rd are provided for the gate electrodes of the FET group F1, the first grounding means, the first biasing means, and the first connecting means, respectively. Are connected to each other to prevent high-frequency signals from leaking out from the respective connection points with respect to each DC potential serving as AC grounding.
[0059]
Further, in this circuit, the third FET group F3 and the fourth FET group 4 are connected to the output terminals OUT1 and OUT2 of the first FET group F1 and the second FET group F2 to be switched. Further, the sources of the third FET group F3 and the fourth FET group F4 are connected to the second common input terminal IN2.
[0060]
The second bias unit is a unit that always applies a predetermined bias Vb to the drain of the fourth FET group F4 (the drain electrode of the FET 4-1 or the FET 4-3). Specifically, a positive constant DC voltage, for example, 3V is applied via the resistor Rg.
[0061]
The second grounding means is means for grounding all the gate electrodes of the third FET group F3 by resistors Rf1, Rf2, and Rf3, respectively. As a result, the gate electrode of the third FET group F3 is always fixed to the ground potential.
[0062]
The second connection means is means for connecting the control terminal CTL and the drain of the third FET group F3 (the drain electrode of the FET 3-1 or the FET 3-3) by the resistor Re.
[0063]
The second separation means is a capacitor Cb connected between the drain of the first FET group F1 and the drain of the third FET group F3, and separates the first FET group F1 and the third FET group F3 in a DC manner. Is.
[0064]
The third separation means is a capacitor Cc connected between the drain of the second FET group F2 and the drain of the fourth FET group F4. The second FET group F2 and the fourth FET group F4 are connected to each other by a direct current. Separate.
[0065]
The fourth separation means is a capacitor Ce connected between the source of the third FET group F3 and the source of the fourth FET group F4, and direct current is connected between the third FET group F3 and the fourth FET group F4. Separate.
[0066]
Resistors Re, Rf1 to Rf3, Rg, and Rh1 to Rh3 are connected to the gate electrodes of the second connecting means, the second grounding means, the second biasing means, and the fourth FET group F4, respectively. The high-frequency signal is prevented from leaking from each connection point for each DC potential.
[0067]
In addition, the first FET group F1 and the second FET group 2 are separated in a DC manner by the capacitor Ca serving as the first separation means to prevent interference between the bias conditions. Further, the first FET group F1 and the third FET group F3 are DC-isolated by the capacitor Cb as the second separating means, and the second FET group F2 and the second FET group are separated by the capacitor Cc as the third separating means. The four FET groups F4 are separated in a direct current manner. In addition, the fourth FET group F4 and the third FET group F3 are galvanically separated by the capacitor Ce as the fourth separation means.
[0068]
As described above, in the present embodiment, the gate electrodes of the second FET group F2 and the third FET group F3 are grounded via the resistors Rb1 to Rb3 and Rf1 to Rf3, respectively, and the second gate electrode is grounded. The drain biases of the FET group F2 and the third FET group F3 are connected to the control terminal CTL in common with the gate biases of the other first FET group F1 and fourth FET group F4. The source biases of the first FET group F1 and the fourth FET group F4 are always supplied at constant voltages Va and Vb. Further, the first FET group F1 and the second FET group F2 are DC-isolated by the capacitor Ca, and the first FET group F1, the third FET group F3, the second FET group F2, and the fourth FET are separated. The group F4 is DC-isolated by the capacitors Cb and Cc, respectively, and the third FET group F3 and the fourth FET group F4 are DC-isolated by the capacitor Ce.
[0069]
Here, since the circuit operation of the second embodiment is the same as that of the first embodiment, the description is omitted, but the gate electrode of the fourth FET group F4 is connected to the control terminal CTL, A control signal of the control terminal is applied to one FET group F1. As a result, when the first FET group F1 is ON, the fourth FET group F4 is ON. On the other hand, since the third FET group F3 and the fourth FET group F4 are galvanically separated by the fourth separating means, the second FET group F2 and the third FET group F3 are turned off.
[0070]
As a result, when 0 V is applied to the control terminal CTL, the signal path of the first common input terminal IN1-second output terminal OUT2 and the second common input terminal IN2-first output terminal OUT1 is turned on, and the control terminal CTL When 3 V is applied, the signal paths of the first common input terminal IN1, the first output terminal OUT1, and the second common input terminal IN2 to the second output terminal OUT2 are turned on (see FIG. 6).
[0071]
Even if the number of stages of the FET group is increased, only the number of resistors Ra and Rb, Rf, Rh connected to each gate electrode is increased, and other circuit configurations are the same as those in FIG.
[0072]
Here, the first and fourth separating means, the first and second connecting means, and the first and second biasing means are not limited to the connection example shown in FIG. 8, but are applied in the same manner as in the first embodiment. Circuit can be applied. In other words, the first separating means only needs to be connected between the first and second FET groups (see FIG. 7A), and the first connecting means is the second FET group. It may be connected to either the source or the drain (see FIG. 7B). Further, the first bias means may be connected to either the source or the drain of the first FET group F1 (see FIG. 7C), and the second bias means is also the source of the fourth FET group F4. Alternatively, it may be connected to any one of the drains (see FIG. 7D). The second connecting means may be connected to either the source or the drain of the third FET group F3 (see FIG. 7E), and the fourth separating means is connected to the third and fourth FET groups. It is only necessary to be connected between them (see FIG. 7F). The above connection changes can be performed independently, and the same effect can be obtained in all combinations. Further, although not shown, the second and third separation means only have to separate between F1 and F3, and F2 and F4, respectively, so that they move to the F1 and F2 sides with respect to the output terminals OUT1 and OUT2, respectively. It doesn't matter.
[0073]
Next, a third embodiment of the present invention will be described with reference to FIG. The third embodiment uses a multi-gate FET as a switching element.
[0074]
In the second embodiment, a plurality of FETs are connected in multiple stages in order to obtain high power, and the number of FETs simply increases, so that the chip area increases. If a multi-gate FET is used to avoid this, it is possible to suppress the increase in chip area and increase the maximum linear allowable linear input power. As shown in FIG. 9A, the multi-gate FET is a GaAs MESFET (depletion type FET) in which, for example, three gate electrodes 3 are arranged between the source electrode 4 and the drain electrode 5.
[0075]
The source electrode 4 and the drain electrode 5 in which the metal layer forms an ohmic junction are alternately arranged with the three gate electrodes 3 interposed therebetween, but actually the channel regions 2 on both sides of the gate electrodes 3 are the source. Since it functions as the electrode 4 and the drain electrode 5, the same effect is obtained as when three FETs (see FIG. 10A) having one gate electrode 3 are connected in series. In other words, the maximum allowable linear input power is 3 times as the maximum allowable linear voltage amplitude and 9 times the square of the power as compared with a switch circuit device using a single FET gate electrode.
[0076]
FIG. 9B is a circuit diagram for realizing DPDT of one control terminal using a multi-gate FET. In the figure, a triple gate structure having three gate electrodes is described as an example. However, the present invention is not limited to this, and the number of gate electrodes is appropriately selected according to the required power.
[0077]
In each FET in the switch circuit device of the third embodiment, the three gate electrodes have different high-frequency potentials. That is, when a high-frequency maximum power is applied to the source electrode or drain electrode of the FET in the off-side FET, the channel is always closed by a depletion layer due to the gate bias immediately below the gate electrode closer to the maximum power among the three gate electrodes. This is not the situation. Although the channel is in a further closing direction just below the gate electrode close to the maximum power just below the middle gate electrode, the situation that the channel is always closed is not reached. The channel is always closed for the first time just below the gate electrode farthest from the third maximum power, and the multi-gate FET can be turned off. As described above, the fact that the high-frequency potentials of the channels immediately below the three gate electrodes are different means that the high-frequency potentials of the three gate electrodes are different. Therefore, when a DC potential as a DC bias is applied to each gate electrode of the multi-gate FET, it is connected to the DC potential through a resistor in order to prevent a high frequency signal from leaking from each gate electrode to a DC potential serving as a high frequency ground. However, as a method for connecting to the DC potential, it is necessary to connect to the DC potential via different resistors. This is because if all three gate electrodes are directly connected and then connected to a DC potential through one resistor, all the high frequency potentials of the three gate electrodes are set to the same potential. The same operation as a single gate FET results in an FET that cannot withstand high power.
[0078]
The gate electrode of the FET 1 is connected to the control terminal CTL through the resistors Ra1, Ra2, and Ra3 to the first gate electrode, the second gate electrode, and the third gate electrode, respectively, outside the operation region, and a control signal is applied.
[0079]
The first grounding means is means for grounding all the gate electrodes of the FET 2 by the resistors Rb1, Rb2, and Rb3. Thereby, all the gate electrodes of the FET 2 are always fixed to the ground potential.
[0080]
All the gate electrodes of the FET 4 are connected to the control terminal CTL through the resistors Rh1, Rh2, and Rh3 to the first gate electrode, the second gate electrode, and the third gate electrode, respectively, outside the operation region, and a control signal is applied.
[0081]
The second grounding means is means for grounding all the gate electrodes of the FET 3 by the resistors Rf1, Rf2, and Rf3. Thereby, all the gate electrodes of the FET 3 are always fixed to the ground potential.
[0082]
The other components are the same as those in the first embodiment, and the circuit operation is also the same as that in the first embodiment. Therefore, the description thereof is omitted, but according to this embodiment, a logic circuit is not provided. In addition, high power DPDT can be realized with one control terminal. Furthermore, the area occupied on the chip can be reduced as compared with the multi-stage FET structure.
[0083]
Further, the first and fourth separation means, the first and second connection means, and the first and second bias means are not limited to the connection example shown in FIG. 9, but are the same application circuit as in the first embodiment. Is also applicable. In other words, the first separating means may be connected between FET1 and FET2 (see FIG. 7A), and the first connecting means may be connected to either the source or drain electrode of FET2. Good (see FIG. 7B). Further, the first bias means may be connected to either the source or drain electrode of FET 1 (see FIG. 7C), and the second bias means is connected to either the source or drain electrode of FET 4. It is also possible (see FIG. 7D). The second connecting means may be connected to either the source or drain electrode of the FET 3 (see FIG. 7E), and the fourth separating means only needs to be connected between the FET 3 and the FET 4 (see FIG. 7). 7 (F)). The above connection changes can be performed independently, and the same effect can be obtained in all combinations.
[0084]
Further, although not shown, the second and third separating means only have to separate between FET1 and FET3, and FET2 and FET4, respectively, so that they move to the FET1 and FET2 side with respect to the output terminals OUT1 and OUT2, respectively. It doesn't matter.
[0085]
Even if the number of gate electrodes between the source and drain electrodes is increased, only the number of resistors Ra, Rb, Rf, Rh connected to each gate electrode is increased, and the other circuit configuration is the same as in FIG. .
[0086]
【The invention's effect】
As described in detail above, according to the present invention, a switch circuit device called DPDT (Double Pole Double Throw) using a GaAs FET at one control terminal can be realized without using a logic circuit. This eliminates the need for preparing a logic circuit, simplifies the circuit arrangement, and reduces the mounting area of the printed circuit board. In addition, power consumption can be reduced.
[0087]
When a multi-stage connection FET or a multi-gate FET is used, high power can be realized as compared with a single-stage FET single-stage switch. In particular, when the multi-gate structure is adopted, the area occupied on the chip can be reduced as compared with the multi-stage FET structure while being high power.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining the present invention.
FIG. 2 is a circuit diagram for explaining the present invention.
FIG. 3 is a circuit diagram for explaining the present invention.
FIG. 4 is a circuit diagram for explaining the present invention.
FIG. 5 is a circuit diagram for explaining the present invention.
FIG. 6 is a truth table for explaining the present invention.
FIG. 7 is a circuit diagram for explaining the present invention.
FIG. 8 is a circuit diagram for explaining the present invention.
9A is a cross-sectional view and FIG. 9B is a circuit diagram for explaining the present invention.
10A is a sectional view, FIG. 10B is a circuit block diagram, and FIG. 10C is a truth table for explaining a conventional example.

Claims (6)

First and second switching elements;
A first common input terminal connected to the source or drain of both the switching elements;
First and second output terminals respectively connected to the drains or sources of the switching elements;
One control terminal connected to the gate of the first switching element;
First bias means for applying a predetermined bias to the source or drain of the first switching element;
First connection means for connecting to the one control terminal and the source or drain of the second switching element;
First grounding means for grounding a gate of the second switching element;
A third switching element connected to the first output terminal;
A fourth switching element connected to the second output terminal and having a gate connected to the control terminal;
Second connection means for connecting the source or drain of the third switching element and the control terminal;
First separation means for DC-separating the first switching element and the second switching element;
A second separating means for DC-separating the first switching element and the third switching element;
Third separation means for DC-separating the second switching element and the fourth switching element;
The fourth separation means for DC-separating the third switching element and the fourth switching element;
Second grounding means for grounding a gate of the third switching element;
Second bias means for applying a predetermined bias to the source or drain of the fourth switching element;
A switch circuit device comprising a second common input terminal connected to the source or drain of the third and fourth switching elements. 2. The FET according to claim 1, wherein each of the first to fourth switching elements is an FET in which a source electrode and a drain electrode are provided on a channel layer surface, and a gate electrode is disposed between the source and drain electrodes. Switch circuit device. The first to fourth switching elements are respectively a first FET group, a second FET group, a third FET group, and a fourth FET group in which a plurality of FETs are connected in series in multiple stages. The switch circuit device according to claim 1. 2. The switch circuit device according to claim 1, wherein each of the first to fourth switching elements is a multi-gate FET in which a plurality of gate electrodes are arranged between a source electrode and a drain electrode. 2. The switch circuit device according to claim 1, wherein the first and second bias means always supply a constant positive DC voltage. 2. The switch circuit device according to claim 1, wherein each of the first, second, third, and fourth separation means is formed by a capacitor.

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