JP2005005701A5 - - Google Patents

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Publication number
JP2005005701A5
JP2005005701A5 JP2004155918A JP2004155918A JP2005005701A5 JP 2005005701 A5 JP2005005701 A5 JP 2005005701A5 JP 2004155918 A JP2004155918 A JP 2004155918A JP 2004155918 A JP2004155918 A JP 2004155918A JP 2005005701 A5 JP2005005701 A5 JP 2005005701A5
Authority
JP
Japan
Prior art keywords
semiconductor wafer
edge
etching
electrode
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004155918A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005005701A (ja
Filing date
Publication date
Priority claimed from KR1020030033844A external-priority patent/KR100585089B1/ko
Priority claimed from KR1020030070634A external-priority patent/KR100604826B1/ko
Application filed filed Critical
Publication of JP2005005701A publication Critical patent/JP2005005701A/ja
Publication of JP2005005701A5 publication Critical patent/JP2005005701A5/ja
Withdrawn legal-status Critical Current

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JP2004155918A 2003-05-27 2004-05-26 ウェーハエッジエッチング装置及び方法 Withdrawn JP2005005701A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020030033844A KR100585089B1 (ko) 2003-05-27 2003-05-27 웨이퍼 가장자리를 처리하기 위한 플라즈마 처리장치,플라즈마 처리장치용 절연판, 플라즈마 처리장치용하부전극, 웨이퍼 가장자리의 플라즈마 처리방법 및반도체소자의 제조방법
KR1020030070634A KR100604826B1 (ko) 2003-10-10 2003-10-10 웨이퍼 가장자리를 처리하기 위한 플라즈마 처리장치 및그 플라즈마 처리방법
US10/762,526 US20040238488A1 (en) 2003-05-27 2004-01-23 Wafer edge etching apparatus and method

Publications (2)

Publication Number Publication Date
JP2005005701A JP2005005701A (ja) 2005-01-06
JP2005005701A5 true JP2005005701A5 (ko) 2006-11-02

Family

ID=34108610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004155918A Withdrawn JP2005005701A (ja) 2003-05-27 2004-05-26 ウェーハエッジエッチング装置及び方法

Country Status (4)

Country Link
JP (1) JP2005005701A (ko)
CN (1) CN1595618A (ko)
DE (1) DE102004024893A1 (ko)
TW (1) TWI281713B (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101218114B1 (ko) 2005-08-04 2013-01-18 주성엔지니어링(주) 플라즈마 식각 장치
US20070068623A1 (en) * 2005-09-27 2007-03-29 Yunsang Kim Apparatus for the removal of a set of byproducts from a substrate edge and methods therefor
US8083890B2 (en) * 2005-09-27 2011-12-27 Lam Research Corporation Gas modulation to control edge exclusion in a bevel edge etching plasma chamber
US7909960B2 (en) 2005-09-27 2011-03-22 Lam Research Corporation Apparatus and methods to remove films on bevel edge and backside of wafer
US8398778B2 (en) * 2007-01-26 2013-03-19 Lam Research Corporation Control of bevel etch film profile using plasma exclusion zone rings larger than the wafer diameter
US8580078B2 (en) * 2007-01-26 2013-11-12 Lam Research Corporation Bevel etcher with vacuum chuck
US8137501B2 (en) * 2007-02-08 2012-03-20 Lam Research Corporation Bevel clean device
EP2260507B1 (en) 2008-03-31 2012-09-26 MEMC Electronic Materials, Inc. Methods for etching the edge of a silicon wafer, silicon wafer, etching apparatus
EP2359390A1 (en) 2008-11-19 2011-08-24 MEMC Electronic Materials, Inc. Method and system for stripping the edge of a semiconductor wafer
CN101930480B (zh) * 2009-06-19 2012-03-07 中芯国际集成电路制造(上海)有限公司 优化cmos图像传感器版图的方法
US8853054B2 (en) 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers
CN103715049B (zh) * 2012-09-29 2016-05-04 中微半导体设备(上海)有限公司 等离子体处理装置及调节基片边缘区域制程速率的方法
JP6348321B2 (ja) * 2013-05-17 2018-06-27 キヤノンアネルバ株式会社 エッチング装置
KR102116474B1 (ko) 2020-02-04 2020-05-28 피에스케이 주식회사 기판 처리 장치 및 기판 처리 방법
JP2022143889A (ja) 2021-03-18 2022-10-03 キオクシア株式会社 半導体製造装置及び半導体装置の製造方法

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