JP2005005549A - Semiconductor device, its packaging structure, and its manufacturing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small, thin, lightweight and low cost packaged semiconductor device mounting semiconductor chips and passive elements three-dimensionally at high density and capable of exhibiting multifunction and dealing with modification of specification, failure of component, and the like, and to provide its packaging structure and its manufacturing process. <P>SOLUTION: Insulation layers 11 and 21 are formed on a silicon substrate 1 to cover passive elements, e.g. capacitors 10 and inductors 20, and an IC chip 30 is face-up fixed in the insulation layer 21. In each insulation layer, electrodes of the buried elements are led out by means of plugs (16 and 26) to the upper surface where conductive layers (25 and the like) for interconnecting the elements and rearranging the electrode positions are formed to be bonded to the plugs. An insulation layer 44 covering the semiconductor device and being provided with external connection electrodes 45 is formed at the uppermost part. An IC chip 50 is fixed externally to a connection electrode 48 for mounting an electronic component in a recess 47 formed at an external connection terminal part. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device having an active element such as a semiconductor chip and a passive element such as a capacitor (capacitor) on a common substrate, a mounting structure thereof, and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, with the spread and development of portable small electronic devices such as mobile phones, the convenience and high performance of portable electronic devices are required, and the semiconductor devices used for them are becoming smaller, lighter and thinner. Or multi-function and cost reduction are required.
[0003]
For this reason, there is a strong demand for module products and package products that use small-sized and high-density packaging technology, and various packages are used to package semiconductor chips and passive elements necessary for realizing desired functions in one package. Many multi-chip module (MCM) products and system-in-package (hereinafter abbreviated as SiP) products have been developed.
[0004]
However, since the silicon substrate is conductive and leakage current and induced current flow, it has not been possible to use the silicon substrate as a SiP substrate for RF (Radio Frequency) circuits such as wireless devices. For this reason, in SiP for RF circuits, ceramic substrates such as LTCC (Low Temperature Co-Fired Ceramic) substrates, and FR-4 (NEMA (National Electrical Manufacturers Association) flame retardant standard) are used as substrates. In general, an organic material substrate such as a glass epoxy substrate is used, and electrical connection to a semiconductor chip is performed by flip chip bonding or wire bonding.
[0005]
FIG. 12 is a schematic sectional view of an example of RF SiP using an LTCC substrate. The LTCC substrate 61 is formed by firing a clay-like sheet (commonly known as a green sheet) made of alumina or the like mixed with a filler at a relatively low temperature of about 600 to 700 ° C. Usually, when producing SiP or the like, as shown in FIG. 12, a plurality of green sheets are stacked and pressed and then fired.
[0006]
The LTCC substrate 61 has the advantages of good heat transfer, high strength, and no warping. In addition, there is an advantage that the passive element can be formed by printed wiring. That is, the inductor 62 and the wiring portion 65 on the substrate can be formed by attaching a printing paste such as silver or tungsten to the surface of the green sheet by printing. Further, since the ceramic itself is a dielectric, the capacitors (capacitors) 63 and 64 can be formed by forming the counter electrode with the ceramic layer interposed therebetween. In addition, the connection part 66 which penetrates a board | substrate can be formed by embedding printing paste in the hole (through hole) opened by the drilling process in the green sheet.
[0007]
However, SiP using an LTCC substrate has the following problems 1 to 6.
1. The thickness of each layer cannot be made very thin (at least about 25 μm, usually about 50 μm). For this reason, it is difficult to thin the SiP by stacking.
2. Connection to the semiconductor chips 67 and 68 can only be performed by flip chip bonding or wire bonding. In flip chip bonding, a space for inserting an underfill material 69 is required, which protrudes in the surface direction from the size of the chip, resulting in a region where other elements cannot be disposed. In wire bonding, a space for providing a wire is required. Become. In any case, compact mounting is difficult.
3. Since firing is performed, the semiconductor chip cannot be embedded in the ceramic layer. Therefore, since it is necessary to fix the semiconductor chip on the substrate as described above, a separate protective material is required, which increases the bulk.
4). The method for forming the pattern is limited to printing.
5. The ceramic layers to be laminated must have the same thermal expansion coefficient and the same material.
6). As a result, the dielectric constant of each layer is also limited, and it is difficult to change between the respective layers, and the capacitance of the capacitor described above is limited.
7). Cost is high.
[0008]
On the other hand, Fig.13 (a) is a schematic sectional drawing of an example of SiP for RF using glass epoxy substrates, such as FR-4. The glass epoxy substrate 71 can be easily processed, such as being drilled with a drill or a laser. However, since the substrate is as thick as about 150 μm and the dielectric constant of the substrate is small, a capacitor is formed by the substrate itself. (However, the inductor 72 can be built-in.) Therefore, similar to the LTCC substrate, the semiconductor chip 77 is connected to the substrate by flip chip bonding or wire bonding on the user side, and the passive element 78 such as a capacitor is soldered (wireless connection) to the substrate. Compact mounting is difficult.
[0009]
Further, as shown in FIG. 13B, it has been studied to embed an electronic component in a glass epoxy substrate. However, since the height of the electronic component is high, the thickness of the layer in which the electronic component such as a semiconductor chip is embedded. Therefore, it is difficult to satisfy the thinning requirement for mobile products and the like.
[0010]
Therefore, a method for reducing the thickness of the semiconductor chip to be embedded and suppressing the overall thickness has been studied. However, since the conventional method for reducing the thickness of the semiconductor chip is a method of grinding using a support substrate, back grinding is performed. In addition to the protective tape laminating device, a laminating device with the support substrate and a peeling device after the laminating are newly required as equipment, and more materials are used. Causes the price to rise.
[0011]
Further, when a structure in which all the electronic parts are embedded is adopted, there is a problem that the parts cannot be exchanged or added, so that it is not possible to cope with the occurrence of a defective part or a failure, or a change in specifications.
[0012]
Further, in the method of fixing a semiconductor chip with high precision in a face-up type, the accuracy is 15 μm in the case of flip chip bonding, and the limit is 35 μm in the case of wire bonding (Japanese Patent Laid-Open No. 2-150041). (See JP-A-5-343449 and JP-A-11-26481). In the laser light emitting element, a die bonder that achieves an accuracy of about 5 μm has been developed. However, since the tact time is long and the accuracy cannot be obtained due to the influence of heat, a large-diameter wafer or substrate cannot be used.
[0013]
When using a silicon substrate, which is a highly reliable substrate, mounting a semiconductor chip face-up on this substrate, embedding and mounting passive elements in an insulating layer, and forming a wiring between each element, However, since there is no connection method other than flip chip bonding and wire bonding, it is difficult to reduce the thickness and size in both the surface direction and the height direction.
[0014]
On the other hand, on the semiconductor chip side, proposals have been made to integrate separately manufactured semiconductor chips using a technique such as an interlayer insulating film to achieve compact mounting and good circuit characteristics (Patent Documents described later) 1 and 2).
[0015]
For example, in Patent Document 1, a circuit having a predetermined function and one or more recesses are formed on a semiconductor substrate, and another type of semiconductor chip prepared in advance is fitted into the recesses. In this embodiment, a contact hole is formed at a necessary portion of the insulating layer, and then a metal such as aluminum is formed between integrated circuits on each semiconductor chip. A method of connecting by wiring is described. Patent Document 2 discloses various arrangement methods for stacking and mounting a plurality of semiconductor chips face up.
[0016]
However, none of the methods considers the production and mounting of passive elements. In the invention according to Patent Document 1, since all semiconductor chips are mounted on one substrate, there is a problem that the substrate area increases as the number of mounted semiconductor chips increases. On the other hand, the invention according to Patent Document 2 is intended only for high-density mounting of about two to three semiconductor chips, and requires another substrate for mounting stacked semiconductor chips.
[0017]
[Patent Document 1]
JP 2001-298149 A (page 4-6, FIG. 1 and FIG. 13)
[Patent Document 2]
JP 2001-189424 A (page 6-10, FIG. 2, FIG. 4, FIG. 6 and FIG. 8)
[0018]
[Problems to be solved by the invention]
In view of the above circumstances, the object of the present invention is to incorporate an active element such as a semiconductor chip and a passive element such as a capacitor at a high density, and can be made compact, thin, lightweight, low cost and multi-functional. It is another object of the present invention to provide a packaged semiconductor device, a mounting structure thereof, and a manufacturing method thereof, which can cope with a change in specifications and occurrence of a component defect or failure.
[0019]
[Means for Solving the Problems]
That is, according to the present invention, at least a face-up type active element (for example, a semiconductor chip; hereinafter the same) and a passive element (for example, a capacitor, an inductor, a resistance; hereinafter the same) are provided by an insulating layer formed on the substrate. And the active element and / or the passive element is connected to the wiring on the insulating layer through the insulating layer as a lower insulating layer, and the upper insulating layer formed on the wiring External connection terminals are provided via the upper insulating layer, and connection electrodes for mounting electronic components are provided using the upper insulating layer, and also relates to a method for manufacturing the semiconductor device,
Covering the active element with the lower insulating layer;
Covering the passive element with the lower insulating layer;
Forming the wiring connected to the active element and / or the passive element on the insulating layer via the lower insulating layer;
Providing an external connection terminal through the upper insulating layer formed on the wiring;
Providing the connection electrode for mounting an electronic component using the upper insulating layer;
The present invention relates to a method for manufacturing a semiconductor device.
[0020]
Furthermore, the present invention also relates to a semiconductor device mounting structure in which the semiconductor device is embedded in an insulating material layer and an external connection electrode is formed through the insulating material layer.
[0021]
The lower insulating layer is an insulating layer formed closer to the base than the wiring.
[0022]
According to the present invention, at least the face-up active element and the passive element are covered by the lower insulating layer formed on the substrate, and the active element and / or the passive element is the lower insulating layer. The active element and the passive element are embedded in the lower insulating layer while forming the necessary electrical connection, so that, for example, the adhesive strength between the insulating layers is The lower insulating layer is formed by laminating a plurality of insulating layers by using the semiconductor device, and a semiconductor device having a desired function can be packaged with a thickness as thin as possible and protected by the insulating layer.
[0023]
That is, various functions of the lower insulating layer, that is, a function capable of forming the passive element or the wiring by attaching a conductor or the like to the surface or the through-hole, covering the active element or the passive element, A function to hold these elements in place while protecting them from adverse mechanical, chemical, or electrical influences, easily forming a thin film with a small thickness, and easily with only the adhesive force between insulating layers The function that can make a laminated structure is fully utilized, and the role of high-density mounting and protection of elements, which has been shared by conventional circuit boards and mold resins, is realized only by the lower insulating layer. Therefore, the semiconductor device of the present invention is a small, thin, lightweight, low-cost SiP, and since the active element is held face-up, the width and pitch are fine via the lower insulating layer. Wiring Can be applied to intention, increases the degree of freedom in design, it is easy to multifunctional incorporates elements of various by increasing the insulating layer stacked.
[0024]
Furthermore, in the semiconductor device of the present invention, the external connection terminal is provided via the upper insulating layer formed on the wiring, and the connection electrode for mounting an electronic component is provided using the upper insulating layer. Therefore, when it becomes necessary to change the specifications of the semiconductor device, the change is easy. For example, since an active element such as a semiconductor chip is embedded in the lower insulating layer, another active element can be externally attached to the connection electrode, so that the performance of the SiP can be improved, the type or layout can be changed, or a new Functions can be added and the degree of freedom in designing the SiP is increased.
[0025]
Further, in the case of an RF circuit or the like, for example, when the basic part of the circuit does not change, but it is necessary to change the capacitance of some capacitors in accordance with the applied frequency, the semiconductor device of the present invention is used for the RF circuit. It is possible to cope with a wide range of frequencies by preparing a basic portion and externally attaching the capacitor to the connection electrode.
[0026]
In addition, when electronic parts such as semiconductor chips with a high defect rate or failure rate are mounted, the yield decreases due to the malfunction of SiP after being embedded in the insulating layer. However, such electronic parts are not attached to the connection electrodes. By enabling the attachment, it is possible to deal with the failure or failure of these electronic components by replacing the defective components, so that the yield of SiP is not reduced.
[0027]
The manufacturing method of the present invention is a method by which the semiconductor device of the present invention can be manufactured with good reproducibility, and the mounting structure of the present invention mounts the semiconductor device of the present invention on a circuit board or the like together with other electrical components. It is a structure that facilitates.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, for example, an active element (for example, a semiconductor chip) as the electronic component may be connected to the connection electrode provided on the surface of the lower insulating layer. For example, an active element that is changed in accordance with a change in specifications, an active element that is additionally provided, an active element having a high defect rate or failure rate, etc. is not embedded in the lower insulating layer as the active element. The connection electrode is preferably connected externally. Thereby, it is possible to cope with a change in specifications, an improvement in performance, addition of functions, occurrence of component defects and failures, and the like.
[0029]
At this time, in order to improve the durability of the semiconductor device, at least a connection portion between the electronic component and the connection electrode is preferably sealed with an insulating material. At this time, it is desirable that the electronic component is fixed in a recess of the upper insulating layer provided on the lower insulating layer in the vicinity of the external connection terminal, but is fixed on the upper insulating layer. May be. Moreover, although the said external connection terminal part is desirable also for the fixed position, another position may be sufficient.
[0030]
The upper insulating layer is formed on the wiring, and an external connection electrode is provided on the upper insulating layer. The wiring is on the lower insulating layer, and the external connection electrode is on the upper insulating layer. In addition, it is preferable that each is formed.
[0031]
In addition, a conductor for connecting the active element and / or the passive element and the wiring may be formed in a connection hole formed in the lower insulating layer. More detailed description is as follows.
[0032]
The semiconductor device of the present invention usually has a structure in which a plurality of insulating layers are stacked to form the lower insulating layer. Each insulating layer has a similar structure, and passive elements and semiconductor chips are formed or fixed in the lower part. Conductor plugs for extracting the electrodes of these elements arranged in the lower part to the upper surface of the insulating layer are insulated. The layers are formed so as to penetrate the layers in the vertical direction, and wirings or the like are provided on the upper surface so as to be connected to the conductor plugs to electrically connect the elements or to rearrange electrode positions. This structure can be realized by flip-chip mounting the semiconductor chip in a face-up manner.
[0033]
Specifically, the conductor plug and the wiring are formed by patterning the insulating layer corresponding to the conductor plug and the wiring, and embedding a metal such as copper in the pattern by plating. Good.
[0034]
The inductance element can be formed as a part of the wiring.
[0035]
The laminated structure is not particularly limited, and various structures can be considered. For example, a first passive element (for example, a capacitor; hereinafter the same) is covered with a first insulating layer, and a second passive element (for example, an inductor; hereinafter the same) is covered by a second insulating layer on the first insulating layer. ) And the semiconductor chip are covered, and the second active element as the electronic component is connected to the connection electrode using the third insulating layer (upper insulating layer) on the second insulating layer. The semiconductor device can be mentioned. In short, the semiconductor chip and the passive element are embedded in each insulating layer while forming necessary electrical connections, and the insulating layers are stacked to assemble a system having a desired function as one package. is there.
[0036]
When fixing the semiconductor chip on the base, both the alignment target on the base or the lower insulating layer and the electrode of the semiconductor chip are within the same field of view using, for example, a CCD (Charge Coupled Device) camera. It is preferable to position the semiconductor chip while recognizing with the above. Thereby, mounting accuracy of ± 2.5 μm can be achieved.
[0037]
When a plurality of semiconductor chips are required, stacking and fixing the plurality of semiconductor chips is advantageous for making the whole compact.
[0038]
When the substrate is thinned by grinding the back surface with the surface side of the substrate held by a protective sheet, a separation groove is formed in advance from the surface side of the substrate so as to reach the separation groove. By thinning the substrate, it is preferable that the thinning and singulation can be performed simultaneously.
[0039]
Further, when the semiconductor wafer to be a semiconductor chip is singulated, the semiconductor wafer is thinned by grinding the back surface opposite to the electrode surface with a protective sheet attached to the electrode surface of the semiconductor wafer. The semiconductor wafer is attached to the dicing sheet with the protective sheet attached, and then the protective sheet is removed and dicing is performed to obtain a thinned semiconductor chip. It is good to fix to. This eliminates the need for materials such as a support substrate for grinding and part of the processing equipment, thereby reducing the cost of thinning.
[0040]
The substrate is preferably a silicon substrate. A certain support is required for forming the insulating layer, and a silicon substrate is most suitable as such a support. The silicon substrate is not only superior in mechanical strength, heat resistance, heat transfer, flatness, and fine workability, but also has the advantage of being able to use the technology and equipment accumulated over the long history of semiconductor processing. There is. For example, a large material with excellent flatness can be obtained, a fine pattern can be easily formed, and the thickness can be easily reduced by the above-described grinding. Further, if necessary, the substrate can be used as a material for forming an active element instead of a simple substrate.
[0041]
Photosensitive polyimide is preferably used as the material for the insulating layer. Polyimide is not only a structural material with excellent heat resistance and mechanical strength, but also has excellent electrical characteristics such as low dielectric constant and high insulation. In addition, the insulating layer made of photosensitive polyimide can be easily patterned into a pattern corresponding to the conductor and the wiring by exposure and development.
[0042]
The mounting structure of the semiconductor device is preferably mounted together with other functional components on the insulating material layer. For example, a crystal oscillator such as a crystal resonator that cannot be incorporated into the semiconductor device or has no merit to be incorporated is preferably mounted together with the semiconductor device using a FR-4 standard glass epoxy substrate or the like.
[0043]
Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.
[0044]
Semiconductor device (SiP)
FIG. 1A is a schematic cross-sectional view showing an example of a semiconductor device (system-in-package; hereinafter abbreviated as SiP) according to a preferred embodiment of the present invention.
[0045]
In this SiP, a capacitor (capacitor) 10 is embedded on a substrate by an insulating layer 11 which is a first insulating layer, and an inductor 20 and an IC chip which is a semiconductor chip are formed thereon by an insulating layer 21 which is a second insulating layer. Insulating layer 44 having a function of a buffer layer that adjusts between the electrode position and wiring inside SiP and the electrode position of an external device, etc. while covering and protecting the inside of SiP at the top. Are stacked. Further, a second IC chip 50 is externally mounted on the external connection terminal portion of the insulating layer 44 so as to be embedded in a recess 47 formed in the insulating layer 44.
[0046]
Although it is not impossible to fabricate a SiP with a single insulating layer using the surface of the substrate as a wiring formation region, in order to make the size in the plane direction compact while realizing various functions, FIG. As shown, a structure in which a plurality of insulating layers are stacked is desirable.
[0047]
Each insulating layer has a similar structure, in which passive elements and semiconductor chips are formed or fixed in the lower part, and conductor plugs (16, 26, etc.) for extracting the electrodes of these elements arranged in the lower part to the upper surface. Etc. are formed through the insulating layer in the vertical direction, and the upper surface of the insulating layer is joined to a conductor plug (16, 26, etc.) to electrically connect each element or rearrange the electrode positions. A conductive layer (such as 25) is provided. With this structure, the semiconductor chip 30 can be flip-chip mounted face up. Each plug is composed of a laminate of a seed layer and an electrolytic plating layer formed by a method described later.
[0048]
Hereinafter, each part will be described in more detail.
[0049]
In this SiP, a silicon substrate 1 is used as a substrate, and a silicon oxide film 2 as an insulating layer is provided on the surface thereof to a thickness of 4000 mm or more. The thickness of the silicon substrate 1 is reduced to 50 μm by grinding. As the substrate, for example, a glass substrate or a ceramic substrate can be used in addition to the silicon substrate.
[0050]
On the silicon oxide film 2, a lower electrode 3 (a thin film of aluminum or copper having a thickness of about 1 μm), a dielectric layer 4, a protective layer 5 for the dielectric layer 4 (a silicon oxide film or a silicon nitride film), and a lower part The lead electrode 6 of the electrode 3 and the upper electrode 7 (a thin film of aluminum or copper having a thickness of about 1 μm) are sequentially laminated to form a capacitor 10.
[0051]
The material of the dielectric layer 4 is tantalum oxide Ta₂O₅, BST (Barium strontium titanate Ba_xSr_1-xTiO₃), PZT (lead zirconate titanate PbZr)_xTi_1-xO₃), Barium titanate BaTiO₃, Silicon nitride SiN, PI (polyimide), or silicon oxide SiO₂Is selected in consideration of the capacitance and breakdown voltage of the capacitor 10.
[0052]
For example, in order to form the capacitor 10 of about 0.1 pF to 40 pF, tantalum oxide Ta₂O₅Is used. In this case, when the film thickness is 40 nm, the unit capacitance is 7 fF / μm.²The withstand voltage is a current density of 1 μA / cm.²Is about 4V.
[0053]
As described above, the SiP based on the present embodiment is superior to the conventional method using the LTCC substrate in that a dielectric material can be selected from many materials and capacitors having various capacitances and breakdown voltages can be formed. Yes.
[0054]
An insulating layer 11 for covering the capacitor 10 and forming a conductive layer such as the inductor 20 is provided on the capacitor 10.
[0055]
The thickness of the insulating layer 11 is 50 μm or more so that an induced current is induced in the silicon substrate 1 by a current flowing through the inductor 20 and the Q value of the inductor 20 does not decrease. The Q value is an amount that represents the sharpness of resonance in forced vibration, and is an important index that indicates the performance of the inductor.
[0056]
The material of the insulating layer 11 is preferably a material having a low dielectric constant, such as polyimide (PI), polybenzoxazole (PBO), epoxy resin, or polyamide-imide resin having a dielectric constant of about 2.9 to 3.3. is there.
[0057]
On the insulating layer 11, an inductor 20, a wiring portion (not shown) and a land portion 17 are formed by a conductive layer, and the land portion 17 is connected to the electrodes 6 and 7 of the capacitor 10 by a plug portion 16. .
[0058]
An IC chip 30 that is a semiconductor chip is also fixed on the insulating layer 11 using a die attach film (DAF). In order to effectively use the space, the IC chip 30 can be disposed so as to overlap the land portion 17 and the wiring portion vertically.
[0059]
The thickness of the IC chip 30 is reduced to, for example, 50 μm by grinding. In addition, when two or more IC chips are stacked and mounted, or particularly when the thickness is limited, an IC chip whose thickness is reduced to, for example, 25 μm is mounted.
[0060]
An insulating layer 21 is provided on the inductor 20 and the IC chip 30, and a conductive layer 25 is provided on the insulating layer 21 to form a lead-out portion of the IC electrode 32.
[0061]
The conductive layer 25 has a role of rearranging the electrode position inside the SiP toward the outside, and the copper post 43 and the external connection electrode 45 provided on the conductive layer 25 are provided at a position convenient for connecting to an external device. It is done. The insulating layer 44 covers the semiconductor device flatly on the outermost side, protects the inside, and adjusts the outer shape of the SiP, thereby improving the reliability of the SiP. The conductive layer 25, the copper post 43, the external connection electrode 45, and the insulating layer 44 function as a buffer layer that adjusts so as to improve connection reliability when SiP is mounted on a mother substrate such as FR-4.
[0062]
When the external connection electrodes are solder bumps 45, the arrangement of the solder bumps 45 coincides with the standard electrode position of an area array type or peripheral type BGA (Ball Grid Array) package. The conductive layer 25 is provided with a land portion 27 at a position corresponding to the external connection electrode 45.
[0063]
Although illustration is omitted, the external connection electrode may be a land instead of the solder bump. In this case, the land is bonded to the counterpart electrode using a solder paste. The land arrangement is made to coincide with the standard electrode position of an LGA (Land Grid Array) package.
[0064]
Further, in the insulating layer 44, the second IC chip 50 is fixed so as to be embedded in the recess 47 provided in the external connection terminal portion where the external connection electrode 45 is formed, and the connection electrode 48 provided in the recess 47 is attached to the connection electrode 48. At least the connection portion is sealed with an insulating resin 49 which is an insulating material.
[0065]
As shown in FIG. 1A, when the second IC chip 50 is flip-chip connected, Ni / Au, UBM, solder bump, or Au stud bump is applied to the electrode portion 51 of the second IC chip 50. And the like and bonded to the connection electrode 48 by thermocompression bonding or ultrasonic pressure bonding. After the bonding, NCP (non-conductor paste), NCF (non-conductor film), ACP (anisotropic conductor film), or ACF (anisotropic conductor film) is used as the insulating resin 49.
[0066]
As shown in FIG. 1B, in the case of wire bonding connection with the wire 52, Ni / Au plating is performed on the connection electrode 48 and wire bonding is performed. After wire bonding, an epoxy resin, a polyimide resin, a phenol resin, or the like is used as the insulating resin 49 for sealing.
[0067]
Fabrication of semiconductor device (SiP)
Next, an example of a process for manufacturing the SiP shown in FIG. 1 will be described in the order of processes with reference to the schematic cross-sectional views of FIGS.
[0068]
First, as shown in FIG. 2 (1), a silicon substrate 1 such as a polycrystalline or single crystal silicon wafer (diameter: 8 inches, thickness: 725 μm, resistivity: 1 to 20 Ω · cm) having an orientation flat or notch. And a silicon oxide film 2 is formed on the surface of the silicon substrate 1 to a thickness of 4000 mm or more by a CVD (Chemical Vapor Deposition) method or a thermal oxidation method. As the substrate, for example, a glass substrate or a ceramic substrate can be used in addition to the silicon substrate.
[0069]
[Capacitor formation]
Next, as shown in FIG. 2B, the capacitor 10 is formed by a MIM-C (Metal Insulator Metal-Capacitor) process.
[0070]
First, as the lower electrode 3, for example, an aluminum or copper thin film is formed to a thickness of about 1 μm by sputtering or vapor deposition. Further, although not shown, a titanium nitride film having a thickness of 50 nm is formed as an oxidation reaction preventing film at a portion where the lower electrode 3 is in contact with the dielectric layer 4.
[0071]
Next, the dielectric layer 4 is formed by CVD or sputtering. The dielectric material is selected from tantalum oxide, BST, PZT, barium titanate, silicon nitride, polyimide, silicon oxide, or the like in consideration of the capacity and breakdown voltage of the capacitor 10.
[0072]
For example, in order to form the capacitor 10 of about 0.1 pF to 40 pF, the tantalum oxide Ta is used as the dielectric layer 4.₂O₅Use layers. In this case, when the film thickness is 40 nm, the unit capacitance is 7 fF / μm.²The withstand voltage is a current density of 1 μA / cm.²Is about 4V.
[0073]
Further, as the protective layer 5 of the dielectric layer 4, a silicon oxide film or a silicon nitride film is formed by a CVD method, and a window for taking out the electrode is formed by reactive ion etching (RIE). Then, an aluminum or copper thin film is formed as a lead electrode 6 and an upper electrode 7 of the lower electrode 3 by a sputtering method or a vapor deposition method in the place where the window is opened, and the capacitor 10 is completed.
[0074]
[Inductor formation]
Next, as shown in FIGS. 2 (3) to 4 (9), the insulating layer 11 is formed, and the conductor pattern is formed thereon, whereby the inductor (L) 20 and the like are manufactured.
[0075]
First, as shown in FIG. 2 (3), the insulating layer 11 is formed. The thickness of the insulating layer 11 is set to 50 μm or more so that an induced current flows through the silicon substrate 1 due to a current flowing through the inductor 20 and a Q value of the inductor 20 does not decrease.
[0076]
The material of the insulating layer 11 is preferably a material having a low dielectric constant. For example, polyimide, polybenzoxazole, epoxy resin, or polyamideimide resin having a dielectric constant of about 2.9 to 3.3 is used. The insulating layer 11 is formed by a spin coating method, a printing method, or a dispensing method.
[0077]
For example, when the insulating layer 11 is formed by spin coating using photosensitive polyimide, the insulating layer 11 having a thickness of 50 μm is formed under the following film forming conditions.
Viscosity of coating solution: 200 P (poise);
Spin coater rotation speed: rotate at 800 rpm for 30 seconds, followed by rotation at 1500 rpm for 30 seconds;
Pre-baking: heating at 90 ° C. for 300 seconds in a nitrogen gas atmosphere, followed by heating at 110 ° C. for 300 seconds.
[0078]
Next, as shown in FIG. 2 (4), a hole having a diameter of 50 μm, for example, is formed in the insulating layer 11 as a connection hole (via hole) 12 for producing a plug portion 16 for connection to the electrodes 6 and 7 of the capacitor 10. Form.
[0079]
When the insulating layer 11 is formed of photosensitive polyimide, the connection hole (via hole) 12 is formed by exposure and development under the following conditions.
Exposure: Using a stepper, broadband light is 400 mJ / cm in terms of i-line²Irradiation;
Development: Perform spray development using a spin developer; E. T.A. (Just Exposure Time) × 1.8 times;
Development inspection: by inspection machine;
Post-baking: Heating is performed at 150 ° C. for 0.5 hours in an atmosphere having an oxygen concentration of 40 ppm or less, followed by heating at 250 ° C. for 2.0 hours.
[0080]
After the development, a scum (resist residue) removal process on the surface of the insulating layer 11 is performed. The scum removal process is performed, for example, using a plasma ashing apparatus for 10 minutes under conditions of an oxygen flow rate of 100 sccm and an RF output of 100 (˜300) mW.
[0081]
Next, as shown in FIG. 3 (5), a laminated film of a titanium film and a copper film is formed as a seed layer (underlying metal layer) 13 by a sputtering method.
[0082]
Sputtering is performed, for example, under the following conditions.
Film thickness: After forming a 1600 mm thick titanium film, a 6000 mm thick copper film is laminated thereon.
Degree of vacuum: 3.6 × 10^-3Pa;
Sputtering pressure: 6.1 × 10^-1Pa;
Argon gas flow rate: 110-115cm³/ Min;
Sputtering power: 2000 to 3000W
[0083]
The seed layer (underlying metal layer) 13 may be formed by an electroless plating method.
[0084]
Next, a photoresist is applied, exposure corresponding to the conductor pattern such as the inductor 20 is performed, development and scum removal processing are performed, and a resist pattern 14 corresponding to the conductor pattern is formed as shown in FIG. Form.
[0085]
For example, a resist is applied by spin coating, and a resist pattern 14 is formed by development under the following conditions.
Spin coater rotation speed: Rotate at 500 rpm for 10 seconds, then rotate at 4000 rpm for 30 seconds, further rotate at 5000 rpm for 0.5 seconds, then gradually decelerate and stop for 3 seconds;
Development: Develop with a spin developer using developer P-7G. The process of rotating for 3 seconds at 50 rpm while spraying the developer on the substrate 1 and then stopping for 30 seconds is repeated 7 times;
Rinse: sprinkle pure water on the substrate 1 for 60 seconds while rotating at 500 rpm;
Spin dry: substrate 1 is rotated at 3000 rpm for 30 seconds, water is sprinkled off and dried;
Development inspection: An inspection machine is used.
[0086]
After the resist pattern 14 is formed, surface scum removal processing is performed. The scum removal process is performed, for example, using a plasma ashing apparatus for 10 minutes under the conditions of an oxygen flow rate of 100 sccm and an RF power of 100 (˜300) mW.
[0087]
Subsequently, as shown in FIG. 3 (7), using the resist pattern 14 as a mask, the conductive layer 15 is embedded by copper electroplating to form a plug portion 16, a land portion 17, a wiring portion 18, and an inductor portion 20. To do. The wiring part 18 is formed to a thickness of about 5 μm, for example.
[0088]
For example, the electrolytic plating is performed under the following conditions.
Washing: Immerse in bump cleaner for 30 minutes, then wash with water for 1 minute, then soak for 30 seconds in 5% aqueous sulfuric acid, then wash with water for 1 minute;
Degreasing and cleaning: performed at 40 ° C. for 1 minute;
Wetting treatment: 2 minutes at 40 ° C;
Pickling with water: 1 minute;
Copper sulfate plating solution: liquid temperature 25 ° C .; copper sulfate concentration: 50 g / l, sulfuric acid concentration: 25 g / l;
Glossy treatment: Cu Bright VF-2 (trade name of Ebara) (A liquid 20cm³/ L and B liquid: 10cm³/ L);
DK (cathode current density): 0.03 A / cm²
[0089]
After the completion of the electrolytic plating, as shown in FIG. 3 (8), the resist 14 is removed and the resist residue is ashed. For example, after removing the resist using an alkali solution, using a plasma ashing device, tetrafluoromethane CF₄While flowing oxygen and oxygen at a flow rate of 50 sccm, the residue is ashed by applying RF power of 25 W. This ashing process is repeated twice for 5 minutes each.
[0090]
Next, light etching for removing the oxide film on the surface of the conductive layer 15 is performed, and then the seed layer 13 (copper film and titanium film) other than the lower part of the conductive layer 15 is removed by etching using the conductive layer 15 as a mask. Thus, the inductor 20 and the land portion (connection terminal) 17 are formed (FIG. 4 (9)).
[0091]
Each layer is removed by etching under the following conditions using, for example, a wet etching apparatus.
[0092]
<Light etching of oxide film>
Hydrofluoric acid is used as the chemical solution.
[0093]
<Copper film>
Using SO-YO (manufactured by Kanto Chemical Co., Inc.) as a chemical solution, the chemical solution is sprayed and washed for 15 seconds while rotating the substrate 1 at 50 rpm. Next, pure water is sprayed for 60 seconds (rinsing) while rotating the substrate 1 at 500 rpm. Next, the substrate 1 is rotated at 3000 rpm for 30 seconds to shake off water and dry (spin drying).
[0094]
<Titanium film>
Using SO-1 (manufactured by Kanto Chemical Co., Inc.) as the chemical solution, the chemical solution is poured and washed for 25 seconds while rotating the substrate 1 at 50 rpm. Next, pure water is sprayed for 60 seconds (rinsing) while rotating the substrate 1 at 500 rpm. Next, the substrate 1 is rotated at 3000 rpm for 30 seconds to shake off water and dry (spin drying).
[0095]
[Thinning processing of IC chip]
Apart from the above, an IC chip 30 to be mounted on the silicon substrate 1 is prepared. Since the IC chip 30 is embedded in the resin layer, as shown in FIGS. 4 (10) to 4 (13), it is essential to perform processing for grinding the IC substrate to make the chip thinner. The thinning process is preferably performed at the stage where the IC chip 30 is formed on the wafer and before being singulated into chips.
[0096]
First, as shown in FIG. 4 (10), a backgrinding protective tape 34 is pasted as a substrate for thinning processing on the surface of an IC substrate (wafer) 31 on which an IC chip 30 is formed by a known method. . Since the protective tape 34 itself has an adhesive layer, it is attached with a pressure roller without heating. For example, a non-ultraviolet curable support type having a total thickness of 265 μm can be used. As the IC substrate 31, for example, a silicon substrate or a gallium arsenide substrate can be used.
[0097]
After applying the protective tape 34, grinding is performed using two types of grindstones having different roughnesses for rough grinding and finish grinding, so that the finished thickness of the substrate 31 is 50 μm (FIG. 4 (11)).
[0098]
For example, when the substrate 31 is a gallium arsenide substrate, rough grinding is performed at a spindle rotational speed of 3000 rpm using a # 600 grindstone, and finish grinding is performed at a spindle rotational speed of 3000 rpm using a # 2000 grindstone. The initial thickness is decreased from 120 μm to 70 μm.
[0099]
Next, as shown in FIG. 4 (12), a die attach film (DAF) 35 and a dicing sheet 36 are attached to the back surface of the IC substrate 31 thinned to a thickness of 50 μm. The DAF 35 and the dicing sheet 36 are of an integrated type, a die attach film 35 (thickness 10 to 50 μm), an adhesive layer (not shown) (thickness 5 μm), and a dicing sheet 36 (thickness made of polyolefin, for example) 100 μm) is a laminated structure. Pasting is performed manually or with an automatic machine.
[0100]
When using an automatic machine, for example, it is attached under the following conditions.
Automatic pasting machine: Use PM-8500 (Nitto Denko);
Temperature: 40 ° C .;
Pressure: 15N / cm²;
Laminating speed: 10 mm / sec;
[0101]
Next, the IC chip 30 is separated into pieces by dicing. In the case where tape cutting dicing is performed by attaching to the dicing sheet 36 as described above and performing tape cut dicing as described above, after bonding to the dicing ring under the above conditions, the backgrinding protective tape 34 is removed and full cut dicing is performed ( FIG. 4 (13)).
[0102]
Dicing is performed under the following conditions depending on the material of the IC substrate (wafer) 31.
<When cutting a 50 μm thick silicon substrate>
Blade: 2050 27HECC (manufactured by DISCO);
Spindle speed: 3000 rpm;
Feeding speed: 30mm / sec
<When cutting a 50 μm thick gallium arsenide substrate>
Blade: ZH126F (manufactured by DISCO);
Spindle speed: 3000 rpm;
Feed rate: 5 mm / sec;
Cutting depth: 40-85 μm
[0103]
[Installation of IC chip on substrate]
Next, the thinned and separated IC chip 30 is removed from the dicing sheet and mounted on the silicon substrate 1 (FIG. 5 (14)). At this time, the DAF 35 adheres and fixes the IC chip 30 on the insulating layer 11 as an insulating adhesive.
[0104]
Pickup from the dicing sheet is performed under the following conditions.
<For needle>
Plunge-up speed: 80 to 100 mm / sec;
Pickup holding time: 10-50 msec;
Pickup lift: 400 μm;
Expand: (minimum) 5 μm;
<For needleless>
Stroke: 3000 μm;
Speed: 10mm / sec
[0105]
FIG. 5 (15) is an explanatory view showing a method of die-bonding the IC chip 30 with a precision of 5 μm in a face-up state and fixing it onto the substrate 1 with a precision of 5 μm. The tool 37 for picking up the IC chip 30 is made of ceramics. Bonding (mounting) is performed at a tool temperature of 110 ° C., a load of 1 N / die, and a peel strength of 1 kgf or more per second. The alignment accuracy with the silicon substrate 1 is within ± 2.5 μm.
[0106]
This will be specifically described below. First, an inspection by pattern recognition is performed on a wafer expanded wafer or an IC chip 30 on a chip tray, and a non-defective product or a defective product is determined in advance. The tool 37 picks up only the IC chip 30 determined to be non-defective.
[0107]
As the coordinates at the time of pick-up, an alignment target 39 formed in advance on the substrate 1 and the positions of the pads (electrodes) 32 of the IC chip 30 to be mounted are input. The tool 37 sucks a position offset from the pad (electrode) 32 of the IC chip 30 by about 100 to 500 μm in one direction. As a result, the substrate 1 and the IC chip 30 can be aligned in a state where the alignment target 39 of the substrate 1 and the pad (electrode) 32 are both within the field of view of one CCD camera 38.
[0108]
More specifically, using the apparatus shown in FIG. 5 (15-1), the tool 37 that has attracted the IC chip 30 is vertically moved to the vicinity of the vertical mounting position in the vicinity of the horizontal mounting position of the IC chip 30. As shown in FIGS. 5 (15-2) and (15-3), the positions of the alignment target 39 of the substrate 1 and the pads (electrodes) 32 of the IC chip 30 are measured at this position. After the alignment of the direction, the tool is further lowered to press the IC chip 30 against the substrate 1 and heated under pressure to complete the mounting of the IC chip 30 on the substrate 1.
[0109]
At this time, the visual field of the camera is a rectangular shape having a length of 480 μm and a width of 640 μm, and pattern matching is performed by edge detection. Mounting accuracy achieves ± 2.5 μm. The mounting condition is, for example, 130 ° C. and 1 N / die. Heating is performed only with the heater of the tool 37, thereby preventing the copper wiring on the substrate 1 from being oxidized. After mounting, the tool 37 is cooled to room temperature by blowing with nitrogen gas.
[0110]
[Embedding IC chip and forming electrode lead-out part]
Next, as shown in FIGS. 5 (16) to 7 (20), the mounted IC chip 30 is embedded in an insulating layer to form a lead-out portion of the IC electrode 32. This process is substantially the same as the process shown in FIGS. 2 (3) to 4 (9). The insulating layer 21, the connection hole 22, the seed layer 23, the resist pattern 24, and the electrolysis are formed. It consists of processes, such as formation of the conductive layer 25 by plating.
[0111]
First, as shown in FIG. 5 (16), the insulating layer 21 is formed by a spin coating method, a printing method, or a dispensing method. With this insulating layer 21, the IC chip 30 is completely embedded up to the upper surface. The coating conditions for the insulating layer 21 are the same as the coating conditions for the insulating layer 11 on the silicon substrate.
[0112]
The material of the insulating layer 21 is preferably a material having a low dielectric constant. For example, polyimide, polybenzoxazole, epoxy resin, or polyamideimide resin is used.
[0113]
For example, when the insulating layer 21 is formed by spin coating using photosensitive polyimide, the insulating layer 21 is formed under the following film formation conditions.
Viscosity of coating solution: 200 P (poise);
Spin coater rotation speed: rotate at 800 rpm for 30 seconds, then rotate at 1200 rpm for 30 seconds;
Pre-baking: heating in a nitrogen gas atmosphere at 60 ° C. for 240 seconds, followed by heating at 90 ° C. for 240 seconds, and further heating at 110 ° C. for 240 seconds.
[0114]
Next, as shown in FIG. 6 (17), a connection hole 22 for extracting an electrode is formed in the insulating layer 21 with a diameter of, for example, 50 μm.
[0115]
When the insulating layer 21 is formed using photosensitive polyimide, the connection hole 22 is formed by exposure and development under the following conditions.
Exposure: Using a stepper, broadband light is 400 mJ / cm in terms of i-line²Irradiation;
Development: Perform spray development using a spin developer; E. T.A. × 1. 8 times;
Development inspection: by inspection machine;
Post-baking: Heating is performed at 150 ° C. for 0.5 hours in an atmosphere having an oxygen concentration of 40 ppm or less, followed by heating at 250 ° C. for 2.0 hours.
[0116]
After the development, a scum (residue) removing process on the surface of the insulating layer 11 is performed. The scum (residue) removing process is performed for 10 minutes using, for example, a plasma ashing apparatus under conditions of an oxygen flow rate of 100 sccm and an RF power of 100 mW.
[0117]
Next, as shown in FIG. 6 (18), a laminated film of a titanium film and a copper film is formed as a seed layer (underlying metal layer) 23 by a sputtering method.
[0118]
Sputtering is performed, for example, under the following conditions.
Film thickness: After forming a 1600 mm thick titanium film, a 6000 mm thick copper film is laminated thereon;
Degree of vacuum: 3.6 × 10^-3Pa;
Sputtering pressure: 6.1 × 10^-1Pa;
Argon gas flow rate: 110-115cm³/ Min;
Sputtering power: 2000 to 3000W
[0119]
Next, a photoresist is applied, exposure corresponding to the wiring pattern is performed, development and scum removal processing are performed, and a resist pattern 24 corresponding to the wiring pattern is formed as shown in FIG.
[0120]
For example, a resist is applied by spin coating, and a resist pattern 24 is formed by development under the following conditions.
Spin coater rotation speed: Rotate at 500 rpm for 10 seconds, then rotate at 4000 rpm for 30 seconds, further rotate at 5000 rpm for 0.5 seconds, then gradually decelerate and stop for 3 seconds;
Pre-bake: heat at 110 ° C. for 30 minutes;
Exposure: using a stepper;
Development: Develop with a spin developer using developer P-7G. The process of rotating for 3 seconds at 50 rpm while spraying the developer on the substrate 1 and then stopping for 30 seconds is repeated 7 times;
Rinse: sprinkle pure water on the substrate 1 for 60 seconds while rotating at 500 rpm;
Spin dry: substrate 1 is rotated at 3000 rpm for 30 seconds, water is sprinkled off and dried;
Development inspection: An inspection machine is used.
[0121]
After the resist pattern 24 is formed, a surface scum removal process is performed. The scum removal process is performed, for example, using a plasma ashing apparatus for 10 minutes under conditions of an oxygen flow rate of 100 sccm and an RF power of 100 mW.
[0122]
Subsequently, as shown in FIG. 7 (20), using the resist pattern 24 as a mask, a conductive layer 25 is embedded in the connection hole 22 and the wiring pattern portion by, for example, copper electroplating, and a plug portion 26 and a land portion 27 are embedded. , And wiring parts. For example, the plug portion 26 has a diameter of 50 μm, the land portion 27 has a diameter of 70 μm, and the wiring portion has a thickness of about 5 μm. At this time, a connection electrode 48 for connecting the second IC chip 50 and a wiring (not shown) connected to the connection electrode 48 are also formed.
[0123]
For example, the electrolytic plating is performed under the following conditions.
Washing: Immerse in bump cleaner for 30 minutes, then wash with water for 1 minute, then soak for 30 seconds in 5% aqueous sulfuric acid, then wash with water for 1 minute;
Degreasing and cleaning: performed at 40 ° C. for 1 minute;
Wetting treatment: 2 minutes at 40 ° C;
Pickling with water: 1 minute;
Copper sulfate plating solution: liquid temperature 25 ° C .; copper sulfate concentration: 50 g / l, sulfuric acid concentration: 25 g / l;
DK (cathode current density): 0.03 A / cm²
[0124]
After the completion of the electrolytic plating, the resist 24 is removed and the resist residue is ashed. For example, after removing the resist 24 using an alkaline solution, a tetrafluoromethane CF is used using a plasma ashing device.₄While flowing oxygen and oxygen at a flow rate of 50 sccm, the residue is ashed by applying RF power of 25 W. This ashing process is repeated twice for 5 minutes each.
[0125]
[Formation of buffer layer and external connection electrode]
Next, as shown in FIGS. 7 (21) to 9 (27), as a buffer layer for improving connection reliability with a mother substrate such as FR-4, a copper post 43 for extracting external connection electrodes, An insulating layer 44 that covers the other portions flatly is formed, a second IC chip is mounted, and an external connection electrode 45 is formed on the exposed surface of the copper post 43.
[0126]
First, after removing the oxide film on the surface of the conductive layer 25 by light etching using hydrofluoric acid, a photosensitive dry film (resist film) 41 is attached. After exposing a part of the resist film 41 by masking, the cover film is peeled off, developed, scum-removed, and holes 42 corresponding to the copper posts 43 are formed in the resist film 41 (FIG. 7 (21)).
[0127]
Thereafter, as shown in FIG. 7 (22), electrolytic plating using the resist film 41 as a mask is performed, and copper is embedded in the voids 42 to form, for example, copper posts 43 having a diameter of 150 μm and a height of 100 μm.
[0128]
Next, as shown in FIG. 8 (23), the dry film 41 is peeled off, and then the seed layer 23 other than the lower part of the conductive layer 25 is removed by etching using the conductive layer 25 as a mask to form the conductive layer 25. The formation of the plug part 26, the land part 27, the connection electrode 48, the wiring part, etc. is completed.
[0129]
The removal of the copper film and the titanium film of the seed layer 23 is performed under the following conditions using, for example, a wet etching apparatus.
<Copper film>
Using SO-YO as a chemical solution, the chemical solution is sprayed and cleaned for 15 seconds while rotating the substrate 1 at 50 rpm. Next, pure water is sprayed for 60 seconds (rinsing) while rotating the substrate 1 at 500 rpm. Next, the substrate 1 is rotated at 3000 rpm for 30 seconds to shake off water and dry (spin drying).
<Titanium film>
Using SO-1 as the chemical solution, the chemical solution is poured and washed for 25 seconds while rotating the substrate 1 at 50 rpm. Next, pure water is sprayed for 60 seconds (rinsing) while rotating the substrate 1 at 500 rpm. Next, the substrate 1 is rotated at 3000 rpm for 30 seconds to shake off water and dry (spin drying).
[0130]
Next, as shown in FIG. 8 (24), with the copper post 43 standing, an insulating layer 44 such as epoxy resin, PBO, PI resin, or phenol resin is formed by spin coating, printing, or transfer molding. To completely cover the copper post 43. The insulating layer 44 is degassed in a vacuum oven and further cured at 120 ° C. for 1 hour and subsequently at 150 ° C. for 2 hours.
[0131]
At this time, for example, when the insulating layer 44 is attached by a printing method, squeezing is performed so as to cover the upper surface of the copper post 43 with a thickness of 10 μm or more, and the surface unevenness is finished within about ± 30 μm. At this time, the resin is prevented from entering the recess 47.
[0132]
After the resin is cured, as shown in FIG. 9 (25), the surface is ground to cue the copper post 43. At this time, for example, grinding is performed using a # 600 grindstone at a spindle rotation speed of 3000 rpm. Thereafter, an activation process is performed to prevent an oxide film from being formed on the exposed portions of the connection electrode 48 and the copper post 43.
[0133]
Next, as shown in FIG. 9 (26), the second IC chip 50 is fixed to the recess 47 and electrically connected to the connection electrode 48. In the case of flip-chip connection, Ni / Au, UBM, solder bump, Au stud bump or the like is formed on the electrode portion 51 of the IC chip 50 and joined to the connection electrode 48 by thermocompression bonding or ultrasonic pressure bonding. After bonding, the bonding portion is sealed using NCP, NCF, ACP, ACF, or the like as the insulating resin 49.
[0134]
When connecting by wire bonding, Ni / Au plating is performed on the connection electrode 48 and wire bonding is performed. After wire bonding, sealing is performed with an epoxy resin, a polyimide resin, or a phenol resin.
[0135]
Next, as shown in FIG. 9 (27), the external connection electrode 45 is formed on the exposed portion of the copper post 43. As the external connection electrodes 45, solder ball bumps, lead-free solder ball bumps, Au stud bumps, LGA, or print bumps are formed.
[0136]
For example, as shown in FIG. 9 (27), when forming a solder ball, after applying the flux, a solder ball having a diameter of about 0.15 mm is attached, and fusion bonding is performed by reflow. After joining, the flux is washed and completed.
[0137]
The arrangement of the external connection electrodes 45 of this package is an arrangement corresponding to an area array type or peripheral type BGA or LGA.
[0138]
[Thinner and thinner package]
After the external connection electrode 45 is formed, the package is thinned and separated.
[0139]
First, as shown in FIG. 10 (28), the silicon substrate 1 is half-cut. At this time, for example, grinding is performed at a spindle rotation speed of 3000 rpm using a # 1500 grindstone to form a groove 46 having a depth of 70 μm in the silicon substrate 1.
[0140]
After half-cutting, the back surface of the silicon substrate 1 is ground to reduce the thickness and separate the pieces at the same time. At this time, a backgrinding protective tape is applied to the surface side of the silicon substrate 1, and for example, rough grinding is performed at 4800 rpm using a # 360 grindstone, and then finish grinding is performed at 5500 rpm using a # 600 grindstone. The substrate 1 is ground to a thickness of 50 μm, for example. Thereafter, the backgrinding protective tape is peeled off and attached to the transfer film, whereby the individualization of the SiP100 is completed (FIG. 10 (29)).
[0141]
SiP mounting structure
FIG. 11 is a schematic cross-sectional view showing a SiP mounting structure.
[0142]
FIG. 11A shows an example in which the above-described SiP 100 is mounted on an FR-4 standard glass epoxy substrate together with other semiconductor chips 78, a crystal resonator 80, and the like. The SiP 100 is embedded in the glass epoxy substrate 71. However, it is preferable to mount a material that cannot be incorporated into the SiP, such as a crystal resonator, or that has no merit of incorporation, on the glass epoxy substrate. As described above, by mounting the SiP 100 together with other semiconductor chips and functional components, a more multifunctional device can be realized.
[0143]
FIG. 11B shows an example in which the SiP 100 is embedded in the interposer layer 81 and mounted. In the figure, the electrode pitch (0.1 to 0.3 mm) of the SiP 100 and the electrode pitch (0.5 mm) of the external device can be adjusted by the rearrangement wiring using the interposer layer 81 by the interposer layer 81. Therefore, even if the wiring width and wiring pitch in the SiP are further reduced to reduce the size of the SiP, the degree of freedom in the arrangement of the external connection electrodes 83 can be obtained and the number of pins (number of external terminals) can be increased.
[0144]
As described above, according to the embodiment of the present invention, passive elements and face-up active elements are mounted on a silicon substrate, and these elements are covered with an insulating layer and embedded. It is possible to form a conductor plug for pulling out the electrode of the element in the upper part through the insulating layer in the vertical direction and to form a necessary wiring on the insulating layer.
[0145]
Thus, by adopting a structure capable of flip-chip mounting and face-up mounting, each element can be mounted three-dimensionally at a high density, and the design freedom of the entire SiP can be improved. . The capacitor formed on the silicon substrate and the IC part can be brought close to each other, and the high frequency characteristics can be improved.
[0146]
Further, since the second IC chip is fixed to the surface of the insulating layer and connected to the connection electrode provided on the surface of the insulating layer, the second IC chip is changed as the specification is changed. In addition, by making additional IC chips, IC chips with high defective product rate and failure rate, etc., for specification change, performance improvement and function addition, parts failure and failure occurrence etc., respectively Can respond.
[0147]
In particular, since an external IC can be mounted on a SiP in which a passive element is formed on a silicon substrate and an active element is embedded, the degree of freedom of SiP design is further increased. In addition, when an IC or the like having a low yield is mounted, the yield of the entire SiP is lowered after being embedded, but the yield of the entire SiP is not lowered by being externally attachable. Then, by installing a land for flip chip connection or wire bonding connection on the SiP, it is possible to cope with the IC layout and the product type change and to cope with the model change at an early stage.
[0148]
At this time, at least the connection portion between the second IC chip and the connection electrode is sealed with an insulating material, and the second IC chip is fixed in the recess provided in the insulating layer. Can be improved.
[0149]
When fixing the IC chip on the substrate, the IC chip is positioned while recognizing both the alignment target on the substrate or the insulating layer and the electrode of the IC chip in the same field of view using, for example, a CCD camera. Therefore, the IC chip can be fixed face-up with a mounting accuracy of ± 2.5 μm.
[0150]
Further, when a plurality of IC chips are stacked, by thinning each IC by grinding, it becomes possible to mount a large number of ICs without changing the thickness of the entire SiP, and it can be easily multi-functionalized.
[0151]
In addition, since a silicon substrate is used as a substrate, not only is it excellent in mechanical strength, heat resistance, heat transfer properties, etc., but it is possible to use technologies and equipment accumulated over the long history of semiconductor processing. Low cost and efficient production is possible. For example, a large and extremely flat wafer can be obtained and can be easily thinned by grinding. In addition, by performing batch processing using semiconductor processing technology on the wafer, it is possible to easily form a fine pattern and efficiently perform rewiring processing such as wiring formation with a small wiring width and pitch and change of electrode position. Therefore, the entire SiP can be reduced in size. Further, if necessary, an active element such as a transistor can be formed in accordance with a conventional method instead of a simple substrate, and can be incorporated into SiP.
[0152]
In addition, since photosensitive polyimide is used as the material for the insulating layer, it has excellent electrical characteristics such as excellent heat resistance, mechanical strength, low dielectric constant, high insulation, and the like. In addition, the insulating layer made of photosensitive polyimide can be easily patterned by exposure and development.
[0153]
Further, the obtained SiP can be embedded in an FR-4 substrate or the like, and a more multifunctional SiP can be formed.
[0154]
It goes without saying that the embodiment of the present invention described above can be appropriately changed with respect to conditions, devices, and the like without departing from the spirit of the invention.
[0155]
[Effects of the invention]
According to the present invention, at least the face-up type active element and the passive element are covered by the lower insulating layer formed on the substrate, and the active element and / or the passive element is interposed between the lower insulating layer and the insulating layer. Because it is connected to the upper wiring, the active and passive elements are embedded in the lower insulating layer while forming the necessary electrical connections, and multiple insulating layers are stacked using, for example, the adhesive force between the insulating layers Thus, a lower insulating layer is formed, and a semiconductor device having a desired function can be packaged with a thickness as thin as possible and protected by the insulating layer.
[0156]
That is, various functions of the lower insulating layer, that is, a function capable of forming a passive element or wiring by attaching a conductor or the like to the surface or the through-hole, and a mechanical element from outside by covering the active element or the passive element A function to hold these elements in place while protecting them from chemical or electrical adverse effects, a thin film with a small thickness can be easily formed, and a laminated structure can be easily formed only by the adhesive force between insulating layers. Since the functions that can be made are fully utilized and the role of high-density mounting and protection of elements, which has been shared by conventional circuit boards and mold resins, is realized by only the lower insulating layer, the present invention This semiconductor device is a small, thin, light, low-cost SiP, and the active element is held face up, so that fine wiring with a small width and pitch can be arbitrarily provided through the lower insulating layer. Can design Degree is increased, it is easy to multifunctional incorporates elements of various by increasing the insulating layer stacked.
[0157]
Furthermore, in the semiconductor device of the present invention, the external connection terminal is provided via the upper insulating layer formed on the wiring, and the connection electrode for mounting the electronic component is provided using the upper insulating layer. When there is a need to change the specifications, it is easy to change. For example, since an active element such as a semiconductor chip is embedded in the lower insulating layer, another active element can be externally attached to the connection electrode, thereby improving the performance of the SiP, changing the product type or layout, This can be added, and the degree of freedom in designing the SiP is increased.
[0158]
Further, in the case of an RF circuit or the like, for example, when the basic part of the circuit does not change, but it is necessary to change the capacitance of some capacitors in accordance with the applied frequency, the semiconductor device of the present invention is used for the RF circuit. It is possible to cope with a wide range of frequencies by producing a basic part and externally attaching a capacitor to the connection electrode.
[0159]
In addition, when electronic parts such as semiconductor chips with a high defect rate or failure rate are mounted, the yield decreases due to the malfunction of SiP after being embedded in the insulating layer. However, such electronic parts are not attached to the connection electrodes. By enabling the attachment, it is possible to deal with the failure or failure of these electronic components by replacing the defective components, so that the yield of SiP is not reduced.
[0160]
The manufacturing method of the present invention is a method by which the semiconductor device of the present invention can be manufactured with good reproducibility, and the mounting structure of the present invention mounts the semiconductor device of the present invention on a circuit board or the like together with other electrical components. It is a structure that facilitates.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing an example of a SiP (system in package) according to a preferred embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 3 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 4 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 5 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 6 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 7 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 8 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 9 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 10 is a schematic cross-sectional view showing a process for producing SiP.
FIG. 11 is a schematic cross-sectional view showing an example of mounting SiP.
FIG. 12 is a schematic cross-sectional view showing an example of an RF system-in-package using a conventional LTCC substrate.
FIG. 13 is a schematic cross-sectional view showing an example of an RF system-in-package using a conventional FR-4 glass epoxy substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Lower electrode, 4 ... Dielectric layer, 5 ... Protective layer, 6 ... Lead electrode, 7 ... Upper electrode, 10 ... Capacitor, 11 ... Insulating layer, 12 ... Connection hole (Via hole), 13 ... seed layer (underlying metal layer), 14 ... resist pattern, 15 ... copper conductive layer, 16 ... plug part, 17 ... land part, 18 ... wiring part, 20 ... inductor, 21 insulating layer, 22 ... Connection hole for electrode extraction, 23 ... seed layer (underlying metal layer), 24 ... resist pattern, 25 ... conductive layer, 25A ... intermediate conductive layer, 26 ... plug part, 27 ... land part, 28 ... intermediate insulating layer, 29 ... Insulating layer, 30, 30A, 30B ... IC chip, 31, 31A, 31B ... IC substrate, 32, 32A, 32B ... IC electrode, 33, 33B ... Passivation film, 34 ... Backgrinding protective tape, 5 ... Die attach film (DAF), 36 ... Dicing sheet, 35 ... Adhesive layer, 41 ... Photosensitive dry film (resist film), 42 ... Hole, 43 ... Copper post, 44 ... Insulating layer, 45 ... External connection electrode , 46 ... groove, 47 ... recess, 48 ... connection electrode, 49 ... insulating resin, 50 ... second IC chip, 51 ... electrode of the second IC chip, 52 ... wire, 61 ... LTCC substrate, 62 ... Inductors, 63, 64 ... capacitors, 65 ... wiring portions on the substrate surface, 66 ... connection portions penetrating the substrate, 67, 68 ... semiconductor chip, 69 ... underfill material, 71 ... glass epoxy substrate such as FR-4 standard , 72 ... inductor, 75 ... wiring part on the substrate surface, 76 ... connection part penetrating the substrate, 77 ... semiconductor chip, 78 ... passive element, 77b ... embedded semiconductor chip, 78b ... buried Or a passive element, 79 ... underfill material, 80 ... crystal oscillator, 81 ... interposer layer, 82 ... internal connection electrode, 83 ... external connection electrodes, 100 ... semiconductor device (SiP)

Claims (28)

At least a face-up type active element and a passive element are covered with an insulating layer formed on the substrate, and the active element and / or the passive element is interposed between the insulating layer as a lower insulating layer and the insulating layer. An external connection terminal is provided via an upper insulating layer formed on the wiring, and a connection electrode for mounting an electronic component is provided using the upper insulating layer. A semiconductor device. The semiconductor device according to claim 1, wherein the electronic component is connected to the connection electrode provided on the surface of the lower insulating layer, and at least the connection portion is sealed with an insulating material. The semiconductor device according to claim 2, wherein the electronic component is fixed in a recess of the upper insulating layer provided on the lower insulating layer in the vicinity of the external connection terminal. The semiconductor device according to claim 1, wherein an external connection electrode is provided on the upper insulating layer formed on the wiring. The semiconductor device according to claim 4, wherein the wiring is formed on the lower insulating layer and the external connection electrode is formed on the upper insulating layer. 2. The semiconductor device according to claim 1, wherein a conductor for connecting the active element and / or the passive element and the wiring is formed in a connection hole formed in the lower insulating layer. The semiconductor device according to claim 1, wherein the wiring forms an inductance element. 2. The semiconductor device according to claim 1, wherein the first passive element is covered with a first insulating layer, and the second passive element and the semiconductor chip are covered with a second insulating layer on the first insulating layer. The semiconductor device according to claim 8, wherein a second active element as the electronic component is connected to the connection electrode using a third insulating layer on the second insulating layer. The semiconductor device according to claim 1, wherein the base is a silicon substrate. The semiconductor device according to claim 1, wherein the insulating layer is made of photosensitive polyimide. A mounting structure for a semiconductor device, wherein the semiconductor device according to claim 1 is embedded in an insulating material layer, and an external connection electrode is formed through the insulating material layer. The mounting structure of a semiconductor device according to claim 12, wherein another functional component is mounted on the insulating material layer. At least a face-up type active element and a passive element are covered with an insulating layer formed on the substrate, and the active element and / or the passive element is interposed between the insulating layer as a lower insulating layer and the insulating layer. An external connection terminal is provided via an upper insulating layer formed on the wiring, and a connection electrode for mounting an electronic component is provided using the upper insulating layer. A method for manufacturing a semiconductor device, comprising:
Covering the active element with the lower insulating layer;
Covering the passive element with the lower insulating layer;
Forming the wiring connected to the active element and / or the passive element on the insulating layer via the lower insulating layer;
Providing an external connection terminal through the upper insulating layer formed on the wiring;
And a step of providing the connection electrode for mounting an electronic component using the upper insulating layer. The method of manufacturing a semiconductor device according to claim 14, wherein the electronic component is connected to the connection electrode provided on the surface of the lower insulating layer, and at least the connection portion is sealed with an insulating material. The method of manufacturing a semiconductor device according to claim 15, wherein the electronic component is fixed in a recess of the upper insulating layer provided on the lower insulating layer in the vicinity of the external connection terminal. The semiconductor device manufacturing method according to claim 14, wherein the upper insulating layer is formed on the wiring, a connection hole is formed in the insulating layer, and an external connection electrode connected to the wiring is formed on the connection hole. Method. The method for manufacturing a semiconductor device according to claim 14, wherein a connection hole is formed in the lower insulating layer, and a conductor is formed in the connection hole so as to connect the active element and / or the passive element and the wiring. . The method for manufacturing a semiconductor device according to claim 14, wherein an inductance element is formed by the wiring. The method of manufacturing a semiconductor device according to claim 14, wherein the formation of the wiring and the connection to the active element and the passive element are performed by plating. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the first passive element is covered with a first insulating layer, and the second passive element and the semiconductor chip are covered with a second insulating layer on the first insulating layer. . The method for manufacturing a semiconductor device according to claim 21, wherein a second active element as the electronic component is connected to the connection electrode using a third insulating layer formed on the second insulating layer. When fixing the semiconductor chip on the substrate, the semiconductor chip is positioned while recognizing both the alignment target on the substrate or the lower insulating layer and the electrode of the semiconductor chip within the same field of view. A method for manufacturing a semiconductor device according to claim 14. The method of manufacturing a semiconductor device according to claim 14, wherein the base is thinned by grinding a back surface in a state where the front side of the base is held by a protective sheet. 25. The method of manufacturing a semiconductor device according to claim 24, wherein a separation groove is formed from the surface side of the base body, and the base body is thinned so as to reach the separation groove, thereby obtaining an individual semiconductor device. When singulating a semiconductor wafer to be a semiconductor chip, by grinding a back surface opposite to the electrode surface in a state where a protective sheet is attached to the electrode surface of the semiconductor wafer, the semiconductor wafer is thinned, The semiconductor wafer is attached to the dicing sheet with the protective sheet attached, and then the protective sheet is removed and dicing is performed to obtain a thinned semiconductor chip, and the semiconductor chip is fixed on the substrate. A method for manufacturing a semiconductor device according to claim 14. The method for manufacturing a semiconductor device according to claim 14, wherein a silicon substrate is used as the base. The method for manufacturing a semiconductor device according to claim 14, wherein the insulating layer is formed of photosensitive polyimide.

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