CN102412250A - Semiconductor packaging structure, integrated passive element and fabrication method thereof - Google Patents
Semiconductor packaging structure, integrated passive element and fabrication method thereof Download PDFInfo
- Publication number
- CN102412250A CN102412250A CN201110344674XA CN201110344674A CN102412250A CN 102412250 A CN102412250 A CN 102412250A CN 201110344674X A CN201110344674X A CN 201110344674XA CN 201110344674 A CN201110344674 A CN 201110344674A CN 102412250 A CN102412250 A CN 102412250A
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive layer
- patterned conductive
- patterning
- pattern dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a semiconductor packaging structure, an integrated passive element and a fabrication method thereof. The integrated passive element comprises a substrate, a first patterned conductive layer, a patterned capacitive layer, a second patterned conductive layer, a first patterned dielectric layer, a third patterned conductive layer and a second patterned dielectric layer. The first patterned conductive layer is arranged on the substrate and provided with a plurality of electrodes. The patterned capacitive layer is arranged on the first patterned conductive layer. The second patterned conductive layer is arranged on the patterned capacitive layer. The first patterned dielectric layer is arranged on the first patterned conductive layer, the patterned capacitive layer and the second patterned conductive layer, and electrodes are exposed. The third patterned conductive layer is arranged on the first patterned dielectric layer, and electrodes are exposed. The second patterned dielectric layer is arranged on the first patterned dielectric layer and the third patterned conductive layer, and electrodes are exposed.
Description
Technical field
The present invention relates to a kind of passive component and manufacturing approach thereof, and particularly relate to a kind of integrated passive component and manufacturing approach thereof.
Background technology
The normally indivedual making of Traditional passive element (for example capacity cell, inductance element and resistive element) back is electrically connected to circuit board according to circuit design.Yet the traditional passive element occupies certain space (highly), and this is unfavorable for the thinning of electronic product.Moreover the electrical numerical value of traditional passive element (for example capacitance, inductance value and resistance value) meets specific standard, and this does not meet the requirement of circuit design.
Summary of the invention
The object of the present invention is to provide a kind of integrated passive component, it has slim outward appearance.
Another object of the present invention is to provide a kind of manufacturing approach of integrated passive component, in order to produce integrated passive component.
For reaching above-mentioned purpose; The present invention provides a kind of integrated passive component, and it comprises a substrate, one first patterned conductive layer, patterning electric capacity layer, second patterned conductive layer, first pattern dielectric layer, the 3rd patterned conductive layer and second pattern dielectric layer.First patterned conductive layer is configured on the substrate, and has a plurality of electrodes.Patterning electric capacity layer is configured on part first patterned conductive layer.Second patterned conductive layer is configured on the patterning electric capacity layer.First pattern dielectric layer is configured on first patterned conductive layer, patterning electric capacity layer and second patterned conductive layer, exposes electrode, and has first patterned conductive layer and partly second patterned conductive layer of a plurality of openings to expose part.The 3rd patterned conductive layer is configured on first pattern dielectric layer, and the opening of filling part is to connect second patterned conductive layer.Second pattern dielectric layer is configured on first pattern dielectric layer and the 3rd patterned conductive layer, and exposes electrode.
The present invention proposes a kind of semiconductor package, and it comprises a support plate, an active element and an integrated passive component.Active element is installed on the support plate, and integrated passive component is installed on the support plate and comprises a substrate, one first patterned conductive layer, patterning electric capacity layer, second patterned conductive layer, first pattern dielectric layer, the 3rd patterned conductive layer and second pattern dielectric layer.First patterned conductive layer is configured on the substrate, and has a plurality of electrodes.Patterning electric capacity layer is configured on part first patterned conductive layer.Second patterned conductive layer is configured on the patterning electric capacity layer.First pattern dielectric layer is configured on first patterned conductive layer, patterning electric capacity layer and second patterned conductive layer, exposes electrode, and has first patterned conductive layer and partly second patterned conductive layer of a plurality of openings to expose part.The 3rd patterned conductive layer is configured on first pattern dielectric layer, and the opening of filling part is to connect second patterned conductive layer.Second pattern dielectric layer is configured on first pattern dielectric layer and the 3rd patterned conductive layer, and exposes electrode, and electrode electricity is connected to support plate.
The present invention proposes a kind of manufacturing approach of integrated passive component, and it comprises provides a substrate, forms one first conductive layer on substrate; Form a capacitor layers again on this first conductive layer; Form one second conductive layer again on capacitor layers, then form one first patterning photoresist layer on second conductive layer, and be light shield with the first patterning photoresist layer; Patterning second conductive layer is to form one second patterned conductive layer.Then; With second patterned conductive layer is light shield, and patterning electric capacity layer is to form a patterning electric capacity layer; Remove the first patterning photoresist layer again, and form one second patterning photoresist layer on first conductive layer and the overlay pattern capacitor layers and second patterned conductive layer.Then, be light shield with the second patterning photoresist layer, patterning first conductive layer, to form one first patterned conductive layer, wherein first patterned conductive layer has a plurality of electrodes.Remove the second patterning photoresist layer; Form one first pattern dielectric layer again on first patterned conductive layer, patterning electric capacity layer and second patterned conductive layer, and first pattern dielectric layer have a plurality of openings to expose second patterned conductive layer of electrode and part.Afterwards; Form a Seed Layer on first pattern dielectric layer; And cover exposed portions first patterned conductive layer and second patterned conductive layer, and form one the 3rd patterning photoresist layer, the Seed Layer of cover part and filling expose the opening of electrode.Then; Form one the 3rd patterned conductive layer; Cover the part Seed Layer that is not covered, and fill not the part opening of being filled, remove the 3rd patterning photoresist layer again to connect second patterned conductive layer by the 3rd patterning photoresist layer by the 3rd patterning photoresist layer.At last, form one second pattern dielectric layer on first pattern dielectric layer and the 3rd patterned conductive layer, and expose electrode.
Based on above-mentioned, the present invention can produce slim integrated passive component and semiconductor package, to meet the thinning demand of electronic product.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing to elaborate as follows.
Description of drawings
Figure 1A to Fig. 1 P is the generalized section of making flow process of a kind of integrated passive component of one embodiment of the invention;
Fig. 2 A is the partial cutaway schematic that second pattern dielectric layer covers an embodiment of first pattern dielectric layer;
Fig. 2 B is the partial cutaway schematic that second pattern dielectric layer covers another embodiment of first pattern dielectric layer;
Fig. 3 is the substrate vertical view of one embodiment of the invention;
Fig. 4 A to Fig. 4 C is that the making flow process of patterning reference lamina of Fig. 3 is along the generalized section of A-A line;
Fig. 5 is the substrate vertical view of another embodiment of the present invention;
Fig. 6 is the generalized section of a kind of integrated passive component of one embodiment of the invention;
Fig. 7 is the generalized section of a kind of semiconductor package of one embodiment of the invention.
The main element symbol description
100,100a: integrated passive component
110: substrate
112: the back side
114: resistive layer
116: patterning resistance layer
120: the first conductive layers
122: the first patterned conductive layers
124: electrode
126: conductive pole
128: backplate
130: capacitor layers
132: patterning electric capacity layer
132a: capacitance part
132b: sign portion
140: the second conductive layers
142: the second patterned conductive layers
145: the three patterned conductive layers
145a: inductive patterns
150: the first patterning photoresist layers
152: the four patterning photoresist layers
160: the second patterning photoresist layers
170: the first pattern dielectric layer
172: opening
175: the second pattern dielectric layer
180: Seed Layer
190: the three patterning photoresist layers
200: semiconductor package
210: support plate
220: active element
230: bonding wire
240: sealing
Embodiment
Figure 1A to Fig. 1 G is the generalized section of manufacture method of a kind of integrated passive component of one embodiment of the invention.Please refer to Figure 1A, at first, a substrate 110 is provided.In the present embodiment, substrate 110 is a transparent material, glass for example, but the present invention is not limited thereto.Then, a resistive layer 114 is formed on the substrate 110.In the present embodiment, the material of resistive layer 114 can be tantalum nitride (TaN).Then, first conductive layer 120 is formed on the resistive layer 114.In the present embodiment, can first conductive layer 120 be formed on the resistive layer 114 sputtering method, and the material of first conductive layer 120 for example is an aluminium copper.Then, a capacitor layers 130 is formed on first conductive layer 120.In the present embodiment, can electric capacity once be formed on first conductive layer 120 galvanoplastic, and the material of capacitor layers 130 can be the dielectric material of high-dielectric coefficient, for example tantalum pentoxide (Ta
2O
5).
Like Figure 1B, one second conductive layer 140 is formed on the capacitor layers 130.In the present embodiment, can second conductive layer 140 be formed on the capacitor layers 130 sputter (sputtering), and the material of second conductive layer 140 for example is an aluminium copper.
Like Fig. 1 C, then, patterning second conductive layer 140 is to form second patterned conductive layer 142.In the present embodiment, the step of patterning comprises that formation one first patterning photoresist layer 150 on second conductive layer 140, is a light shield with the first patterning photoresist layer 150 again, etching second conductive layer 140.Etched mode can be dry-etching (dry etching).
Like Fig. 1 D, patterning electric capacity layer 130 is to form patterning electric capacity layer 132.In the present embodiment, the step of patterning comprises that with second patterned conductive layer 142 be light shield, etching capacitor layers 130.
Like Fig. 1 E and 1F, remove the first patterning photoresist layer 150.Afterwards, on first conductive layer 120, form one second patterning photoresist layer 160.The second patterning photoresist layer, 160 overlay pattern capacitor layers 132, second patterned conductive layer 142 and part first conductive layer 120.
Like Fig. 1 G and 1H, patterning first conductive layer 120 is to form first patterned conductive layer 122.In the present embodiment, the step of patterning comprises that with the second patterning photoresist layer 160 be light shield, etching first conductive layer 120.Then, patterning resistance layer 114 is to form patterning resistance layer 116.In the present embodiment, the step of patterning comprises that with first patterned conductive layer 122 be light shield, etching resistive layer 114.Then, remove the second patterning photoresist layer 160, to expose electrode 124 by part first patterned conductive layer 122 a plurality of external connections that defined.
Like Fig. 1 I and 1J, form one the 4th patterning photoresist layer 152, its overlay pattern capacitor layers 132, second patterned conductive layer 142, patterning resistance layer 116 and part first patterned conductive layer 122.Then, be light shield with the 4th patterning photoresist layer 152, remove part first patterned conductive layer 122 that is not covered with etching mode, to expose partially patterned resistive layer 116 by the 4th patterning photoresist layer 152.Then, remove the 4th patterning photoresist layer 152.So, form the electric resistance structure of the integrated passive component 100 of present embodiment.
Like Fig. 1 L and 1M, form one first pattern dielectric layer 170 on first patterned conductive layer 122, patterning resistance layer 116, patterning electric capacity layer 132 and second patterned conductive layer 142.First pattern dielectric layer 170 has a plurality of openings 172 to expose second patterned conductive layer 142 of electrode 124 and part.Afterwards, on first pattern dielectric layer 170, form a Seed Layer 180, wherein Seed Layer 180 also covers opening 172 and first patterned conductive layer 122 that exposed by first pattern dielectric layer 170 and the surface of second patterned conductive layer 142.In the present embodiment, Seed Layer 180 can form through sputter.
Like Fig. 1 N and 1O, form one the 3rd patterning photoresist layer 190, the opening 172 of the Seed Layer 180 of its cover part and filling exposed electrode 124.Then; Form one the 3rd patterned conductive layer 145; Cover the Seed Layer 180 that is not covered, and fill not the part opening 172 of being filled to connect second patterned conductive layer 142 by the 3rd patterning photoresist layer 190 by the 3rd patterning photoresist layer 190.In the present embodiment, the material of the 3rd patterned conductive layer 145 can be copper, and the 3rd patterned conductive layer 145 also can comprise an inductive patterns 145a, with the induction structure of the integrated passive component 100 that forms present embodiment.In the present embodiment, inductive patterns 145a can be spirality.
At last,, remove the 3rd patterning photoresist layer 190, exposing electrode 124, and form second pattern dielectric layer 175 on first pattern dielectric layer 170 and cover the 3rd patterned conductive layer 145 with reference to figure 1P, and exposed electrode 124.So, promptly accomplish the making of the integrated passive component 100 of present embodiment.
Integrated passive component 100 that it should be noted that present embodiment can comprise capacitance structure, electric resistance structure and induction structure.In the embodiment that other do not illustrate of the present invention, integrated passive component also can be only has capacitance structure, or has electric resistance structure or induction structure is wherein arbitrary and the integrated passive component of capacitance structure.If integrated passive component does not comprise induction structure, the 3rd patterned conductive layer 145 of Fig. 1 P does not just comprise inductive patterns 145a.If integrated passive component does not comprise resistance, then in above-mentioned manufacture craft, need not to form resistive layer shown in Figure 1 114, get final product on substrate 110 but directly form first conductive layer 120.Therefore, also can omit resistive layer 114 patternings to form the step of patterning resistance layer 116.And, also can omit the step shown in Fig. 1 I and Fig. 1 J in order to exposure pattern resistive layer 116.
Fig. 2 A is the partial cutaway schematic that second pattern dielectric layer covers an embodiment of first pattern dielectric layer.Please refer to Fig. 2 A; In the present embodiment; Second pattern dielectric layer 175 covers the 3rd patterned conductive layer 145 and part first pattern dielectric layer 170, and is covered in one side at least of each electrode 124 by first pattern dielectric layer 170 that second pattern dielectric layer, 175 parts cover.
Fig. 2 B is the partial cutaway schematic that second pattern dielectric layer covers another embodiment of first pattern dielectric layer.In the present embodiment, second pattern dielectric layer 175 covers the 3rd patterned conductive layer 145, first pattern dielectric layer 170 and partial electrode 124.Meaning promptly; Second pattern dielectric layer 175 not only covers the 3rd patterned conductive layer 145; Cover first pattern dielectric layer 170 more fully; And first pattern dielectric layer 170 and second pattern dielectric layer, 175 common one side at least that cover each electrode 124, so that electrode 124 more firmly is fixed on the substrate 110.
When using clear glass, cause the manufacture craft personnel to differentiate the difficulty of the working face of transparency carrier 110 easily as the material of substrate 110.Fig. 3 is the substrate vertical view of one embodiment of the invention.Please refer to Fig. 3; In order to solve the above-mentioned problem that can't differentiate the working face of substrate 110, in another embodiment of the present invention, patterning electric capacity layer 132 can comprise a capacitance part 132a and a 132b of sign portion; Wherein the 132b of sign portion is around capacitance part 132a, in order to the working region of marker substrate 110.
Fig. 4 A to Fig. 4 C is that the making flow process of patterning reference lamina of Fig. 3 is along the generalized section of A-A line.Please be simultaneously with reference to figure 4A to 4C, in the present embodiment, the patterning electric capacity layer 132 behind the patterning has a capacitance part 132a and a 132b of sign portion, and wherein the 132b of sign portion is around capacitance part 132a.In aforementioned step with first conductive layer, 120 patternings; Can second patterned conductive layer 142 that cover on the 132b of sign portion be removed in the lump; To expose the 132b of sign portion, the 132b of sign portion that therefore exposes forms an icon indicia layer around capacitance part 132a.Owing to the 132b of sign portion is come by capacitor layers 132 patternings, so its material also is a tantalum oxide.Because tantalum oxide is a colored materials, so the 132b of sign portion around capacitance part 132a has the effect that on substrate 110, indicates working face.Fig. 5 is the substrate vertical view of another embodiment of the present invention.Please refer to Fig. 5, in another embodiment of the present invention, the 132b of its sign portion also can be around substrate 110, with the working face of marker substrate.The manufacture craft of the 132b of sign portion is identical with above-mentioned manufacture craft.
Fig. 6 is the generalized section of a kind of integrated passive component of one embodiment of the invention.Please refer to Fig. 6, in the present embodiment, integrated passive component 100a more can comprise a plurality of conductive poles 126 and a plurality of backplate 128.Conductive pole 126 is arranged in substrate 110, and connects first patterned conductive layer 122.Backplate 128 is disposed at a back side 112 of substrate 110, and connects conductive pole 126 respectively.So, first patterned conductive layer 122 of integrated passive component 100a just can the conducting via conductive pole 126 with backplate 128.
Fig. 7 is the generalized section of a kind of semiconductor package of one embodiment of the invention.Please refer to Fig. 7, of the present invention a kind of semiconductor package 200 is provided in addition, it comprises a support plate 210, an active element 220, many bonding wires 230, a sealing 240 and integrated passive components 100.Active element 220 and integrated passive component 100 all are installed on the support plate 210, and the electrode electricity of integrated passive component 100 is connected to support plate 210.In the present embodiment, integrated passive component 100 is via bonding wire 230 its electrode 124 to be connected to support plate 210 and active element 220, and coats active element 220, integrated passive component 100 and bonding wire 230 with sealing 240.
In sum, the present invention can produce slim integrated passive component and semiconductor package, to meet the thinning demand of electronic product.In addition, the present invention forming sign portion, and shows the working face of substrate through the sign standard laid down by the ministries or commissions of the Central Government through coloured capacitor layers, the problem that is difficult to identification with the working face that solves transparency carrier.
Though disclosed the present invention in conjunction with above embodiment; Yet it is not in order to limit the present invention; Be familiar with this operator in the technical field under any; Do not breaking away from the spirit and scope of the present invention, can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (13)
1. integrated passive component comprises:
Substrate;
First patterned conductive layer is configured on this substrate, and has a plurality of electrodes;
Patterning electric capacity layer is configured on this first patterned conductive layer of part;
Second patterned conductive layer is configured on this patterning electric capacity layer;
First pattern dielectric layer; Be configured on this first patterned conductive layer, this patterning electric capacity layer and this second patterned conductive layer; Expose those electrodes, and have a plurality of openings this first patterned conductive layer and this second patterned conductive layer partly to expose part;
The 3rd patterned conductive layer is configured on this first pattern dielectric layer, and those openings of filling part are to connect this second patterned conductive layer; And
Second pattern dielectric layer is configured on this first pattern dielectric layer and the 3rd patterned conductive layer, and exposes those electrodes.
2. integrated passive component as claimed in claim 1, wherein the 3rd patterned conductive layer has an inductive patterns.
3. integrated passive component as claimed in claim 1 also comprises:
Patterning resistance layer is configured between this substrate and this first patterned conductive layer, this patterning resistance layer of this first patterned conductive layer expose portion, and this first pattern dielectric layer covers this patterning resistance layer of exposed portions.
4. integrated passive component as claimed in claim 1 also comprises:
The patterning mark layer is configured on the substrate and around this patterning electric capacity layer.
5. integrated passive component as claimed in claim 4, wherein this patterning mark layer is configured on this first patterned conductive layer of part, and the material of this patterning mark layer is identical with the material of this capacitor layers.
6. integrated passive component as claimed in claim 1, wherein this second pattern dielectric layer covers the 3rd patterned conductive layer and this first pattern dielectric layer of part.
7. integrated passive component as claimed in claim 1, wherein this second pattern dielectric layer covers respectively this electrode of the 3rd patterned conductive layer, this first pattern dielectric layer and part.
8. the manufacturing approach of an integrated passive component comprises:
One substrate is provided;
Form one first conductive layer on this substrate;
Form a capacitor layers on this first conductive layer;
Form one second conductive layer on this capacitor layers;
This second conductive layer of patterning is to form one second patterned conductive layer;
This capacitor layers of patterning is to form a patterning electric capacity layer;
This first conductive layer of patterning, to form one first patterned conductive layer, wherein this first patterned conductive layer has a plurality of electrodes;
Form one first pattern dielectric layer on this first patterned conductive layer, this patterning electric capacity layer and this second patterned conductive layer, and this first pattern dielectric layer have a plurality of openings to expose second patterned conductive layer of those electrodes and part;
Form a Seed Layer on this first pattern dielectric layer, and cover this first patterned conductive layer of exposed portions and this second patterned conductive layer;
Form one the 3rd patterned conductive layer, this Seed Layer of cover part, and those openings of filling part are to connect this second patterned conductive layer;
Form one second pattern dielectric layer on this first pattern dielectric layer and the 3rd patterned conductive layer, and expose those electrodes.
9. the manufacturing approach of integrated passive component as claimed in claim 8, wherein the 3rd patterned conductive layer also can comprise an inductive patterns.
10. the manufacturing approach of integrated passive component as claimed in claim 8 also comprises:
Form a resistive layer between this substrate and this first conductive layer;
After being this first conductive layer of mask patternization with this second patterning photoresist layer, this resistive layer of patterning again is to form a patterning resistance layer;
After removing this second patterning photoresist layer, form one the 4th patterning photoresist layer, cover this patterning electric capacity layer, this second patterned conductive layer, this patterning resistance layer and this first patterned conductive layer of part;
With the 4th patterning photoresist layer is light shield, removes this first patterned conductive layer of exposed portions to expose this patterning resistance layer; And
Remove the 4th patterning photoresist layer.
11. the manufacturing approach of integrated passive component as claimed in claim 8; Wherein in the step of this capacitor layers of patterning; This patterning electric capacity layer has a capacitance part and a sign portion; This sign portion centers on this capacitance part, and in the step of this first conductive layer of patterning, removes this second patterned conductive layer of part in this sign portion.
12. the manufacturing approach of integrated passive component as claimed in claim 8, wherein this second pattern dielectric layer covers on the 3rd patterned conductive layer and this first pattern dielectric layer of part.
13. the manufacturing approach of integrated passive component as claimed in claim 8, wherein this second pattern dielectric layer covers the 3rd patterned conductive layer, and this first pattern dielectric layer and part be this electrode respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110344674XA CN102412250A (en) | 2011-11-04 | 2011-11-04 | Semiconductor packaging structure, integrated passive element and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110344674XA CN102412250A (en) | 2011-11-04 | 2011-11-04 | Semiconductor packaging structure, integrated passive element and fabrication method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102412250A true CN102412250A (en) | 2012-04-11 |
Family
ID=45914244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110344674XA Pending CN102412250A (en) | 2011-11-04 | 2011-11-04 | Semiconductor packaging structure, integrated passive element and fabrication method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102412250A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400741A (en) * | 2019-07-25 | 2019-11-01 | 上海航天电子通讯设备研究所 | A kind of preparation method of the passive Resistor-Capacitor Unit of LCP flexible base board |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437232A (en) * | 2002-02-05 | 2003-08-20 | 亚太优势微系统股份有限公司 | Chip package structure and its making process |
| TW200423193A (en) * | 2003-04-23 | 2004-11-01 | Kuender & Co Ltd | Integrated passive device manufacturing method using MEMS technology |
| US20040238941A1 (en) * | 2001-07-12 | 2004-12-02 | Toshiya Satoh | Semiconductor connection substrate |
| CN1988083A (en) * | 2005-12-20 | 2007-06-27 | 富士通株式会社 | Thin-film capacitor and method for fabricating the same, electronic device and circuit board |
| CN101335267A (en) * | 2007-06-27 | 2008-12-31 | 财团法人工业技术研究院 | Image sensing module having crystal three-dimensional stacking construction |
| CN101378049A (en) * | 2007-08-29 | 2009-03-04 | 佳邦科技股份有限公司 | Inner-burying type multifunctional integration type structure and preparation method thereof |
| JP4280979B2 (en) * | 2003-06-13 | 2009-06-17 | ソニー株式会社 | Semiconductor device, mounting structure thereof, and manufacturing method thereof |
| CN101834178A (en) * | 2009-03-12 | 2010-09-15 | 日月光半导体制造股份有限公司 | Integration-type passive element and manufacturing method thereof |
| CN101946304A (en) * | 2008-02-20 | 2011-01-12 | Nxp股份有限公司 | Ultra high density capacity comprising pillar-shaped capacitors formed on both sides of a substrate |
| CN101996990A (en) * | 2009-08-21 | 2011-03-30 | Tdk株式会社 | Electronic component and manufacturing method thereof |
-
2011
- 2011-11-04 CN CN201110344674XA patent/CN102412250A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040238941A1 (en) * | 2001-07-12 | 2004-12-02 | Toshiya Satoh | Semiconductor connection substrate |
| CN1437232A (en) * | 2002-02-05 | 2003-08-20 | 亚太优势微系统股份有限公司 | Chip package structure and its making process |
| TW200423193A (en) * | 2003-04-23 | 2004-11-01 | Kuender & Co Ltd | Integrated passive device manufacturing method using MEMS technology |
| JP4280979B2 (en) * | 2003-06-13 | 2009-06-17 | ソニー株式会社 | Semiconductor device, mounting structure thereof, and manufacturing method thereof |
| CN1988083A (en) * | 2005-12-20 | 2007-06-27 | 富士通株式会社 | Thin-film capacitor and method for fabricating the same, electronic device and circuit board |
| CN101335267A (en) * | 2007-06-27 | 2008-12-31 | 财团法人工业技术研究院 | Image sensing module having crystal three-dimensional stacking construction |
| CN101378049A (en) * | 2007-08-29 | 2009-03-04 | 佳邦科技股份有限公司 | Inner-burying type multifunctional integration type structure and preparation method thereof |
| CN101946304A (en) * | 2008-02-20 | 2011-01-12 | Nxp股份有限公司 | Ultra high density capacity comprising pillar-shaped capacitors formed on both sides of a substrate |
| CN101834178A (en) * | 2009-03-12 | 2010-09-15 | 日月光半导体制造股份有限公司 | Integration-type passive element and manufacturing method thereof |
| CN101996990A (en) * | 2009-08-21 | 2011-03-30 | Tdk株式会社 | Electronic component and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400741A (en) * | 2019-07-25 | 2019-11-01 | 上海航天电子通讯设备研究所 | A kind of preparation method of the passive Resistor-Capacitor Unit of LCP flexible base board |
| CN110400741B (en) * | 2019-07-25 | 2022-05-27 | 上海航天电子通讯设备研究所 | Preparation method of LCP flexible substrate passive resistance-capacitance element |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107203296B (en) | Display panel, manufacturing method thereof and display device | |
| CN105159515B (en) | Touch-control structure and preparation method thereof, touch base plate and display device | |
| CN105242467B (en) | Display device and its manufacturing method | |
| CN109742121A (en) | A kind of flexible base board and preparation method thereof, display device | |
| CN209087845U (en) | A kind of flexible base board and display device | |
| CN106909258B (en) | Structure of touch screen functional sheet lead wire and manufacturing method thereof | |
| CN103441128B (en) | A kind of tft array substrate and manufacture method thereof | |
| CN101699378B (en) | Touch panel and manufacturing method thereof | |
| JP2023145618A (en) | Through electrode substrate, semiconductor device, and method of manufacturing through electrode substrate | |
| CN105679967A (en) | Mask plate and method for preparing organic light-emitting display device | |
| CN106610754A (en) | Touch panel and manufacturing method thereof | |
| CN102385461A (en) | Projecting capacitor type touch panel and manufacture method thereof | |
| CN109614008B (en) | Double-sided patterning method and manufacturing method of touch panel | |
| CN102623424B (en) | Chip package and method for forming the same | |
| CN102136430B (en) | Semiconductor encapsulating structure and manufacturing method thereof | |
| CN102593085A (en) | Chip packaging structure and chip packaging manufacturing process | |
| CN104216562B (en) | Contact panel and its manufacture method and display device | |
| CN102412250A (en) | Semiconductor packaging structure, integrated passive element and fabrication method thereof | |
| CN109742118B (en) | Display panel, array substrate and preparation method thereof | |
| CN104812226A (en) | Cover plate structure and manufacturing method thereof | |
| CN102290330A (en) | Forming method of capacitor structure | |
| CN103681586B (en) | Coreless capsulation substrates and method for making thereof | |
| CN106364197B (en) | panel and preparation method thereof | |
| KR100908225B1 (en) | Resistive membrane type touch panel | |
| CN106056032B (en) | Composite substrate sensing device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120411 |