JP2005005346A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the high-frequency characteristics of a semiconductor integrated circuit device from being deteriorated due to the coupling capacity produced between a level shift circuit provided in the circuit device and another peripheral circuit due to the resistance loss compensating capacitor of a level shift diode provided in the level shift circuit. <P>SOLUTION: The semiconductor integrated circuit device comprises level shift diodes D1 and D2 etc., formed on a substrate S<SB>1</SB>and the resistance loss compensating capacitor C<SB>s</SB>formed in an upper layer facing at least parts of the level shift diodes D1 and D2, etc. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device suitable for constituting an ultrahigh frequency electronic device used for optical communication or wireless communication.
[0001]
[Prior art]
For example, in a source follower circuit, a level shift circuit composed of a diode is used to match the DC bias level with the next stage.
[0002]
FIG. 3 is a main part explanatory view showing a semiconductor integrated circuit device and an equalization circuit for explaining the level shift circuit, (A) is a cutaway side view of the main part of the semiconductor integrated circuit device, and (B) is an equalization. Each circuit diagram is shown.
[0003]
In FIG, _S substrate ₁ is made of InP, GND is a ground power supply line, VSS is the substrate - source supply lines, a source-follower connected FET Q1, Q2 constitute a constant current source FET, D1, D2 shows the level shifting diodes, C _s is the resistance loss compensation capacitor, C _f is the binding capacity, respectively. The number of level shift diodes is not limited to two.
[0004]
In the illustrated level shift circuit, the level shift diodes D1 and D2 include a series resistance component, which causes signal loss at high frequencies.
[0005]
In order to solve the above problem, as shown in FIG. 3, a resistance loss compensating capacitor C _s is connected in parallel with the level shift diodes D1 and D2, and the resistance loss at high frequency is canceled to improve the high frequency characteristics. Means for improving are known (for example, see Non-Patent Document 1).
[0006]
However, since the capacitor C _s used in the semiconductor integrated circuit device shown in FIG. 3 needs to be considerably large in size, the coupling capacitance C between the electrode of the capacitor C _s and the peripheral circuit, for example, the ground power supply line GND. _f is generated, it is not a factor that degrades the high frequency characteristics, moreover, there is also the effect of the problems existing capacitors C _s resulting in expanded layout area.
[0007]
FIG. 4 is a cutaway side view showing a main part of the semiconductor integrated circuit device for explaining that the junction capacitance _Cf is generated. The same reference numerals as those used in FIG. It shall have meaning.
[0008]
As is apparent from the figure, the coupling capacitance is generated because the electric field from the lower electrode E _c1 of the capacitor C _s affects other peripheral circuits in the integrated circuit device, for example, the ground power supply line GND. .
[0009]
[Non-Patent Document 1]
Y. Nakasha, et. al “A43-Gb / s Full-Rate-Clock 4: 1 Multiplexer in InP-Based HEMT Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 37 pp 1703-1709 DEC. 2002
[0010]
[Problems to be solved by the invention]
The present invention provides a semiconductor integrated circuit in which a coupling capacitance generated between another peripheral circuit due to a resistance loss compensation capacitor of a level shift diode provided in a level shift circuit in a semiconductor integrated circuit device is provided. Do not degrade the high-frequency characteristics of the device.
[0011]
[Means for Solving the Problems]
In the semiconductor integrated circuit device according to the present invention, a level shift diode (for example, level shift diodes D1 and D2) formed on a substrate (for example, substrate S ₁ ) and the level shift diode are provided. It comprises a resistance loss compensation capacitor (for example, a resistance loss compensation capacitor C _s ) formed in an upper layer facing at least a part.
[0012]
By adopting the above means, the coupling capacitance generated due to the resistance loss compensating capacitor provided in the level shift circuit is generated between the lower electrode of the capacitor and the level shift diode. From the viewpoint of the equalization circuit, the capacitor is connected in parallel with the resistor for compensating for the loss of resistance, and thus the function of the capacitor for compensating for the loss of resistance is promoted in the same way as increasing the capacity. become.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a main part explanatory view showing a semiconductor integrated circuit device and an equalizing circuit for explaining an embodiment of the present invention, (A) is a cutaway side view of the main part of the semiconductor integrated circuit device, and (B). Are respectively equivalent circuit diagrams, and the same symbols as those used in FIG. 3 represent the same parts or have the same meanings.
[0014]
As apparent from the figure, in the present invention, at least a part of the region level shifting diodes D1 and D2 are occupied, Aru preferably arranged capacitor C _s resistance loss compensation in the upper portion over most.
[0015]
By adopting this configuration, the coupling capacitance C _f is connected to the connection point between the lower electrode E _c1 of the capacitor C _s and any part of the level shift diodes D1 and D2, in the illustrated example, the level shift diodes D1 and D2. because it is produced during capacitive coupling of the capacitor C _s and other peripheral circuitry is relaxed, the deterioration of high frequency characteristics is prevented.
[0016]
In this case, in a potential change to the diode on the circuit operation because the same as in the potential change in the capacitor, the generation of coupling capacitance C _f between the diodes are none adversely affect the operation, since the level shifting diodes D1 and D2 and the capacitor C _s is formed in a state of being stacked, the layout area is reduced, and, also becomes shorter connection wiring length, the high frequency characteristic is further improved.
[0017]
FIG. 2 is a fragmentary cutaway side view showing a semiconductor integrated circuit device for explaining that capacitive coupling between a capacitor and other peripheral circuits is relaxed according to one embodiment of the present invention. The same symbols used in 1 shall represent the same parts or have the same meaning.
[0018]
As apparent from the figure, the capacitor C _s is positioned so as to cover the diodes D1 and D2, and _therefore the electric field from the lower electrode E _c1 of the capacitor C _s is shielded by the diodes D1 and D2. Capacitive coupling is alleviated because the ground power supply line GND is not affected or is little if any.
[0019]
【The invention's effect】
A semiconductor integrated circuit device according to the present invention includes a level shift diode formed on a substrate and a resistance loss compensating capacitor formed in an upper layer facing at least a part of the level shift diode. It is out.
[0020]
By adopting the above configuration, the coupling capacitance generated due to the resistance loss compensating capacitor provided in the level shift circuit is generated between the lower electrode of the capacitor and the level shift diode. From the viewpoint of the equalization circuit, the capacitor is connected in parallel with the resistor for compensating for the loss of resistance, and thus the function of the capacitor for compensating for the loss of resistance is promoted in the same way as increasing the capacity. become.
[0021]
Further, since the level shift diode group and the resistance loss compensation capacitor are formed in a stacked state, the layout area is reduced and the length of the connection wiring is shortened, so that the high frequency characteristics are further improved.
[Brief description of the drawings]
FIG. 1 is a main part explanatory view showing a semiconductor integrated circuit device and an equalizing circuit for explaining an embodiment of the present invention;
FIG. 2 is a fragmentary cutaway side view showing a semiconductor integrated circuit device for explaining that capacitive coupling between a capacitor and other peripheral circuits is relaxed according to an embodiment of the present invention;
FIG. 3 is a main part explanatory view showing a semiconductor integrated circuit device and an equalizing circuit for explaining a level shift circuit;
FIG. 4 is a cutaway side view showing a main part of a semiconductor integrated circuit device for explaining that a junction capacitance _Cf is generated;
[Explanation of symbols]
Substrate GND made of S ₁ InP Ground power supply line VSS Substrate-source power supply line Q1 Source-follower-connected FET
Q2 FET constituting a constant current source
D1, D2 level shifting diode _{C s} resistance loss compensation capacitor _{C f} binding capacity _{E c1} lower electrode capacitors _{C s}

Claims (1)

A semiconductor integrated circuit device comprising: a level shift diode formed on a substrate; and a resistance loss compensating capacitor formed in an upper layer facing at least a part of the level shift diode.

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