JP2005005346A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device Download PDFInfo
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- JP2005005346A JP2005005346A JP2003164655A JP2003164655A JP2005005346A JP 2005005346 A JP2005005346 A JP 2005005346A JP 2003164655 A JP2003164655 A JP 2003164655A JP 2003164655 A JP2003164655 A JP 2003164655A JP 2005005346 A JP2005005346 A JP 2005005346A
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- Prior art keywords
- level shift
- semiconductor integrated
- circuit device
- integrated circuit
- capacitor
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Abstract
Description
【発明の属する技術分野】
本発明は、光通信或いは無線通信などに用いる超高周波用電子機器を構成するのに好適な半導体集積回路装置に関する。
【0001】
【従来の技術】
例えば、ソース・フォロワ回路に於いて、次段とのDCバイアス・レベルを合わせる為、ダイオードで構成されたレベル・シフト回路が用いられる。
【0002】
図3はレベル・シフト回路を説明する為の半導体集積回路装置及び等化回路を表す要部説明図であり、(A)は半導体集積回路装置の要部切断側面図、(B)は等化回路図をそれぞれ示している。
【0003】
図に於いて、S1 はInPからなる基板、GNDは接地電源ライン、VSSは基板−ソース間電源ライン、Q1はソース・フォロワ接続されたFET、Q2は定電流源を構成するFET、D1,D2はレベル・シフト・ダイオード、Cs は抵抗損失補償用キャパシタ、Cf は結合容量をそれぞれ示している。尚、レベル・シフト・ダイオードは2個に限らない。
【0004】
図示のレベル・シフト回路に於いて、レベル・シフト・ダイオードD1、D2は直列抵抗成分が含まれていることから、高周波に於いては信号損失の原因になる。
【0005】
前記問題を解決する為、図3に見られるように、レベル・シフト・ダイオードD1、D2に並列に抵抗損失補償用キャパシタCs を接続し、高周波に於ける抵抗損失を相殺して高周波特性を向上する手段が知られている(例えば非特許文献1参照。)。
【0006】
ところが、図3に見られる半導体集積回路装置で用いるキャパシタCs は、サイズがかなり大きいものが必要である為、キャパシタCs の電極と周辺回路、例えば接地電源ラインGNDとの間に結合容量Cf が生成され、それが高周波特性を劣化させる要因になっていて、しかも、キャパシタCs の存在がレイアウト面積が拡げてしまう旨の問題もある。
【0007】
図4は接合容量Cf が生成されることを説明する為の半導体集積回路装置を表す要部切断側面図であり、図3に於いて用いた記号と同記号は同部分を表すか或いは同じ意味を持つものとする。
【0008】
図から明らかなように、結合容量が生成されるのは、キャパシタCs の下部電極Ec1からの電界が集積回路装置内の他の周辺回路例えば接地電源ラインGNDに影響を与えることに起因する。
【0009】
【非特許文献1】
Y.Nakasha,et.al“A43−Gb/s Full−Rate−Clock 4:1 Multiplexer in InP−Based HEMT Technology”IEEE JOURNAL OF SOLID−STATE CIRCUITS,Vol.37 pp1703−1709 DEC.2002
【0010】
【発明が解決しようとする課題】
本発明は、半導体集積回路装置内のレベル・シフト回路に設けられたレベル・シフト・ダイオードの抵抗損失補償用キャパシタに起因して他の周辺回路との間に生成される結合容量が半導体集積回路装置の高周波特性を劣化させないようにする。
【0011】
【課題を解決するための手段】
本発明に依る半導体集積回路装置に於いては、基板(例えば基板S1 )上に形成されたレベル・シフト・ダイオード(例えばレベル・シフト・ダイオードD1及びD2など)及び該レベル・シフト・ダイオードの少なくとも一部と対向する上層に形成された抵抗損失補償用キャパシタ(例えば抵抗損失補償用キャパシタCs )を含んでなることを特徴とする。
【0012】
前記手段を採ることに依り、レベル・シフト回路に設けた抵抗損失補償用キャパシタに起因して生成される結合容量は、当該キャパシタの下部電極とレベル・シフト・ダイオードとの間に生成されることになり、等化回路的に見ると、抵抗損失補償用キャパシタと並列的に接続された状態となるので、容量を増加させたことと同等となって抵抗損失補償用キャパシタの機能を助長することになる。
【0013】
【発明の実施の形態】
図1は本発明の一実施の形態を説明する為の半導体集積回路装置と等化回路を表す要部説明図であり、(A)は半導体集積回路装置の要部切断側面図、(B)は等化回路図をそれぞれ示し、図3に於いて用いた記号と同記号は同部分を表すか或いは同じ意味を持つものとする。
【0014】
図から明らかなように、本発明では、レベル・シフト・ダイオードD1及びD2が占有する領域の少なくとも一部、好ましくは大部分を覆う上層部に抵抗損失補償用キャパシタCs を配置してある。
【0015】
この構成を採ることで、結合容量Cf はキャパシタCs の下部電極Ec1とレベル・シフト・ダイオードD1及びD2の何れかの部分、図示例ではレベル・シフト・ダイオードD1及びD2の接続点との間に生成されているので、キャパシタCs と他の周辺回路との容量結合は緩和され、高周波特性の劣化は防止される。
【0016】
この場合、回路動作上でのダイオードに於ける電位変化はキャパシタに於ける電位変化と同じであるから、ダイオードとの間の結合容量Cf の生成は動作に悪影響を及ぼすことは皆無であり、そして、レベル・シフト・ダイオードD1及びD2とキャパシタCs とは積層された状態に形成されているので、レイアウト面積は低減され、且つ、接続配線長も短くなるので、高周波特性は更に向上する。
【0017】
図2は本発明の一実施の形態に依ってキャパシタと他の周辺回路との間の容量結合が緩和されることを説明する為の半導体集積回路装置を表す要部切断側面図であり、図1に於いて用いた記号と同記号は同部分を表すか或いは同じ意味を持つものとする。
【0018】
図から明らかなように、ダイオードD1及びD2を覆うようにキャパシタCs が位置している為、キャパシタCs の下部電極Ec1からの電界はダイオードD1及びD2で遮蔽された状態となって、接地電源ラインGNDに影響を与えることは無くなるか、或いは、あっても僅かとなるので、容量結合は緩和されるものである。
【0019】
【発明の効果】
本発明に依る半導体集積回路装置に於いては、基板上に形成されたレベル・シフト・ダイオード及び該レベル・シフト・ダイオードの少なくとも一部と対向する上層に形成された抵抗損失補償用キャパシタを含んでいる。
【0020】
前記構成を採ることに依り、レベル・シフト回路に設けた抵抗損失補償用キャパシタに起因して生成される結合容量は、当該キャパシタの下部電極とレベル・シフト・ダイオードとの間に生成されることになり、等化回路的に見ると、抵抗損失補償用キャパシタと並列的に接続された状態となるので、容量を増加させたことと同等となって抵抗損失補償用キャパシタの機能を助長することになる。
【0021】
また、レベル・シフト・ダイオード群と抵抗損失補償用キャパシタとは積層された状態に形成されているので、レイアウト面積は低減され、且つ、接続配線長も短くなるので高周波特性は更に向上する。
【図面の簡単な説明】
【図1】本発明の一実施の形態を説明する為の半導体集積回路装置と等化回路を表す要部説明図である。
【図2】本発明の一実施の形態に依ってキャパシタと他の周辺回路との間の容量結合が緩和されることを説明する為の半導体集積回路装置を表す要部切断側面図である。
【図3】レベル・シフト回路を説明する為の半導体集積回路装置及び等化回路を表す要部説明図である。
【図4】接合容量Cf が生成されることを説明する為の半導体集積回路装置を表す要部切断側面図である。
【符号の説明】
S1 InPからなる基板
GND 接地電源ライン
VSS 基板−ソース間電源ライン
Q1 ソース・フォロワ接続されたFET
Q2 定電流源を構成するFET
D1,D2 レベル・シフト・ダイオード
Cs 抵抗損失補償用キャパシタ
Cf 結合容量
Ec1 キャパシタCs の下部電極BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device suitable for constituting an ultrahigh frequency electronic device used for optical communication or wireless communication.
[0001]
[Prior art]
For example, in a source follower circuit, a level shift circuit composed of a diode is used to match the DC bias level with the next stage.
[0002]
FIG. 3 is a main part explanatory view showing a semiconductor integrated circuit device and an equalization circuit for explaining the level shift circuit, (A) is a cutaway side view of the main part of the semiconductor integrated circuit device, and (B) is an equalization. Each circuit diagram is shown.
[0003]
In FIG, S substrate 1 is made of InP, GND is a ground power supply line, VSS is the substrate - source supply lines, a source-follower connected FET Q1, Q2 constitute a constant current source FET, D1, D2 shows the level shifting diodes, C s is the resistance loss compensation capacitor, C f is the binding capacity, respectively. The number of level shift diodes is not limited to two.
[0004]
In the illustrated level shift circuit, the level shift diodes D1 and D2 include a series resistance component, which causes signal loss at high frequencies.
[0005]
In order to solve the above problem, as shown in FIG. 3, a resistance loss compensating capacitor C s is connected in parallel with the level shift diodes D1 and D2, and the resistance loss at high frequency is canceled to improve the high frequency characteristics. Means for improving are known (for example, see Non-Patent Document 1).
[0006]
However, since the capacitor C s used in the semiconductor integrated circuit device shown in FIG. 3 needs to be considerably large in size, the coupling capacitance C between the electrode of the capacitor C s and the peripheral circuit, for example, the ground power supply line GND. f is generated, it is not a factor that degrades the high frequency characteristics, moreover, there is also the effect of the problems existing capacitors C s resulting in expanded layout area.
[0007]
FIG. 4 is a cutaway side view showing a main part of the semiconductor integrated circuit device for explaining that the junction capacitance Cf is generated. The same reference numerals as those used in FIG. It shall have meaning.
[0008]
As is apparent from the figure, the coupling capacitance is generated because the electric field from the lower electrode E c1 of the capacitor C s affects other peripheral circuits in the integrated circuit device, for example, the ground power supply line GND. .
[0009]
[Non-Patent Document 1]
Y. Nakasha, et. al “A43-Gb / s Full-Rate-Clock 4: 1 Multiplexer in InP-Based HEMT Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 37 pp 1703-1709 DEC. 2002
[0010]
[Problems to be solved by the invention]
The present invention provides a semiconductor integrated circuit in which a coupling capacitance generated between another peripheral circuit due to a resistance loss compensation capacitor of a level shift diode provided in a level shift circuit in a semiconductor integrated circuit device is provided. Do not degrade the high-frequency characteristics of the device.
[0011]
[Means for Solving the Problems]
In the semiconductor integrated circuit device according to the present invention, a level shift diode (for example, level shift diodes D1 and D2) formed on a substrate (for example, substrate S 1 ) and the level shift diode are provided. It comprises a resistance loss compensation capacitor (for example, a resistance loss compensation capacitor C s ) formed in an upper layer facing at least a part.
[0012]
By adopting the above means, the coupling capacitance generated due to the resistance loss compensating capacitor provided in the level shift circuit is generated between the lower electrode of the capacitor and the level shift diode. From the viewpoint of the equalization circuit, the capacitor is connected in parallel with the resistor for compensating for the loss of resistance, and thus the function of the capacitor for compensating for the loss of resistance is promoted in the same way as increasing the capacity. become.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a main part explanatory view showing a semiconductor integrated circuit device and an equalizing circuit for explaining an embodiment of the present invention, (A) is a cutaway side view of the main part of the semiconductor integrated circuit device, and (B). Are respectively equivalent circuit diagrams, and the same symbols as those used in FIG. 3 represent the same parts or have the same meanings.
[0014]
As apparent from the figure, in the present invention, at least a part of the region level shifting diodes D1 and D2 are occupied, Aru preferably arranged capacitor C s resistance loss compensation in the upper portion over most.
[0015]
By adopting this configuration, the coupling capacitance C f is connected to the connection point between the lower electrode E c1 of the capacitor C s and any part of the level shift diodes D1 and D2, in the illustrated example, the level shift diodes D1 and D2. because it is produced during capacitive coupling of the capacitor C s and other peripheral circuitry is relaxed, the deterioration of high frequency characteristics is prevented.
[0016]
In this case, in a potential change to the diode on the circuit operation because the same as in the potential change in the capacitor, the generation of coupling capacitance C f between the diodes are none adversely affect the operation, since the level shifting diodes D1 and D2 and the capacitor C s is formed in a state of being stacked, the layout area is reduced, and, also becomes shorter connection wiring length, the high frequency characteristic is further improved.
[0017]
FIG. 2 is a fragmentary cutaway side view showing a semiconductor integrated circuit device for explaining that capacitive coupling between a capacitor and other peripheral circuits is relaxed according to one embodiment of the present invention. The same symbols used in 1 shall represent the same parts or have the same meaning.
[0018]
As apparent from the figure, the capacitor C s is positioned so as to cover the diodes D1 and D2, and therefore the electric field from the lower electrode E c1 of the capacitor C s is shielded by the diodes D1 and D2. Capacitive coupling is alleviated because the ground power supply line GND is not affected or is little if any.
[0019]
【The invention's effect】
A semiconductor integrated circuit device according to the present invention includes a level shift diode formed on a substrate and a resistance loss compensating capacitor formed in an upper layer facing at least a part of the level shift diode. It is out.
[0020]
By adopting the above configuration, the coupling capacitance generated due to the resistance loss compensating capacitor provided in the level shift circuit is generated between the lower electrode of the capacitor and the level shift diode. From the viewpoint of the equalization circuit, the capacitor is connected in parallel with the resistor for compensating for the loss of resistance, and thus the function of the capacitor for compensating for the loss of resistance is promoted in the same way as increasing the capacity. become.
[0021]
Further, since the level shift diode group and the resistance loss compensation capacitor are formed in a stacked state, the layout area is reduced and the length of the connection wiring is shortened, so that the high frequency characteristics are further improved.
[Brief description of the drawings]
FIG. 1 is a main part explanatory view showing a semiconductor integrated circuit device and an equalizing circuit for explaining an embodiment of the present invention;
FIG. 2 is a fragmentary cutaway side view showing a semiconductor integrated circuit device for explaining that capacitive coupling between a capacitor and other peripheral circuits is relaxed according to an embodiment of the present invention;
FIG. 3 is a main part explanatory view showing a semiconductor integrated circuit device and an equalizing circuit for explaining a level shift circuit;
FIG. 4 is a cutaway side view showing a main part of a semiconductor integrated circuit device for explaining that a junction capacitance Cf is generated;
[Explanation of symbols]
Substrate GND made of S 1 InP Ground power supply line VSS Substrate-source power supply line Q1 Source-follower-connected FET
Q2 FET constituting a constant current source
D1, D2 level shifting diode C s resistance loss compensation capacitor C f binding capacity E c1 lower electrode capacitors C s
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JP2003164655A JP2005005346A (en) | 2003-06-10 | 2003-06-10 | Semiconductor integrated circuit device |
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JP2003164655A JP2005005346A (en) | 2003-06-10 | 2003-06-10 | Semiconductor integrated circuit device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7800195B2 (en) | 2007-02-27 | 2010-09-21 | Denso Corporation | Semiconductor apparatus having temperature sensing diode |
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2003
- 2003-06-10 JP JP2003164655A patent/JP2005005346A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7800195B2 (en) | 2007-02-27 | 2010-09-21 | Denso Corporation | Semiconductor apparatus having temperature sensing diode |
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