JP2005340507A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device for suppressing electromagnetic radiation caused by oscillation, and for preventing the deterioration of the efficiency of charge feeding at the time of carrying out on-chip de-coupling. <P>SOLUTION: This semiconductor integrated circuit 10 is constituted of an inverter circuit 12 and a capacitor 14, and the inverter circuit 12 is a CMOS inverter constituted by connecting a pMOS 16 with an nMOS 18. The capacitor 14 is constituted so that a dielectric 38 can be interposed between a pair of electrodes constituted of electrodes 36A and 36B. The electrode 36A is connected to a p diffusion region 24A and n diffusion region 44 of a pMOS 16 and a VDD terminal 46 for a power source input. The electrode 36B is connected to an n diffusion region 30B, p diffusion region 48 of the nMOS 18, and a VSS terminal 50 for the ground. The electrodes 36A and 36B are formed of materials with losses larger than that of metal or polysilicon to be used as materials of normal electrodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device used in electronic equipment such as a personal computer, a copying machine, a printer, and a facsimile.

  The digital signal processed on the semiconductor integrated circuit used in the electronic apparatus as described above includes harmonic components of the fifth to tenth order with respect to the clock frequency and all of its subharmonics.

  Normally, switching operation is performed in synchronization with a clock signal for each functional unit such as many flip-flops included in a semiconductor integrated circuit, so that a switching current flows from the power supply on the printed wiring board to the semiconductor integrated circuit according to the clock frequency. Moreover, it flows from the semiconductor integrated circuit to the ground of the printed wiring board. Furthermore, when the semiconductor integrated circuit drives the load element with a signal synchronized with the clock through the signal wiring on the printed wiring board, the signal current flows from the power supply on the printed wiring board to the signal wiring through the semiconductor integrated circuit, and further the signal It flows from the wiring to the ground of the printed wiring board through the semiconductor integrated circuit. Since the current of these power supply systems propagates through a path having a finite inductance, such as a wiring on the package of the semiconductor element and a wiring for connecting to the wiring on the printed wiring board, the current i changes over time to di / dt. On the other hand, a potential difference V (= L × di / dt) is generated. This causes a so-called ground bounce of the reference potential of the semiconductor element on the package with respect to the reference potential of the printed wiring board.

  This ground bounce within the package propagates on the printed circuit board through all I / O pins whether or not the circuit is operating, and sometimes causes significant EMI (unwanted electromagnetic radiation) problems.

  In order to suppress the ground bounce inside the package, it is effective to reduce the impedance of the power supply pins, ground pins, and wiring and perform sufficient decoupling outside the chip. Due to the enormous package size, it is difficult to secure a sufficient number of pins for the power supply system, and there is a limit to reducing the impedance.

  Therefore, as described in Patent Document 1, a so-called on-chip decoupling method has been proposed in which power supply stabilization is performed by arranging a power supply capacitor in a portion where no LSI functional circuit exists. That is, a capacitor is formed in a portion of the semiconductor layer that is not used by the functional circuit.

  However, as described in Non-Patent Document 1, as a result of experimentally verifying the effect of on-chip decoupling, electromagnetic radiation caused by switching has a clear effect on both the through current and the output buffer current. However, it has been found that there are frequencies at which electromagnetic radiation increases.

According to the analysis by the present inventors, the cause of this increase in electromagnetic radiation is that resonance occurs in a loop with the stray capacitance of the transistor to be switched by connecting a large-capacitance capacitor with low impedance. It turns out that there is.
Japanese Patent No. 3217098 Toshio Sudo, Takeshi Nakano, “Study on LSI Power Supply Characteristics and Behavior of Simultaneous Switching Noise and Radiation Noise”, IEICE Technical Report CPM 2003-187, The Institute of Electronics, Information and Communication Engineers, February 2004, p63-68

  As described above, when on-chip decoupling (especially when an empty cell of a semiconductor element is used or when a capacitor cell is formed in a semiconductor element) is performed, resonance occurs in a loop with the stray capacitance of the transistor to be switched. However, if the capacity of the decoupling capacitor is reduced in order to prevent this, the efficient charge supply corresponding to the high-speed switching that is the original purpose is impaired.

  In order to solve this, it is conceivable to limit the high-frequency current by adding inductance.

  However, the addition of inductance only shifts the resonance point to the low frequency side, and in particular, the clock harmonics are of low order close to the fundamental wave and have a large energy, rather than being a fundamental solution rather than a problem. May be exacerbated. Further, adding a separate resistance element in series adds an inductance corresponding to an increase in the path in the current direction, and at the same time inhibits high-frequency charge supply. In other words, a structure that does not reduce the efficiency of charge supply while avoiding the influence of the resonance is required.

  The present invention has been made to solve the above-described problem. In the case of performing on-chip decoupling, the semiconductor integrated circuit can suppress electromagnetic radiation due to resonance and prevent a decrease in charge supply efficiency. An object is to provide a circuit device.

  In order to achieve the above object, an invention according to claim 1 is directed to an electrode pair and a dielectric sandwiched between the electrode pair between a power supply input portion and a reference potential input portion of a functional circuit included in a semiconductor integrated circuit. The capacitor is formed in the semiconductor integrated circuit, and at least one of the electrode pair and the dielectric has a predetermined loss.

  According to the present invention, in the semiconductor integrated circuit device, the capacitor is formed between the power supply input portion and the reference potential input portion of the functional circuit included in the semiconductor integrated circuit. The functional circuit is operated by the power supplied from the power input unit and has a predetermined function.

  The capacitor includes an electrode pair and a dielectric sandwiched between the electrode pair, and is formed in a semiconductor integrated circuit, that is, in a semiconductor chip. That is, the capacitor is formed in the semiconductor integrated circuit integrally with the functional circuit by using, for example, an empty cell in the semiconductor integrated circuit or by forming a capacitor cell in a region where the functional circuit is not formed. Further, at least one of the electrode pair and the dielectric has a predetermined loss.

  Specifically, as described in claim 2, the electrode pair can be configured to have a resistance at least greater than that of metal and polysilicon.

  In general, polysilicon having a loss larger than that of metal is used for electrodes in a semiconductor integrated circuit, but it is insufficient to avoid the influence of resonance phenomenon, and a larger resistor must be used. Even if a resistance element is added between the capacitor electrode part and the switching part of the semiconductor integrated circuit, it is preferable that the resonance point only moves to the low frequency side where the harmonic energy of the switching frequency is large due to the addition of inductance. Absent.

  On the other hand, a capacitor for on-chip decoupling is provided between the power supply input portion and the reference potential input portion of the functional circuit, and the metal and polysilicon normally used as electrodes as in the invention according to claim 2 Reducing the resonance between stray capacitance and inductance in the switching element caused by the capacitor part having a low impedance at high frequencies by forming the electrode pair with a material having a large resistance and giving the electrode pair a loss. can do.

  In addition, when a capacitor inserted in series with respect to the resonance loop due to stray capacitance and inductance of the switching element portion has conductance G, the Q value indicating the sharpness of resonance is in inverse proportion to the conductance component G, and Increasing the value of G is effective to suppress the influence. For this purpose, it can be said that it is appropriate to use a material having a high high-frequency conductance so as to give a loss to a high-frequency resonance current flowing through the high-dielectric constant while ensuring a sufficient charge supply.

  Therefore, as described in claim 3, the dielectric may have a configuration having a dielectric loss larger than at least silicon oxide.

  Thus, by configuring the dielectric with a dielectric material having a dielectric loss larger than that of generally used silicon oxide, it is possible to suppress the resonance by giving a loss to the high-frequency resonance current and sufficiently Charge supply can be ensured.

  According to a fourth aspect of the present invention, one electrode of the electrode pair may be a diffusion region in which a semiconductor substrate constituting the semiconductor integrated circuit is doped with a carrier.

  According to the present invention, the diffusion region diffused by doping the carrier in the semiconductor substrate or well constituting the semiconductor integrated circuit is used as the electrode. Therefore, the resistance value of the diffusion region can be easily controlled by controlling the doping amount of the carrier. Can be controlled. Therefore, it is possible to easily configure an electrode having an optimum resistance value corresponding to the strength of resonance.

  According to a fifth aspect of the present invention, a capacitor is connected to an electrode pair that is formed on a package on which a semiconductor integrated circuit is mounted and is connected to a power supply input portion and a reference potential input portion of the semiconductor integrated circuit. The electrode pair has a resistance greater than that of at least metal and polysilicon.

  According to the present invention, the semiconductor integrated circuit and the capacitor are mixedly mounted on the package, and the electrode pair for connecting to the power supply input portion and the reference potential input portion of the semiconductor integrated circuit is formed, and the capacitor is connected to the electrode pair. Is done. As the capacitor, for example, a chip-type multilayer ceramic capacitor can be used.

  The electrode pair formed on the package has a resistance that is at least greater than that of metal and polysilicon, and the electrode pair itself has a loss.

  When a resistance element is added between the electrode pair and the switching portion of the semiconductor integrated circuit, the resonance point moves to the low frequency side where the harmonic energy of the switching frequency is large due to the addition of inductance, which is not preferable. By providing a loss to the electrode pair itself as described above, the resonance between the stray capacitance and the inductance of the switching element portion caused by the capacitor portion having a low impedance at a high frequency can be mitigated.

  As described above, according to the present invention, when on-chip decoupling is performed, electromagnetic radiation due to resonance can be suppressed and the charge supply efficiency can be prevented from decreasing.

(First embodiment)
The first embodiment of the present invention will be described below. In the present embodiment, a case where the present invention is applied to an inverter circuit will be described.

  FIG. 1 is a schematic perspective view showing a part of a semiconductor integrated circuit device 10 according to the present invention. FIG. 2 shows a circuit diagram of the semiconductor integrated circuit device 10.

  As shown in FIG. 1, a semiconductor integrated circuit device 10 includes an inverter circuit 12 and a capacitor 14 as functional circuits included in a semiconductor integrated circuit (semiconductor chip).

  As shown in FIG. 2, the inverter circuit 12 is a so-called CMOS inverter formed by connecting a p-type MOS transistor (hereinafter referred to as pMOS) 16 and an n-type MOS transistor (hereinafter referred to as nMOS) 18. .

  As shown in FIG. 1, the pMOS 16 has an n-well 22 made of an n-type semiconductor formed on a p-type substrate (for example, a silicon substrate) 20 made of a p-type semiconductor. The p diffusion regions 24A and 24B are formed, and the dielectric film 26 and the gate electrode 28 are laminated so as to straddle the p diffusion regions 24A and 24B.

  In the nMOS 18, n diffusion regions 30A and 30B made of an n type semiconductor are formed on a p type substrate 20, and a dielectric film 32 and a gate electrode 34 are laminated so as to straddle the n diffusion regions 30A and 30B. It has become.

  The gate electrodes 28 and 34 are connected to an input terminal 40 for signal input, and the p diffusion region 24B and the n diffusion region 30A are connected to an output terminal 42 for signal output.

  The capacitor 14 has a configuration in which a dielectric 38 is sandwiched between electrode pairs including electrodes 36A and 36B. The electrode 36A is connected to the p diffusion region 24A of the pMOS 16, the n diffusion region 44 formed on the n well 22, and the VDD terminal 46 for power supply (VDD) input. The electrode 36B is connected to the n diffusion region 30B of the nMOS 18, the p diffusion region 48 formed on the p-type substrate 20, and the VSS terminal 50 for ground potential (VSS).

Here, the dielectric 38 is made of, for example, a silicon oxide film. On the other hand, the electrodes 36A and 36B are formed of a material having a loss larger than that of metal or polysilicon (conductivity: 4.0 × 10 ⁶ [S / cm]) that is usually used as a material of the electrode. Examples of such materials include nichrome (conductivity: 1.0 × 10 ⁶ [S / cm]), carbon (conductivity: 3.0 × 10 ⁴ ), tellurium (conductivity: 5.0 × 10 ^3). [S / cm]), etc., but is not limited to this as long as the material has a loss larger than that of metal or polysilicon.

  The capacitor 14 is provided by using an empty cell of the semiconductor element, or is provided by forming a capacitor cell in the semiconductor element.

  As described above, for the on-chip decoupling, a capacitor is provided using an empty cell of the semiconductor element, or a loss is applied to the electrodes 36A and 36B of the capacitor 14 provided by forming the capacitor cell in the semiconductor element. By providing this, the resonance between the stray capacitance and the inductance of the switching element portion, which is caused when the portion of the capacitor 14 has a low impedance at a high frequency, can be mitigated.

  Note that the capacitance of the capacitor 14 used for on-chip decoupling is preferably set to a sufficiently large value (usually 10 times or more) with respect to the capacitance simultaneously switched in the semiconductor integrated circuit device 10. Under such conditions, it can be regarded as a series circuit with a switching capacitance C and a loss due to the electrodes 36A and 36B, that is, a resistance R component. Accordingly, by determining the capacitance of the capacitor 14 and the resistance values of the electrodes 36A and 36B so that the cut-off frequency f (= 1 / 2πCR) falls within the frequency band (about several hundred MHz) of the electromagnetic wave radiation to be suppressed. Band resonance can be suppressed.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same part as 1st Embodiment, and the detailed description is abbreviate | omitted.

  FIG. 3 is a schematic perspective view of the semiconductor integrated circuit device 60 according to the present embodiment. The semiconductor integrated circuit device 60 is different from the semiconductor integrated circuit device 10 shown in FIG. 1 only in the configuration of the capacitor 62, and other description is omitted.

  The capacitor 62 has a configuration in which a dielectric 66 is sandwiched between electrode pairs including electrodes 64A and 64B. The electrodes 64A and 64B are made of a commonly used semiconductor such as metal or polysilicon, and the dielectric 66 is made of a dielectric material having a dielectric loss larger than that of a generally used silicon oxide film. Examples of such a dielectric material include polyimide (tan δ = 0.005), nylon (tan δ = 0...) Having a dielectric loss larger than that of silicon (tan δ (dielectric loss) = 0.001 to 0.004). 04), epoxy (tan δ = 0.02) and the like, but not limited to this as long as the material has a dielectric loss larger than that of silicon.

  In this way, by forming the dielectric 66 constituting the capacitor 62 with a dielectric material having a dielectric loss higher than that of silicon, it is possible to suppress the resonance by giving a loss to the high-frequency resonance current, and sufficiently Can be ensured.

(Third embodiment)
Next, a third embodiment of the present invention will be described.

  FIG. 4 shows a schematic cross-sectional view of the semiconductor integrated circuit device 70 according to the present embodiment. As shown in FIG. 4, the semiconductor integrated circuit device 70 is a BGA (Ball Grid Array) type semiconductor integrated circuit device, in which a semiconductor integrated circuit 74 is mounted on a semiconductor integrated circuit package 72, and a printed wiring (not shown) The substrate is electrically connected by a ball grid 76.

  The power supply (VDD) input portion 78 of the semiconductor integrated circuit 74 is connected to an electrode pad 82 A formed on the semiconductor integrated circuit package 72 by a wiring 80. One end of a decoupling capacitor 84 is connected to the electrode pad 82A, and the other end of the decoupling capacitor 84 is connected to an electrode pad 82B formed on the semiconductor integrated circuit package 72. The electrode pad 82A is connected to a ball grid 76G for ground (VSS) through a wiring 86, and the electrode pad 82B is connected to a ball grid 76V for power supply input through a wiring 88. As described above, the decoupling capacitors 84 are provided on the semiconductor integrated circuit package 72 in accordance with the number of power input portions 78 of the semiconductor integrated circuit 74.

  As the decoupling capacitor 84, for example, a chip-type multilayer ceramic capacitor or the like can be used.

  Here, the electrode pads 82A and 82B have the same loss as in the first embodiment. That is, the electrode pads 82A and 82B are formed of a material having a larger loss than a metal or polysilicon used as a normal electrode material.

  Thus, for on-chip decoupling, a decoupling capacitor 84 is provided on the semiconductor integrated circuit package 72, and loss is caused in the power supply and ground electrode pads 82A and 82B to which the decoupling capacitor 84 is connected. By providing it, the resonance between the stray capacitance and the inductance of the switching element portion caused by the decoupling capacitor 84 portion having a low impedance in terms of high frequency can be mitigated.

  In the present embodiment, the case where the present invention is applied to a BGA type semiconductor integrated circuit device has been described. However, the present invention is not limited to this and can be applied to other types of semiconductor integrated circuit devices. Absent.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same part as 1st Embodiment, and the detailed description is abbreviate | omitted.

  FIG. 5 is a schematic perspective view of the semiconductor integrated circuit device 90 according to the present embodiment. As shown in FIG. 5, the semiconductor integrated circuit device 90 includes the inverter circuit 12 similar to that shown in FIG.

  The capacitor 92 includes an n diffusion region 94 in which a predetermined region of the p-type substrate 20 is doped with electron carriers, a dielectric film 96, and an electrode film 98. As the dielectric film 96, for example, a silicon oxide film obtained by oxidizing the p-type substrate 20 may be used as it is, or may be formed of a lossy material as described in the second embodiment. The electrode film 98 may be made of metal, polysilicon, or the like, but it is preferable to use a lossy material as described in the first embodiment.

  The n diffusion region 94 is connected to the p diffusion region 48 connected to the VSS terminal 50, and the electrode film 98 is connected to the n diffusion region 44 connected to the VDD terminal 46.

  As described above, the n diffusion region 94 functions as an electrode of the capacitor 92, but an arbitrary conductivity can be obtained by controlling the doping amount of the electron carrier.

  Therefore, by setting the doping amount of the electron carrier according to the strength of resonance, the optimum resistance value according to the strength of resonance can be obtained, and resonance can be effectively suppressed.

  Next, examples of the present invention will be described.

  FIG. 6 shows the result of simulating the relationship between the frequency of electromagnetic wave radiation and the voltage value with the SPICE program for the semiconductor integrated circuit device 10 described in the first embodiment.

  In the simulation, as shown in FIG. 7, the inverter circuit 12 of the semiconductor integrated circuit device 10 is equivalent to a standard product of a low voltage CMOS inverter, and a 20 MHz rectangular wave signal is used as a drive source for driving the inverter circuit 12. Source 100 was used. Further, the inverter circuit 12 is mounted by, for example, a so-called SOP package 101 and connected to a power source and a ground through a power source wiring impedance 102 of the inverter circuit 12, and a capacitance component 104 of a capacitor 14 for on-chip decoupling is connected thereto. The simulation was performed by SPICE under the condition that the resistance component 106 by the electrodes 36A and 36B was added.

  As shown in FIG. 6, when the on-chip decoupling capacitive component 104 does not exist, the 20 MHz clock harmonics have a wide distribution with a peak in the vicinity of 700 MHz.

  In addition, when the capacitance of the capacitive component 104 is 1000 pF and the resistance component 106 is not added, that is, when no loss is given, the frequency component of 300 MHz or more is remarkably suppressed, but at the same time, a resonance peak occurs at 200 MHz. It has occurred.

  Further, when the resistance value of the resistance component 106 is set to 1Ω, that is, when some loss is given, the resonance peak at 200 MHz is almost completely suppressed without significantly damaging the suppression effect on the frequency component of 300 MHz or higher. Has been.

  That is, by configuring the capacitor for on-chip decoupling as in the present invention, it is possible to suppress an increase in electromagnetic radiation due to resonance generated in a loop with the stray capacitance of the transistor to be switched, and to improve the efficiency of charge supply. It was found that it was possible to prevent the decrease.

  It should be noted that substantially the same result can be obtained when the loss of the dielectric is increased as shown in the second embodiment, instead of giving the electrode a loss as in the present simulation. The same effect is also obtained for the structure in which the chip capacitor is mounted on the semiconductor integrated circuit package as shown in the third embodiment and the structure in which the semiconductor diffusion region is used as the electrode as shown in the fourth embodiment. can get.

1 is a schematic partial cross-sectional perspective view of a semiconductor integrated circuit device according to a first embodiment. 1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment. FIG. 6 is a schematic partial cross-sectional perspective view of a semiconductor integrated circuit device according to a second embodiment. It is a schematic sectional drawing of the semiconductor integrated circuit device which concerns on 3rd Embodiment. It is a general | schematic partial cross-section perspective view of the semiconductor integrated circuit device concerning 4th Embodiment. It is a diagram which shows the simulation result of the relationship between the frequency of electromagnetic wave radiation, and a voltage value. It is a figure for demonstrating a simulation model.

Explanation of symbols

10, 60, 70, 90 Semiconductor integrated circuit device 12 Inverter circuits 14, 62, 92 Capacitor 20 P-type substrate 22 N wells 24A, 24B, 48 p Diffusion regions 26, 32 Dielectric films 28, 34 Gate electrodes 30A, 30B, 44, 94 n Diffusion regions 36A, 36B, 64A, 64B Electrodes 38, 66 Dielectric 40 Input terminal 42 Output terminal 46 VDD terminal 50 VSS terminal 72 Semiconductor integrated circuit package 74 Semiconductor integrated circuits 82A, 82B Electrode pad 84 Decoupling capacitor 96 Dielectric film 98 Electrode film

Claims (5)

  A capacitor composed of an electrode pair and a dielectric sandwiched between the electrode pair is formed in the semiconductor integrated circuit between a power supply input portion and a reference potential input portion of a functional circuit included in the semiconductor integrated circuit, A semiconductor integrated circuit device, wherein at least one of the electrode pair and the dielectric has a predetermined loss.   The semiconductor integrated circuit device according to claim 1, wherein the electrode pair has a resistance at least greater than that of metal and polysilicon.   3. The semiconductor integrated circuit device according to claim 1, wherein the dielectric has a dielectric loss larger than at least silicon oxide.   4. The semiconductor integrated circuit according to claim 1, wherein one electrode of the electrode pair is a diffusion region in which a semiconductor substrate constituting the semiconductor integrated circuit is doped with a carrier. 5. apparatus.   A capacitor is connected to an electrode pair that is formed on a package on which the semiconductor integrated circuit is mounted and is connected to a power supply input portion and a reference potential input portion of the semiconductor integrated circuit, and the electrode pair is at least a metal And a semiconductor integrated circuit device having a larger resistance than polysilicon.

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