JP2004536417A5 - - Google Patents

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Publication number
JP2004536417A5
JP2004536417A5 JP2003512981A JP2003512981A JP2004536417A5 JP 2004536417 A5 JP2004536417 A5 JP 2004536417A5 JP 2003512981 A JP2003512981 A JP 2003512981A JP 2003512981 A JP2003512981 A JP 2003512981A JP 2004536417 A5 JP2004536417 A5 JP 2004536417A5
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JP
Japan
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JP2003512981A
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JP2004536417A (ja
JP4199658B2 (ja
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Priority claimed from US09/905,004 external-priority patent/US6779074B2/en
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Publication of JP2004536417A publication Critical patent/JP2004536417A/ja
Publication of JP2004536417A5 publication Critical patent/JP2004536417A5/ja
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Publication of JP4199658B2 publication Critical patent/JP4199658B2/ja
Anticipated expiration legal-status Critical
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JP2003512981A 2001-07-13 2002-07-10 読出及び書込動作でバースト順序が異なるアドレッシングを行うメモリデバイス Expired - Fee Related JP4199658B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/905,004 US6779074B2 (en) 2001-07-13 2001-07-13 Memory device having different burst order addressing for read and write operations
PCT/US2002/022458 WO2003007303A2 (en) 2001-07-13 2002-07-10 Memory device having different burst order addressing for read and write operations

Publications (3)

Publication Number Publication Date
JP2004536417A JP2004536417A (ja) 2004-12-02
JP2004536417A5 true JP2004536417A5 (ja) 2005-11-17
JP4199658B2 JP4199658B2 (ja) 2008-12-17

Family

ID=25420145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003512981A Expired - Fee Related JP4199658B2 (ja) 2001-07-13 2002-07-10 読出及び書込動作でバースト順序が異なるアドレッシングを行うメモリデバイス

Country Status (8)

Country Link
US (3) US6779074B2 (ja)
EP (1) EP1415304B1 (ja)
JP (1) JP4199658B2 (ja)
KR (2) KR100679370B1 (ja)
CN (1) CN100419901C (ja)
AT (1) ATE406657T1 (ja)
DE (1) DE60228585D1 (ja)
WO (1) WO2003007303A2 (ja)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6779074B2 (en) * 2001-07-13 2004-08-17 Micron Technology, Inc. Memory device having different burst order addressing for read and write operations
US6775759B2 (en) 2001-12-07 2004-08-10 Micron Technology, Inc. Sequential nibble burst ordering for data
US7054999B2 (en) * 2002-08-02 2006-05-30 Intel Corporation High speed DRAM cache architecture
US7142461B2 (en) * 2002-11-20 2006-11-28 Micron Technology, Inc. Active termination control though on module register
US20040194500A1 (en) * 2003-04-03 2004-10-07 Broadway Entertainment, Inc. Article of jewelry
KR100612414B1 (ko) * 2003-04-28 2006-08-16 삼성전자주식회사 영상 데이터 처리 시스템 및 영상 데이터 독출/기입 방법
US6982892B2 (en) * 2003-05-08 2006-01-03 Micron Technology, Inc. Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
US20050172091A1 (en) * 2004-01-29 2005-08-04 Rotithor Hemant G. Method and an apparatus for interleaving read data return in a packetized interconnect to memory
US7916574B1 (en) * 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7519877B2 (en) * 2004-08-10 2009-04-14 Micron Technology, Inc. Memory with test mode output
US20060171233A1 (en) * 2005-01-18 2006-08-03 Khaled Fekih-Romdhane Near pad ordering logic
US20060256793A1 (en) * 2005-05-13 2006-11-16 Freescale Semiconductor, Inc. Efficient multi-bank buffer management scheme for non-aligned data
US8239637B2 (en) * 2007-01-19 2012-08-07 Spansion Llc Byte mask command for memories
US8230154B2 (en) * 2007-01-19 2012-07-24 Spansion Llc Fully associative banking for memory
GB2480192A (en) * 2007-02-02 2011-11-09 Ubiquisys Ltd Determining the location of a base station
US8085801B2 (en) * 2009-08-08 2011-12-27 Hewlett-Packard Development Company, L.P. Resource arbitration
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
US8792294B2 (en) * 2012-01-09 2014-07-29 Mediatek Inc. DRAM and access and operating method thereof
US9396109B2 (en) * 2013-12-27 2016-07-19 Qualcomm Incorporated Method and apparatus for DRAM spatial coalescing within a single channel
US9792049B2 (en) * 2014-02-24 2017-10-17 Cypress Semiconductor Corporation Memory subsystem with wrapped-to-continuous read
CN111796306B (zh) * 2020-07-31 2023-05-02 北京中捷时代航空科技有限公司 一种导航卫星信号接收方法及接收机
CN113299328A (zh) * 2021-05-21 2021-08-24 深圳市格灵精睿视觉有限公司 随机寻址读写控制方法、控制系统及存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5402389A (en) * 1994-03-08 1995-03-28 Motorola, Inc. Synchronous memory having parallel output data paths
JP3605150B2 (ja) 1994-08-22 2004-12-22 株式会社アドバンテスト アドレスパターン発生器
US5513148A (en) * 1994-12-01 1996-04-30 Micron Technology Inc. Synchronous NAND DRAM architecture
US5850368A (en) 1995-06-01 1998-12-15 Micron Technology, Inc. Burst EDO memory address counter
US5966724A (en) 1996-01-11 1999-10-12 Micron Technology, Inc. Synchronous memory device with dual page and burst mode operations
US5749086A (en) 1996-02-29 1998-05-05 Micron Technology, Inc. Simplified clocked DRAM with a fast command input
US5784705A (en) 1996-07-15 1998-07-21 Mosys, Incorporated Method and structure for performing pipeline burst accesses in a semiconductor memory
US5917760A (en) 1996-09-20 1999-06-29 Sldram, Inc. De-skewing data signals in a memory system
US5903496A (en) 1997-06-25 1999-05-11 Intel Corporation Synchronous page-mode non-volatile memory with burst order circuitry
US6640266B2 (en) * 2000-03-24 2003-10-28 Cypress Semiconductor Corp. Method and device for performing write operations to synchronous burst memory
US6779074B2 (en) * 2001-07-13 2004-08-17 Micron Technology, Inc. Memory device having different burst order addressing for read and write operations

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