JP2004531054A - Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits - Google Patents

Abstract

Structures and methods for fabricating high-speed digital, analog, and combined digital / analog systems using planarization relaxed SiGe as a material platform. Relaxed SiGe results in excess strained Si layers with enhanced electronic properties. By placing or embedding MOSFET channels on the surface, high speed digital and / or analog circuits can be made. Planarization prior to depositing the epitaxial layers of the device ensures a flat surface for high-level lithography. According to one embodiment of the present invention, planarization relaxed Si _1-x Ge _x layer and the planarization relaxed Si _1-x Ge _x layer on the deposited device heterostructure comprising at least one strained layer on a substrate Resulting in a semiconductor structure comprising:
[Selection diagram] Fig. 1

Description

[Priority information]
[0001]
The present invention claims priority from U.S. Patent Nos. 09 / 906,551 and 09 / 906,545, both filed on July 16, 2001, which are incorporated by reference in their entirety. No. 60 / 273,112, filed on Jan. 2, which claims priority.
【Technical field】
[0002]
The present invention relates to the field of relaxed SiGe platforms for high-speed CMOS electronics and high-speed analog circuits.
[Background Art]
[0003]
Si CMOS as a platform for digital integrated circuits has evolved as predicted by the industry roadmap. That advance has been driven by device scaling, resulting in higher performance, higher reliability, and even lower cost. However, as the interconnect hierarchy has increased, new obstacles in data flow have become apparent. Digital integrated circuits have advanced at an unprecedented rate, while analog circuits have made little progress. In addition, in the near future, serious economic and technical problems will stand in the way of digital integrated circuits.
[0004]
The digital and telecommunications chip market requires the full development of Si CMOS enhancements and roadmaps. One highly promising material candidate that enhances digital integrated circuit technology and creates new analog integrated circuit possibilities is relaxed SiGe material on Si substrates. A relaxed SiGe alloy on Si can have a thin layer of Si deposited thereon. Tensile Si layers have many advantageous properties for the basic devices of integrated circuits, metal oxide field effect transistors (MOSFETs). First, when Si is placed in a tensile state, the electron mobility that moves parallel to the surface of the wafer increases, thereby increasing the operating frequency of the circuit associated with the MOSFET. Second, the band offset between relaxed SiGe and strained Si traps electrons in the Si layer. Thus, in an electronic channel device (n-channel), the channel can be removed from the surface or “buried”. This ability to spatially separate charge carriers from scattering centers, such as ionized impurities and "rough" oxide interfaces, allows for the production of low noise, high performance analog devices and circuits.
[0005]
A central development in this area was the invention of a relaxed SiGe buffer with a low threshold dislocation density. Background inventions centered on such fields are disclosed in US Pat. No. 5,442,205 to Brasen et al. And US Pat. No. 6,107,653 to Fitzgerald. These patents describe currently the best method for producing high quality relaxed SiGe.
[0006]
New device structures in the laboratory have been built on the earliest basic types of relaxation buffers. For example, the unique g _m A strained Si, surface channel n MOSFET (Rim et al., IEDM 98 Tech. Dig. P. 707) has been fabricated that exhibits more than 60% enhancement and more than 75% increased electron mobility. Strained Si, buried channel devices with high transconductance and high mobility have also been manufactured (U. Konig, MRS Symposium Proceedings 533, 3 (1998)). Unfortunately, these devices have various commercialization problems. First, if the material is relaxed by the introduction of dislocations, the SiGe surface on Si becomes very rough, and the quality of commonly available materials is insufficient for practical applications. Such dislocations are essential when growing a relaxed SiGe layer on Si to compensate for the stress caused by lattice mismatch between the materials. For more than a decade, researchers have attempted to intrinsically control the surface morphology by epitaxial growth, but the intrinsic epitaxial solution has been inadequate because the stress field due to unsuitable dislocations affects the growing surface. It was possible. The present invention discloses a planarization and regrowth method that allows all devices built on relaxed SiGe to have a significantly planar surface. Reducing surface roughness increases the yield of fine-line lithography, thereby enabling the production of strained Si devices.
[0007]
A second problem with previously fabricated strained Si devices is that researchers have dedicated themselves to optimizing the device for a wide variety of applications. Surface channel devices have been explored to enhance conventional MOSFET devices, and buried channel devices can only mimic previously available buried channel devices in III-V materials such as AlGaAs / GaAs. Has been built. Disclosed here by recognizing that the substructure that fabricates Si requires a material platform that is compatible with Si, scalable, and can be used in high volume Si integrated circuit applications. The present invention provides a platform that enables both the enhancement of Si CMOS-based circuits and the manufacture of analog circuits. Therefore, high performance analog or digital systems can be designed using this flat form. As a further advantage, either type of circuit can be manufactured in a CMOS process, so that it is possible to design a combined integrated digital / analog system as a single chip solution.
[0008]
Such advanced SiGe material platforms have enabled the provision of various devices and circuit topologies that utilize this new material system. According to an exemplary embodiment of the present invention, an improved strained layer Si device structure and method of assembly and a circuit based on device diversity, all structures and methods of assembly from the same starting material platform are disclosed. . Starting from the same material platform is key to minimizing cost and building as many circuit topologies as possible on this platform.
DISCLOSURE OF THE INVENTION
[Problems to be solved by the invention]
[0009]
Thus, the present invention provides a flat relaxed SiGe platform material with regrown device layers. The method of planarization and regrowth allows the device layer to have a minimum surface roughness as compared to the method of growing the device layer without planarization. This flattened and regrown platform is a receiver for strained Si devices that may have optimal properties for both digital and analog circuits. A structure and process is described that allows for the assembly of high performance digital logic and analog circuits, which structure is utilized to accept a combination of digital and analog circuits forming a single system-on-chip. be able to.
[Means for Solving the Problems]
[0010]
According to one embodiment of the present invention, a relaxed Si planarized on a substrate _1-x Ge _x Semiconductor structure comprising a layer and a planarized relaxed Si having at least one strained layer _1-x Ge _x A device heterostructure is provided that is deposited on the layer.
BEST MODE FOR CARRYING OUT THE INVENTION
[0011]
FIG. 1 is a schematic block diagram of a structure 100 having a relaxed SiGe layer epitaxially grown on a Si substrate. In this structure, a composition gradient buffer layer 104 is used to adjust the lattice mismatch between the uniform SiGe layer 106 and the Si substrate. Extending the lattice mismatch over a distance minimizes the number of dislocations reaching the surface by the tilt buffer, thereby providing a way to grow high quality relaxed SiGe films on Si.
[0012]
Any method of growing a high quality relaxed SiGe layer on Si results in a known cross-hatch pattern roughness on the surface of the SiGe layer. This crosshatch pattern has a thickness of several hundred angstroms, typically over a distance of a few micrometers. Therefore, the crosshatch pattern has a surface morphology that is gentle and undulating with respect to the size of electrons or holes. For that reason, it is possible to build individual devices that achieve enhancement over the control Si device complement. However, commercializing these devices requires injecting materials into the Si CMOS process environment to obtain low cost, high performance objects. This process environment requires that the properties of the materials and devices have minimal impact on the manufacturing process. Cross-hatch patterns on the wafer surface are one of the limiting properties of relaxed SiGe on Si that affect yield and manufacturing simplicity. Therefore, for higher yield and simplicity in lithography, flattening is desired.
[0013]
The cross hatch pattern is derived from the stress field due to injected maladaptive dislocations. The effect is illustrated by the exemplary structure 200 shown in FIG. Obviously, dislocations must be introduced to adjust the lattice mismatch between the SiGe alloy and the Si substrate. The stress field starts at the dislocation and ends at the film surface. However, termination at the surface results in a crystal lattice migrating around on the surface of the wafer. It is possible to correlate the growth rate to certain dimensions of the grating, different thicknesses of the deposits occurring at different locations on the wafer. One would think that growing thick layers beyond the maladaptive dislocations would eliminate the unevenness in the thickness of these different layers. Unfortunately, because surface undulations have a relatively long period, surface diffusion is typically not large enough to remove its morphology.
[0014]
FIG. 3 is a table showing surface roughness data for a relaxed SiGe buffer generated by injecting dislocations through a graded SiGe layer on a Si substrate. Relaxed Si _0.8 Ge _0.2 Note that the as-grown crosshatch pattern for the buffer produces a typical roughness of approximately 7.9 nm. This average roughness increases as the Ge content in the relaxation buffer increases. Thus, for SiGe layers that have been relaxed by the introduction of dislocations during growth, the surface roughness is unacceptable for high-tech assembly manufacturing equipment. After the relaxed SiGe planarization step, the average roughness is less than 2 nm (typically 0.57 nm), and after deposition of the device layer, the average roughness is 0.77 with a regrowth thickness of 1.5 μm. nm. Thus, it is possible to reduce the roughness by an order of magnitude or more after the structure has been completely assembled.
[0015]
The regrown device layer may exceed or be less than the critical thickness of the regrown layer. In general, in lattice-mismatched epitaxial growth, a thin layer can be deposited without worrying about the introduction of dislocations at the interface. At a sufficiently large thickness, any lattice mismatch between the film and the substrate will also introduce maladaptive dislocations in the regrown heterostructure. Such new dislocations may cause additional surface roughness. Thus, if the lattice mismatch between the regrown device layer and the relaxed SiGe buffer is too large, the effect of planarizing the relaxed SiGe will be lost because the introduction of large dislocations will roughen the surface.
[0016]
There are two distinct possibilities for regrown thickness and surface quality. If the regrown layer is very thin and the lattice exactly matches the composition of the regrown layer, no relaxation buffer element is needed. In this case, the surface roughness will be very small, approximately equal to the flatness after planarization. However, in many applications of the device, the thickness of the regrown layer is 1-2 μm or more. If the Ge concentration between the relaxed SiGe and the regrown layer differs by 1%, the critical thickness is about 0.5 μm. Therefore, if optimal flatness is desired, it is best to keep the regrown layer below about 0.5 μm unless the uniformity of Ge concentration across the wafer can be adequately controlled. While this compositional match can be achieved with high-tech tools, FIG. 3 shows an inaccurate match, ie, the introduction of maladaptive dislocations and new cross-links due to Ge concentrations within 2%. It shows that the introduction of a hatch pattern results. However, due to the small lattice mismatch, the average roughness is still very low at about 0.77 nm. Thus, lattice mismatch or some mismatch will result in a good device layer surface for processing.
[0017]
It should also be noted that a relaxed SiGe alloy having a surface roughness need not be a uniform composition relaxed SiGe layer in the composition gradient layer. Although this material layer structure was shown as an early example of high quality relaxed SiGe, this structure has several disadvantages. For example, SiGe alloys have a very low coefficient of thermal conductivity as compared to pure Si. Therefore, for electronic devices located on the surface, it may be relatively difficult to release heat from the device area due to the thick composition gradient layer and the uniform composition layer.
[0018]
According to another exemplary embodiment of the present invention shown in FIGS. 4A-4D, this problem can be solved and a platform for high power SiGe devices is manufactured. 4A-4D illustrate an exemplary process flow and resulting platform structure in accordance with the present invention. The structure is manufactured by first forming a uniform relaxed SiGe alloy 400 through a compositionally graded layer 402 on a Si substrate 404. The SiGe layer 400 is then transferred to the second Si substrate 406 using a conventional bonding method. For example, the uniform SiGe alloy 400 on the graded layer 402 allows for flattening to remove cross-hatch patterns and allows the relaxed SiGe alloy to be bonded to the Si wafer. The graded layer 402 and the original substrate 404 can be removed by various conventional processes. For example, as one method, there is a method of selectively etching SiGe by pulverizing and removing the original Si substrate, performing a controlled dry etching or wet etching, or embedding an etching stopper layer. . The end result is a relaxed SiGe alloy 400 on Si without a thick graded layer. This structure is more suitable for high power applications because it can conduct heat more efficiently from the SiGe layer.
[0019]
This bonding and substrate removal technique can also be used to fabricate SiGe on insulating substrates or SGOIs. The SGOI wafer is manufactured using a similar technique as shown in FIGS.4A-4D, but the second substrate is SiO2 prior to bonding. _Two Coated with a layer. In an alternative embodiment, each wafer is made of SiO 2 to allow for oxide-oxide bonding. _Two Can be coated. The resulting structure after removing the substrate is a high quality, relaxed SiGe layer on the insulating film. Devices built on this platform can be used to enhance the performance of both strained Si and SOI architectures.
[0020]
It should be understood that if the SiGe layer is transferred to another receiving substrate, it may still be necessary to planarize before regrowth of the device layer structure. The SiGe surface may be too rough for high-level methods with substrate removal techniques. In this case, the relaxed SiGe is planarized and the device layer is regrown on the top layer of the high quality relaxed SiGe surface.
[0021]
Planarizing the surface by mechanical or other physical methods is necessary to planarize the surface and obtain a CMOS quality device. However, field effect transistors (FETs) that can enhance digital and analog circuits are very thin and may be removed during the planarization process. Therefore, the first part of the present invention recognizes that the growth and planarization of relaxed SiGe following device layer regrowth is key to producing enhanced CMOS platforms with high performance and high yield. It is in. 5 and 6 illustrate the processing sequence and regrowth layers required to fabricate each of the surface channel FET and buried channel FET embodiments.
[0022]
5A to 5D are diagrams schematically illustrating the process flow and the resulting layer structure according to the present invention. FIG. 5A shows a typical surface roughness 500 of a relaxed SiGe alloy 502 on a substrate 504 as an exaggerated undulating surface. Note that the substrate is labeled in a comprehensive manner because the substrate itself is Si, a compositionally graded relaxed SiGe layer on Si, or other material to which relaxed SiGe has been transferred by wafer bonding and removal techniques. . The relaxed SiGe alloy 502 is planarized to remove substantial roughness (FIG. 5B), and then a device regrowth layer 506 is deposited epitaxially (FIG. 5C). It is desirable that the composition of the regrown layer 506 be lattice-matched as close as possible to the relaxed SiGe 502, but the surface remains substantially flat, so that slight misalignments and dislocations at the interface are eliminated. Introduction is acceptable. For surface channel devices, a strained Si layer 508 having a thickness of less than 0.1 μm is then grown on top of a relaxed SiGe 502 with an optional sacrificial layer 510, as shown in FIG. 5D. The strained layer 508 is a layer used as a channel in the final CMOS device.
[0023]
6A to 6D schematically show the corresponding process flow and layer structure for a buried channel FET platform according to the present invention. In this structure, the regrown layer 606 includes a lattice-matched SiGe layer 602, a strained Si channel layer 608 having a thickness of less than 0.05 μm, a SiGe isolation or spacer layer 612, a Si gate oxide layer 614, and initial processing steps of the device. Includes an optional sacrificial layer 610 used to protect the heterostructure between.
[0024]
Once the device structure is deposited, the rest of the process flow for assembling the device is very similar to that of bulk Si. FIGS. 7A to 7D show a simplified process flow of the surface channel MOSFET according to the present invention. This surface channel MOSFET includes a relaxed SiGe layer 700 and a strained Si layer 702. The device isolation oxide 704 shown in FIG. 7A is typically formed first. In this step, the SiN layer 706 on top of the thin pad oxide layer 708 acts as a hard mask for either local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Both techniques use thick oxides (compared to device dimensions) to obtain high threshold voltages between devices. However, STI is more suitable for techniques below 0.25 μm. FIG. 7B shows a schematic of the device region after the gate oxide 716 has been grown and a shallow source-drain has been implanted. Implant region 710 is self-aligned using poly-Si gate 712 patterned with photoresist 714 as a masking layer. Subsequently, a deep source-drain implant 718 is placed utilizing conventional spacer 720 formation techniques, and the device forms silicide 722 at the gate and silicide / germanide 724 at the source and drain. Electrical contact (FIG. 7C). FIG. 7D shows a schematic of the device after the first level metal interconnect 726 has been deposited and etched.
[0025]
Due to the limited thickness of the layer on top of the entire structure, removal of surface material during the process is more difficult than with standard Si. For surface channel devices, the regrown structure is composed primarily of nearly lattice-matched SiGe and includes a standard Si thin surface layer. Most of the first steps in the Si manufacturing process procedure remove Si from the surface. Without careful control of the process, the entire strained Si layer may be removed prior to gate oxidation. Since the resulting device is a relaxed SiGe channel FET, it is advantageous that a strained Si channel is not realized.
[0026]
The logical solution to address the removal of Si during the initial steps is to make the strained Si layer thick enough to offset this removal. However, thick Si layers are not possible for two reasons. First, it is based on the fact that the enhanced electrical properties distort Si and that thick layers release pressure through the introduction of maladaptive dislocations. Second, the maladaptive dislocations themselves are undesirable in large quantities because they scatter carriers and increase the leakage current at the junction.
[0027]
Cleaning steps before oxidizing the gate must be minimized and / or a protective layer applied to prevent removal of the strained Si layer at the surface. A protective layer is useful because its removal can be done carefully. Some examples of protective layers for surface channel devices are shown in FIGS. 8A and 8B. FIG. 8A shows a strained Si heterostructure consisting of a relaxed SiGe layer 800 and a strained Si channel layer 802 protected by a surface layer 804 of SiGe. Since the surface SiGe layer 804 has the same Ge concentration as the lower relaxed SiGe layer 800, the thickness is not limited by the critical thickness limitation. During the initial cleaning, the SiGe sacrificial layer is removed instead of the strained Si channel layer. The thickness of the sacrificial layer can be adjusted to be equal to or greater than the thickness to be removed. In the latter case, the excess SiGe can be selectively removed prior to the step of oxidizing the gate so as to expose a strained Si layer free of impurities at the thickness as grown. If a Si-terminated surface is preferred for a particular manufacturing facility, a sacrificial Si layer can be deposited over the SiGe sacrificial cap layer.
[0028]
FIG. _Two Shown is a structure in which a layer 806 and a surface layer 808 of either polycrystalline or amorphous material are used as a protective layer. In this method, an oxide layer is grown or deposited after epitaxial growth of a strained Si layer. Next, a polycrystalline or amorphous layer of Si, SiGe or Ge is deposited. Such a semiconductor layer protects the strained Si layer during the process before oxidizing the gate, similar to a SiGe cap. Prior to oxidizing the gate, the polycrystalline / amorphous and oxide layers are selectively removed. Although a sacrificial layer is shown to protect surface channel devices, this technique is also applicable to buried channel heterostructures.
[0029]
Another way to modify the conventional Si process is to form silicide-germanide between the source and drain (FIG. 7C). In a conventional Si processing step, a metal (typically Ti, Co or Ni) is reacted with Si to form a low resistivity silicide by standard annealing procedures. However, in this case, the metal reacts simultaneously with both Si and Ge. Since silicides have very low free energy compared to germanides, Ge tends to be driven out while silicides are formed. The displaced germanium forms lumps and increases contact resistance. This increase in series resistance offsets the benefit of excess drive current from the heterostructure and negates the benefits of the structure.
[0030]
Ti and Ni can form a phase that does not violently reject Ge, so that good contact can be formed. In the case of Co, there is a further problem. However, as described above for the issue of Si removal, a protective layer can be applied at the epitaxial stage of the device instead of optimizing the SiGe-metal reaction. For example, strained Si that becomes a surface channel can be coated with a Ge-rich SiGe alloy (Ge content higher than the initial relaxed SiGe) followed by strained Si. Two approaches utilizing these surface contact layers are possible. Both methods introduce the thicker Si at the surface, so that conventional siliconization techniques can be performed without the problems of the SiGe-metal reaction.
[0031]
The first approach, shown in the surface channel heterostructure 900 of FIG. 9A, uses a Ge-rich layer 906 that is thin enough to provide sufficient strain. The layer 906 is provided on the strained Si channel layer 904 and the relaxed SiGe layer 902. In this case, the next Si layer 908 exceeds the critical thickness, and the compressed Ge-rich layer 906 functions as a barrier to dislocations entering the strained Si channel 904. This barrier is beneficial because dislocations do not have an adverse effect on the siliconization process. Therefore, the presence of dislocations in the next Si layer 908 is not important. However, dislocations penetrating the channel have a detrimental effect on the device.
[0032]
The second approach, shown in FIG. 9B, allows for a Ge-rich layer 910 that exceeds the critical thickness more than intended, thereby allowing sufficient relaxation in the Ge-rich layer. In this case, an Si layer 912 having an arbitrary thickness can be applied on the relaxed Ge-rich layer. Although this layer will contain more defects than the strained channels, these defects have no effect on device operation since this Si is only involved in the silicidation reaction. In each case, the process does not pose any problems with the metal-SiGe reaction, since the metal only reacts with Si.
[0033]
Once the silicide contact is formed, for example, it typically provides a supply of heat due to the fact that silicide-germanide (if used optionally) cannot withstand higher temperatures than conventional silicides. Except for close monitoring, the rest of the procedure is a standard Si CMOS process flow. A major advantage of using Si / SiGe FET heterostructures to achieve enhanced performance is compatibility with conventional Si technology. Many of the steps are the same as in the Si CMOS manufacturing process, and when the first half of the process, that is, the manufacturing process of the Si / SiGe heterostructure, is completed, the entire second half of the process is not affected by the Si / SiGe being placed below.
[0034]
Although the starting heterostructure for the buried channel device is different from the structure of the surface channel device, the process flow is very similar to the surface channel process flow shown in FIGS. 7A to 7D. . FIG. 10 is a schematic block diagram of a buried channel MOSFET structure 1000 after forming a device insulating oxide 1016 using a SiN mask 1014. In this case, the strain channel 1002 on the first SiGe layer 1010 is separated from the surface by growing another SiGe layer 1004, followed by growing another Si layer 1006. This Si layer requires a gate oxide 1008 because the formation of the gate oxide on the SiGe creates a very high interface state, which results in a non-ideal MOSFET. One consequence of this Si layer is that if it is too thick, a significant portion of the Si layer will remain after oxidation of the gate. Carriers concentrate in this residual Si layer, forming surface channels parallel to the desired buried channel, which can result in detrimental device properties. Therefore, the surface layer Si must be kept as thin as possible, typically in the range of 5-15 °, below 50 °.
[0035]
Another additional feature required for buried channel devices is the implantation of the supply layer. When the device is switched on, the vertical affected electric field is strong enough to remove carriers from the buried channel 1002 and the Si / SiO _Two The carriers are concentrated on the Si channel 1006 near the interface 1012. This negates any advantage of the buried channel. Therefore, a dopant supply layer must be introduced either into the layer 1004 between the buried channel and the top Si layer 1006, or below the buried channel below the SiGe 1010. In this way, the device is forcibly switched on with a small voltage or without voltage applied and is switched off by the application of a voltage (depletion mode device).
[0036]
FIG. 11 is a schematic flow diagram of the process for any heterostructure FET device deposited on relaxed SiGe according to the present invention. The steps of the main process are indicated in a box and optional steps or annotations are indicated by circles. The first three steps (1100, 1102, 1104) describe the fabrication and assembly of the strained silicon heterostructure. The procedure includes producing relaxed SiGe on Si, planarizing the SiGe, and regrowing the device layers. Once the strained heterostructure is formed (1106), device isolation using either STI (1110) or LOCOS (1108) is performed (1112), and fabrication and assembly of the MOS is started. Before proceeding with oxidation of the gate, the buried channel device must be subjected to a supply threshold implant (1114) to selectively remove the protective layer applied to either the buried or surface channel heterostructure (1116). ). The procedure of the manufacturing process of the gate oxidation (1118) is similar to the conventional Si CMOS manufacturing process. These steps include gate deposition, doping and definition, self-aligned shallow source-drain implant (1122), spacer formation (1124), self-aligned deep source-drain implant (1126), silicide formation (1128) , And pad separation (1130) via metal deposition and etching. Those steps that require significant changes are discussed.
[0037]
One of the unique advantages of the process of FIG. 11 is that surface channel devices and buried channel devices can be used on the same platform. Considering FIGS. 12A-12D and FIGS. 13A-13D, these illustrate a general arrangement of substrate layers and a fabrication process where surface channel MOSFETs and buried channel MOSFETs coexist on the same chip. This universal substrate is one in which both surface channel devices and buried channel devices can be assembled and manufactured. There are two possibilities when fabricating surface channel devices with this procedure, which are shown in FIGS. 12 and 13. The process flow for coupling the surface channel and the buried channel is similar to the aforementioned process described with reference to FIG. Thus, FIGS. 12 and 13 show only the critical steps involved in exposing the appropriate gate region.
[0038]
12A and 13A show the same basic heterostructure 1200, 1300 for integrating surface and buried channel devices. There are surface strained Si layers 1202, 1302, SiGe spacer layers 1204, 1304, embedded strained Si layers 1206, 1306, and SiGe relaxation platforms 1208, 1308. Since the buried channel MOSFET requires a surface Si layer to form the gate oxide and a buried Si layer to form the device channel, two strained Si layers are required. The figure also shows a device isolation region 1210 that separates the buried channel device regions 1212, 1312 from the surface channel device regions 1214, 1314.
[0039]
Unlike buried channel devices, surface channel MOSFETs require only one strained Si layer. As a result, the surface channel MOSFET may be formed either in the uppermost strained Si layer, as shown in FIGS.12B-12D, or in the buried Si layer channel, as shown in FIGS.13B-13D. Can be. FIG. 12B is a diagram schematically showing the surface channel gate oxide layer 1216 in the uppermost Si layer. In this case, after oxidation, the remaining strained Si layer must be present to form a channel, so that the uppermost Si layer is desirably thicker. FIG. 12B also shows a possible arrangement for a buried channel supply implant 1218, which is typically implanted before growing the buried channel gate oxide. Since the top Si layer is optimized for the surface channel device, it is necessary to remove some of the top strained Si in the region 1220 where the buried channel device is formed, as shown in Figure 12C . To minimize the thickness of the surface Si after the formation of the gate oxide 1222 (FIG. 12D), it must be removable and avoid the formation of parallel device channels.
[0040]
When the surface channel MOSFET is formed in the buried strained Si layer, the uppermost strained Si layer can be thinned, that is, it can be optimally designed as a buried channel MOSFET. In FIG. 13B, the topmost strained Si and SiGe layers are removed in the region 1312 where the surface channel MOSFET is formed. Since Si and SiGe have different properties, range selective removal techniques such as wet chemical etching or dry chemical etching can be used. Selective oxidation can also be used because SiGe oxidizes faster than Si, especially under wet oxidation conditions. FIG. 13C shows a gate oxide 1314 for a surface channel device, as well as a feed layer implant 1316 for a buried channel device. Finally, FIG. 13D shows the location of the buried channel gate oxide 1318. Since the epitaxial thickness is optimized for the buried channel device, it is not necessary to reduce the thickness of the top Si layer prior to oxidation. Subsequent to these initial steps, as described above, the manufacturing steps for each device are advanced.
[0041]
Another important step in this process is the use of local implantation to create the required supply layer for buried channel devices. In a MOSFET structure, the activation of the channel produces a large vertical electric field that brings carriers to the surface. The band offset between Si and SiGe that keeps electrons in the buried strained Si layer is not large enough to prevent carriers from being pulled out of the buried channel. Thus, first, the buried channel MOSFET will appear to be disabled. However, if there is sufficient charge on the top SiGe layer, the MOSFET will be a depletion mode device, ie, a device that is normally on and requires a bias to turn off the channel. In a surface / buried channel device platform, the supply layer implant can be manufactured in the region where the buried channel is formed, thus facilitating the integration process. If for some reason feed layer implantation is not possible, dopants can be introduced into the top SiGe layer during epitaxial growth, thus creating a surface channel above the buried Si layer as shown in FIG. Note that the process is an acceptable process. The supply layer is then removed from the surface channel MOSFET region once the uppermost SiGe and strained Si layers have been removed by selective etching.
[0042]
In the steps described with reference to FIGS. 10, 12, and 13, it is considered desirable to manufacture a buried channel MOSFET. If the oxide of the buried channel device is removed, a buried channel device with a metal gate (called MODFET or HEMT) can be formed. The advantage of this device is that the transconductance can be higher because the lack of oxide reduces the capacitance. However, there are two disadvantages when using this device. First, all thermal processes after gate definition must be very cold, otherwise the metal will react with the semiconductor and have very low or no barrier alloys A gate is formed. In this connection, there is a second disadvantage. Due to the low heat supply, formation and contact of the source and drain are typically performed prior to gate definition. This reversal of the steps increases the series resistance between the gate and the source and between the gate and the drain because self-alignment of the gate with the source and the drain is hindered. Thus, by utilizing a carefully designed buried channel MOSFET, the self-aligned characteristics can be a significant advantage in device performance. Another benefit of the MOSFET structure is that the gate leakage is very low.
[0043]
Combinations of buried n-channel structures with n-type and p-type surface channel MOSFETs have been of great importance. It has also been emphasized that in buried n-channel and surface channel devices, it is important that the channel need not be pure Si. Si _ly Ge _y Channels can be used to increase stability during the manufacturing process. Figures 14A and 14B show relaxed Si _1-z Ge _z Si on layer 1404 _1-y Ge _y FIG. 2 schematically illustrates a surface 1400 and embedded 1450 channel device utilizing a channel 1402. A post-siliconization device is shown, including a poly-Si gate 1410, a gate oxide 1408, a silicide region 1412, a spacer 1414, and a doped region 1416. In the surface channel device 1400, a thin layer of Si 1406 is deposited to form the gate oxide 1408, as described above for the buried channel. _1-y Ge _y Must be deposited on layer 1402. Embedded Si _1-y Ge _y In the channel device 1450, the order of the device layers does not change and includes a buried strain channel 1402, a SiGe spacer layer 1418, and a surface Si layer 1420 for oxidation.
[0044]
To maintain tensile strain in the channel of an nMOS device, the lattice constant of the channel layer must be smaller than that of the relaxed SiGe layer, ie, y must be less than z. Since n-channel devices are sensitive to alloy scattering, the highest mobility results when the Ge concentration in the channel is low. In order to distort this channel layer at a reasonable critical thickness, the underlying SiGe should have a Ge concentration in the range of 10-50%.
[0045]
Experimental data has shown that the p-channel has little sensitivity to alloy scattering. Thus, surface MOSFETs with alloy channels are also possible. In addition, the buried channel device is simply a p-channel device by increasing the Ge concentration y in the channel to be greater than the Ge concentration z in the relaxed SiGe alloy and changing the supply dopant from n-type to p-type. be able to. This arrangement can be used to form a Ge channel device when y = 1 and 0.5 <z <0.9.
[0046]
The ability to mix enhancement mode surface channel devices (implanted n-channel and p-channel, as in typical Si COMS technology) with depletion mode buried channel MOSFETs and MODFETs allows for highly integrated digital / Analog systems can be formed. Enhancement mode devices can be fabricated in high performance CMOS, and areas of analog circuitry requiring high performance, low noise depletion mode devices can be fabricated in the buried channel region. Therefore, it is possible to construct optimal communication stages, digital processing stages, and the like on a single platform. These different areas are electrically connected to the back end of the Si CMOS chip, just as the transistors are connected by today's back-end technology. Thus, a mere change to the COMS manufacturing process is only a change in some parameters of the manufacturing process in the manufacturing facility, and new materials, or the entire manufacturing process, are evident in the change. As such, such a platform for Si CMOS systems integrated on a chip is economically favorable.
[0047]
Although the present invention has been shown and described with reference to certain preferred embodiments, various changes, omissions, and additions to those forms and details can be made without departing from the spirit and scope of the invention. .
[Brief description of the drawings]
[0048]
FIG. 1 is a schematic block diagram of a structure including a relaxed SiGe layer epitaxially grown on a Si substrate.
FIG. 2 is a schematic block diagram of an exemplary structure showing that the crosshatch pattern is derived from a stress field due to implantation mismatch dislocations.
FIG. 3 is a table showing surface roughness data for a relaxed SiGe buffer created by dislocation injection through a graded SiGe layer on a Si substrate.
FIG. 4 illustrates an exemplary process flow and the resulting platform structure according to the present invention.
FIG. 5 is a schematic diagram illustrating a corresponding process flow and layer structure for a surface channel FET platform according to the present invention.
FIG. 6 is a schematic diagram illustrating a corresponding process flow and layer structure for a buried channel FET platform according to the present invention.
FIG. 7A is a schematic diagram illustrating a process flow for a surface channel MOSFET according to the present invention.
FIG. 7B is a schematic diagram illustrating a process flow for a surface channel MOSFET according to the present invention.
FIG. 7C is a schematic diagram illustrating a process flow for a surface channel MOSFET according to the present invention.
FIG. 7D is a schematic diagram illustrating a process flow for a surface channel MOSFET according to the present invention.
FIG. 8A is a schematic block diagram illustrating a surface channel device having a protective layer.
FIG. 8B is a schematic block diagram illustrating a surface channel device having a protective layer.
FIG. 9A is a schematic block diagram illustrating a surface channel device having a Si layer on a Ge rich layer for use in silicide formation.
FIG. 9B is a schematic block diagram illustrating a surface channel device having a Si layer on a Ge-rich layer for use in silicide formation.
FIG. 10 is a schematic diagram showing a buried channel MOSFET after device isolation according to the present invention.
FIG. 11 is a schematic process flow diagram for a heterostructure FET device deposited on relaxed SiGe, according to the present invention.
FIG. 12A is a schematic process flow diagram for forming a surface channel MOSFET on the uppermost strained Si layer according to the present invention.
FIG. 12B is a schematic process flow diagram for forming a surface channel MOSFET on the uppermost strained Si layer according to the present invention.
FIG. 12C is a schematic process flow diagram for forming a surface channel MOSFET on the uppermost strained Si layer according to the present invention.
FIG. 12D is a schematic process flow diagram for forming a surface channel MOSFET on the uppermost strained Si layer according to the present invention.
FIG. 13A is a schematic process flow diagram for forming a surface channel MOSFET in a buried strained Si layer according to the present invention.
FIG. 13B is a schematic process flow diagram for forming a surface channel MOSFET in a buried strained Si layer according to the present invention.
FIG. 13C is a schematic process flow diagram for forming a surface channel MOSFET in a buried strained Si layer according to the present invention.
FIG. 13D is a schematic process flow diagram for forming a surface channel MOSFET in a buried strained Si layer according to the present invention.
FIG. 14A: Si _ly Ge _y Relaxed using Si _lz Ge _z FIG. 2 is a schematic diagram illustrating a surface channel device built on a layer.
FIG. 14A: Si _ly Ge _y Relaxed using Si _lz Ge _z FIG. 2 is a schematic diagram illustrating a buried channel device built on a layer.

Claims (48)

A planarization moderating Si _1-x Ge _x layer on a substrate, and
A device heterostructure comprising at least one strained layer deposited on said planarization relaxed Si _1-x Ge _x layer;
A semiconductor structure comprising: The structure of claim 1, wherein the strained layer comprises Si _1-y Ge _y where y <x. Structure according to claim 1, wherein the strained layer comprises Si _1-y Ge _y is a y> x. The structure of claim 1 including the device heterostructure, Si _1-z Ge _z layer equal to z approximately x, Si _1-y Ge _y layer is y <x, and a layer of Si. The structure of claim 1 including the device heterostructure, Si _1-z Ge _z layer equal to z approximately x, Si _1-y Ge _y layer is y> x, and a layer of Si. It said device heterostructure has the structure according to claim 1 comprising a layer of equal to z is approximately x Si _1-z Ge _z layer and Si. 6. The structure according to claim 5, wherein y is approximately 1. 7. The structure of claim 6, wherein both x and z are greater than 0.1 and less than or equal to 0.5. 9. The structure according to claim 8, wherein said Si layer is thinner than 0.1 μm. 8. The structure according to claim 7, wherein both x and z are greater than 0.5 and less than or equal to 0.9. 11. The structure according to claim 10, wherein said Si layer is thinner than 0.005 µm. Said device heterostructure, z is approximately Si _1-z Ge _z layer is equal to x, y <second Si _1-y Ge _y layer is x, w equals approximately x third Si _1-w Ge _2. The structure according to claim 1, comprising a _w layer and a layer of Si. 13. The structure of claim 12, wherein said y is approximately zero. 14. The structure according to claim 13, wherein 0.1 <x <0.5 and the thickness of the second Si _1-y Ge _y layer is less than 0.05 μm. 15. The structure of claim 14, wherein the layer of Si is thinner than 0.005 μm. The device heterostructure has a Si _1-z Ge _z layer where z is approximately equal to x, a second Si _1-y Ge _y layer where y> x, a third Si _1-w Ge layer where w is approximately equal to x. _2. The structure according to claim 1, comprising a _w layer and a layer of Si. 17. The structure of claim 16, wherein said y is approximately one. 18. The structure according to claim 17, wherein 0.5 <x <0.9 and the thickness of the second Si _1-y Ge _y layer is less than 0.05 μm. 19. The structure of claim 18, wherein said layer of Si is less than 0.005 [mu] m. 2. The structure according to claim 1, wherein the substrate includes a composition gradient relaxation SiGe layer on Si. 2. The structure according to claim 1, wherein the substrate is made of Si. 22. The structure according to claim 21, wherein said relaxed SiGe / Si structure is formed by wafer bonding. _2. The structure of claim 1, wherein said substrate comprises Si having a layer of SiO2. The structure of claim 23 wherein said relaxed SiGe / SiO ₂ / Si structure is formed by wafer bonding. Providing a relaxed Si _1-x Ge _x layer on the substrate,
Planarizing the relaxed Si _1-x Ge _x layer; and
Depositing a heterostructure on said planarized relaxed Si _1-x Ge _x layer comprising at least one strained layer;
A method for manufacturing a semiconductor structure including: The method of claim 25 wherein the strained layer comprises Si _1-y Ge _y is y <x. The method of claim 25, wherein the strained layer comprises Si _1-y Ge _y is a y> x. The heterostructure, _z Si _1-z Ge z layer is equal to approximately x, A method according to claim 25 comprising a layer of a _{y <x Si 1-y Ge} y layer and Si. The heterostructure, Si _1-z Ge _z layer equal to z approximately x, A method according to claim 25 comprising a layer of a _{y> x Si 1-y Ge} y layer and Si. The heterostructure The method of claim 25 comprising a layer of equal to z is approximately x Si _1-z Ge _z layer and Si. 30. The method of claim 29, wherein y is approximately one. 31. The method of claim 30, wherein both x and z are greater than 0.1 and less than or equal to 0.5. 33. The method of claim 32, wherein the layer of Si is less than 0.1 [mu] m. 32. The method of claim 31, wherein both x and z are greater than 0.5 and less than or equal to 0.9. 35. The method of claim 34, wherein said layer of Si is less than 0.005 [mu] m. The heterostructure comprises a Si _1-z Ge _z layer in which z is approximately equal to x, a second Si _1-y Ge _y layer in which y <x, a third Si _1-w Ge _w layer in which w is approximately equal to x. 26. The method of claim 25, comprising a layer and a layer of Si. 37. The method of claim 36, wherein y is approximately zero. 0.1 <x in <0.5, and a second Si _1-y Ge method of claim 37 thickness _y layer is less than 0.05 .mu.m. 39. The method of claim 38, wherein said layer of Si is less than 0.005 [mu] m. The heterostructure comprises a Si _1-z Ge _z layer in which z is approximately equal to x, a second Si _1-y Ge _y layer in which y> x, a third Si _1-w Ge _{w in which} w is approximately equal to x. 26. The method of claim 25, comprising a layer and a layer of Si. 41. The method of claim 40, wherein y is approximately 1. 42. The method according to claim 41, wherein 0.5 <x <0.9 and the thickness of the second Si _1-y Ge _y layer is less than 0.05 μm. 43. The method of claim 42, wherein said layer of Si is less than 0.005 [mu] m. 26. The method of claim 25, wherein said substrate comprises a compositionally graded SiGe layer on Si. The method according to claim 25, wherein the substrate is made of Si. 46. The method of claim 45, wherein said relaxed SiGe / Si structure is formed by wafer bonding. Said substrate, The method of claim 25 consisting of Si with a layer of SiO _2. The method of claim 47, wherein the relaxed SiGe / SiO ₂ / Si structure is formed by wafer bonding.

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