JP2004526295A - Trench gate Fermi threshold field effect transistor and method of manufacturing the same - Google Patents

Abstract

The field effect transistor includes a semiconductor substrate of a first conductivity type having a surface. A tub region of the second conductivity type is at a surface within the semiconductor substrate and extends into the semiconductor substrate from the first surface to a first depth. A second conductivity type spaced source and drain region is included on the surface of the second conductivity type tub region and, together with the second conductivity type tub region, is a single conductivity type second conductivity type tab region. Form a bond. These spaced source and drain regions extend into the tub region to a second depth that is less than the first depth. The trench is included in the tub region between the spaced source and drain regions and extends from the surface into the tub region to a third depth greater than the second depth but less than the first depth. . An insulated gate electrode is included in the trench. Source and drain electrodes in electrical contact with the source and drain regions, respectively, are provided on the surface. These field effect transistors are fabricated in a semiconductor substrate of a first conductivity type by forming, at one surface, a tab region of a second conductivity type extending from the surface to a first depth in the semiconductor substrate. You. A source / drain region of the second conductivity type is formed on the surface of the tab region of the second conductivity type to form a single conductive junction of the second conductivity type with the tab region of the second conductivity type. . The source / drain regions extend into the tub region to a second depth that is less than the first depth. A trench is formed in the source / drain region to form spaced source and drain regions therefrom. The trench extends from the surface into the tub region to a third depth that is greater than the second depth but less than the first depth. An insulated gate electrode is formed in the trench. Source and drain electrodes in electrical contact with the source and drain regions, respectively, are formed on the surface.

Description

ここで、Ｎ_dはタブ領域のドーピング濃度、Ｎ_aは半導体基板のドーピング濃度、Ｎ_iは温度Ｔケルビンにおける基板の固有のキャリア濃度、ε_sは基板の誘電率、ｑは１．６ｘ１０^-19クーロン、及びｋは１．８３ｘ１０^-23ジュール／ケルビンである。
【００３５】
前述した全ての実施形態における半導体基板は、実質的には、前記表面において、それ自体が第２の導電型の半導体基板の中にあり、第２の導電型のタブ領域が、その表面において、第１の導電型の井戸領域の中にあり、表面から第１の深さまで井戸領域内に延びるような、第１の導電型の井戸領域とすることができる。
【００３６】
さらに、前述した全ての半導体基板では、絶縁されたゲート電極はトレンチ内の、表面から凹ませることができる。いくつかの実施形態では、絶縁されたゲート電極は、電界効果トランジスタ内のドレイン電流を減少させずに、絶縁されたゲート電極と間隔を空けたソース及びドレイン領域との間の容量を最小にする量だけ、表面から凹まされる。
【００３７】
さらに別の実施形態では、半導体基板は第１のドーピング濃度の第１の導電型にドープされ、タブ領域は第２のドーピング濃度の第２の導電型にドープされる。第１、第２及び第３の深さ並びに第１及び第２のドーピング濃度の少なくともいずれかは、前述した実施形態のいずれかに基づいて選択される。
【００３８】
電界効果トランジスタは、第１の導電型の半導体基板の中に、ある表面おいて、半導体基板内に表面から第１の深さまで延びる第２の導電型のタブ領域を形成することによって、本発明の実施形態に基づいて製造される。第２の導電型のソースまたはドレイン領域は、第２の導電型のタブ領域の表面に形成され、第２の導電型のタブ領域との第２の導電型の単一の導電接合を形成する。ソースまたはドレイン領域は、第１の深さよりも浅い第２の深さまでタブ領域の中に延びる。トレンチがソースまたはドレイン領域の中に形成されて、そこから間隔を空けたソース及びドレイン領域を形成する。このトレンチは、第２の深さよりも深いが第１の深さよりも浅い第３の深さまで表面からタブ領域の中に延びる。絶縁されたゲート電極がトレンチの中に形成される。ソース及びドレイン領域にそれぞれ電気的に接触するソース及びドレインの電極が表面上に形成される。
【００３９】
別の実施形態では、ソースまたはドレイン領域は、タブ領域を形成する前に形成される。さらに別の実施形態では、トレンチは、ソースまたはドレイン領域及びタブ領域を形成した後で形成される。さらに別の実施形態では、絶縁されたゲート電極は、ソース及びドレインの電極を形成する前に形成される。前述した全ての方法の実施形態では、第１、第２及び第３の深さ及び／又は第１及び第２のドーピング濃度は、前述した構造上の実施形態のいずれかの中で説明されたように選択される。さらに、前述したように、第１の導電型の井戸領域は第２の導電型の半導体基板に中に形成され、第２の導電型のタブ領域は第１の導電型の井戸領域の中に形成される。最後に、前述したように、絶縁されたゲート電極は表面から凹まされる。
【００４０】
これらの方法の実施形態では、ソースまたはドレイン領域は、第２の導電型のイオンを大きな傾斜角で半導体基板内に注入することによって形成される。これにより、浅いソースまたはドレイン領域を作ることができるが、ゲート電極はソースまたはドレイン領域を作った後で形成されるため、位置合わせ不良の原因にはならない。このため、ゲート電極は、ソースまたはドレインの注入を遮るように作用することはない。さらに、絶縁されたゲート電極は、トレンチを絶縁層で被覆し、ゲート電極を絶縁層で被覆したトレンチの中に形成することによって形成される。ゲート電極は、ゲート電極層を基板上及びトレンチ内に形成し、ゲート電極層を平坦化してゲート電極層を表面から取り除くことによって形成される。平坦化に続いて、ゲート電極が表面から凹まされる。
【００４１】
トレンチの（第３の）深さは、トレンチゲート形フェルミＦＥＴの電界効果トランジスタを形成し、そのパラメータを測定することによって決定される。さらに、トレンチの深さはシミュレーションによって決定することができる。実験的な方法を使用して、タブ領域及びその中にソースまたはドレイン領域を有する一連のサイト上の一連の容量対電圧の測定値を求めることによって、本発明の実施形態によるトレンチの深さを決定することもできる。この場合、ソースまたはドレイン領域の異なる量が、一連のサイトにおいてエッチングされる。これらのサイトは、単一のウエハ又は複数のウエハ上に置くことができる。トレンチの深さは、最大の容量を負電圧で得ることができる最大深さを求めることによって決定することができる。
【発明を実施するための最良の形態】
【００４２】
［好ましい実施形態の詳細な説明］
本発明の好ましい実施形態が示されている添付の図面を参照しながら、本発明を以下のようにより完全に説明する。しかしながら、本発明は多くの異なった形態で具体化することができるが、本願に記載された実施形態に限定されると解釈してはならない。むしろ、この開示が詳細で完全であり、また発明の範囲を当業者に十分に伝えるように、これらの実施形態が提供される。図面では、層及び領域の厚さは明快にするため誇張されている。全体を通して、同じ番号は同様の素子を指している。層、領域又は基板などのある要素が別の要素の「上に」あると言われる場合、その要素は別の要素の直接上にあるか、又は介在する要素が存在することもあることは理解されよう。その一方で、ある要素が別の要素の「直接上に」あると言われる場合は、介在する要素は存在しない。
【００４３】
本発明のトレンチゲート形フェルミしきい値電界効果トランジスタを説明する前に、米国特許第５，１９４，９２３号及び５，３６９，２９５号のゲート容量及び拡散容量を減少させたフェルミしきい値電界効果トランジスタ（「低容量フェルミＦＥＴ」又は「タブＦＥＴ」と呼ぶことがある）を、米国特許第５，３７４，８３６号の大電流フェルミしきい値電界効果トランジスタとして説明する。米国特許第５，５４３，６５４号による形状付けられたタブ形フェルミＦＥＴも説明する。米国特許第５，８１４，８６９号の短チャネル形フェルミＦＥＴも説明する。米国特許第５，６９８，８８４号のバイナルＦＥＴも説明する。公開されたＰＣＴ出願第ＷＯ９９／１７３７１号の金属ゲート形フェルミＦＥＴも説明する。一層完全な説明がこれらの特許及び特許出願の中で見出される。これらの開示内容は、引用することにより本願の一部をなすものとする。本発明の実施形態によるトレンチゲート形フェルミＦＥＴを、次ぎに説明する。
【００４４】
［ゲート容量及び拡散容量を減少させたフェルミＦＥＴ］
以下に、フェルミタブを含む低容量形フェルミＦＥＴを要約する。これ以上の詳細は、米国特許第５，１９４，９２３号及び５，３６９，２９５号の中で見つけることができる。
【００４５】
従来のＭＯＳＦＥＴ装置は、キャリアの伝導を支援するために、反転層を半導体の表面に作る必要がある。反転層の深さは、一般に、１００Å未満である。これらの状況のもとでは、ゲート容量は本質的に、その厚さで除算されたゲート絶縁体層の誘電率である。言い換えると、チャネルの電荷は表面に非常に近いので、基板の誘電特性の影響はゲート容量を決定する上で重要ではない。
【００４６】
伝導キャリアがゲートの下のチャネル領域内に閉じ込められる場合は、ゲート容量を低下させることができる。この場合、チャネル電荷の平均深さは、ゲート容量を計算するためには基板の誘電率を算入する必要がある。一般に、低容量形フェルミＦＥＴのゲート容量は、次の式によって表される。
【数５】

ここで、Ｙ_fはフェルミチャネルと呼ばれる伝導チャネルの深さ、ε_sは基板の誘電率、またβは基板の下のフェルミチャネルの中を流れる電荷の平均深さを決定する係数である。βは、ソースからチャネルに注入されるキャリアの深さに依存するプロフィールに左右される。低容量形フェルミＦＥＴについては、βはほぼ２である。Ｔ_oxはゲートの酸化被膜の厚さであり、ε_iは誘電率である。
【００４７】
低容量形フェルミＦＥＴは、導電型が基板の導電型と反対でドレイン及びソース領域の導電型と同じの、所定の深さのフェルミタブ領域を含む。このフェルミタブは、基板表面から所定の深さだけ下向きに延び、ドレイン及びソースの拡散部はフェルミタブ領域の中のフェルミタブ境界内に形成される。好ましいフェルミタブの深さは、フェルミチャネルの深さＹ_fと空乏深さＹ₀との合計である。所定の深さＹ_f及び幅Ｚのフェルミチャネル領域は、ソース及びドレインの拡散部の間を延びる。フェルミチャネルの導電率は、ゲート電極に印加される電圧によって制御される。
【００４８】
ゲート容量は、フェルミチャネルの深さ及びフェルミチャネル内のキャリア分布によって決定され、ゲートの酸化被膜の厚さには比較的無関係である。拡散容量は、逆に、フェルミタブの深さ及び基板内の空乏深さＹ₀の合計の深さと拡散部Ｘ_dの深さとの間の差に依存する。拡散深さは、フェルミタブの深さＹ_Tよりも浅いことが好ましい。フェルミタブ領域に対するドーパント濃度は、フェルミチャネルの深さをＭＯＳＦＥＴ内の反転層の深さの３倍よりも大きくできるように選択することが好ましい。
【００４９】
従って、低容量形フェルミＦＥＴは、第１の表面を有する第１の導電型の半導体基板、この基板内の第１の表面に第２の導電型のフェルミタブ領域、フェルミタブ領域内の第１の表面に第２の導電型の間隔を空けたソース及びドレイン領域、及びフェルミタブ領域内の間隔を空けたソース及びドレインの領域の間に第２の導電型のチャネルを含む。このチャネルは、第１の表面から第１の所定の深さ（Ｙ_f）まで延び、タブはチャネルから第２の所定の深さ（Ｙ₀）まで延びる。基板上の間隔を空けたソース及びドレインの領域間の第１の表面に、ゲート絶縁層を設ける。それぞれ、ソース領域、ドレイン領域及びゲート絶縁層と電気的に接触するソース、ドレイン及びゲートの電極を設ける。
【００５０】
少なくとも第１及び第２の所定の深さは、電界効果トランジスタのしきい値電圧をゲート電極に加える場合、第１の深さにおいて第１の表面に垂直な静電界がゼロになるように選択される。第１及び第２の所定の深さは、また、電界効果トランジスタのしきい値電圧を超える電圧をゲート電極に加える場合、第２の導電型のキャリアが第１の所定の深さから第１の表面に向かって延びるチャネル内を、ソースからドレインに流れることができるように選択される。キャリアは、フェルミタブ領域の中に反転層を作らずに、第１の表面の下側をソース領域からドレイン領域に流れる。第１及び第２の所定の深さは、また、基板接点と基板との間及びポリシリコンのゲート電極とゲート電極との間の電圧の合計に等しく極性が逆の電圧を、ゲートの絶縁層に隣接する基板表面に発生するように選択される。
【００５１】
基板がドーピング濃度Ｎ_sでドープされ、温度Ｔケルビンで固有のキャリア濃度ｎ_iを有し、また誘電率ε_sを有し、電界効果トランジスタが基板と電気的に接触するための基板接点を含み、チャネルが基板の表面から第１の所定の深さＹ_fまで延び、フェルミタブ領域がチャネルから第２の所定の深さＹ₀まで延び、フェルミタブ領域が係数α掛けるＮ_sのドーピング濃度でドープされ、またゲート電極が第１の導電型のポリシリコンの層を含むと共にドーピング濃度Ｎ_pでドープされる場合、第１の所定の深さ（Ｙ_f）は、次の式で示される。
【数６】

ここで、ｑは１．６ｘ１０^-19クーロンであり、Ｋは１．３８ｘ１０^-23ジュール／ケルビンである。第２の所定の深さは、次の式に等しい。
【数７】

ここで、φ_sは２φ_f＋ｋＴ／ｑＬｎ（α）であり、φ_fは半導体基板のフェルミ電位である。
【００５２】
［大電流形フェルミＦＥＴの構造］
ここで図１を参照すると、米国特許第５，３７４，８３６号によるＮチャネルの大電流形フェルミＦＥＴが図示されている。当業者は、Ｎ及びＰの領域の伝導性を逆にすることによって、ＰチャネルのフェルミＦＥＴを得ることができることは理解されよう。
【００５３】
図１に示すように、大電流形フェルミＦＥＴ２０は、この図ではＰ型の第１の導電型であり、基板表面２１ａを含む半導体基板２１の中に製造される。この図ではＮ型の第２の導電型のフェルミタブ領域２２が、基板２１内の表面２１ａに形成される。この図ではＮ型で第２の導電型の、それぞれ間隔を空けたソース及びドレイン領域２３及び２４が、フェルミタブ領域２２の中の表面２１ａに形成される。当業者は、ソース及びドレイン領域は表面２１ａ内のトレンチにも形成できることは理解されよう。
【００５４】
ゲート絶縁層２６が、基板２１上の、それぞれ間隔を空けたソース及びドレインの領域２３及び２４の間の表面２１ａに形成される。当業者は周知のように、このゲート絶縁層は一般に、二酸化ケイ素である。しかしながら、窒化ケイ素や他の絶縁体も使用することができる。
【００５５】
ゲート電極が、基板２１の反対側のゲート絶縁層２６の上に形成される。このゲート電極は、ここではＰ型の第１の導電型の多結晶シリコン（ポリシリコン）のゲート電極層２８を含むことが好ましい。導電体のゲート電極層、一般に、金属のゲート電極層２９が、ゲート絶縁層２６の反対側のポリシリコンのゲート電極２８の上に形成される。一般に金属のソース電極３１及びドレイン電極３２も、それぞれソース領域２３及びドレイン領域２４上に形成される。
【００５６】
ここではＰ型の第１の導電型の基板接点３３も、基板２１内の、図示のようにフェルミタブ２２の内部又はタブ２２の外部のいずれかに形成される。図示のように、基板接点３３は、ここではＰ型の第１の導電型にドープされ、比較的高度にドープされた領域３３ａ及び比較的軽度にドープされた領域３３ｂを含む。基板電極３４は、基板との電気的な接触を確立する。
【００５７】
これまで図１を参照して説明した構造体は、米国特許第５，１９４，９２３号及び５，３６９，２９５号の低容量形フェルミＦＥＴの構造体に対応する。これらの応用例の中ですでに説明したように、チャネル３６がソース領域２３とドレイン領域２４との間に作られる。図１ではＹ_fで示した、表面２１ａからのチャネル深さ、及び図１ではＹ₀で示したチャネルの底部からフェルミタブ２２の底部までの深さ、並びに基板２１、タブ領域２２、及びポリシリコンのゲート電極２８のドーピングレベルは、前記の式（１）及び式（２）の関係を用いる高性能で低容量の電界効果トランジスタを提供するように選択される。
【００５８】
さらに図１を参照すると、ここではＮ型の第２の導電型のソース注入領域３７ａが、ソース領域２３に隣接しドレイン領域に向けて設けられる。このソース注入領域は、キャリアをチャネル３６に注入する深さを制御することによって、大電流のフェルミＦＥＴを提供する。ソース注入領域３７ａは、ソース領域２３とドレイン領域２４との間のみに延びる。ソース注入領域は、図１に示すように、ソース領域２３を囲んで、ソース注入タブ領域３７を形成することが好ましい。ソース領域２３の側面及び底面は、ソース注入タブ領域３７によって完全に囲まれる。別の方法では、ソース領域２３は側面がソース注入タブ領域３７によって囲まれるが、底部はソース注入タブ領域３７から突き出ている。さらに別の方法では、ソース注入領域３７ａは、基板２１内の、フェルミタブ２２と基板２１との間の接合部まで延びる。ドレイン注入領域３８ａ、好ましくはドレイン領域２４を囲むドレイン注入タブ領域３８も設ける。
【００５９】
ソース注入領域３７ａ及びドレイン注入領域３８ａ又はソース注入タブ領域３７及びドレイン注入タブ領域３８は、フェルミタブ２２の比較的低いドーピングレベルとソース２３及びドレイン２４の比較的高いドーピングレベルとの中間のドーピングレベルで、ここではＮ型の第２の導電型にドープされることが好ましい。このため、図１に示すように、フェルミタブ２２はＮとして示され、ソース及びドレインの注入タブ領域３７，３８はＮ⁺と示され、またソース及びドレイン領域２３，２４はＮ⁺⁺と示される。これにより、ユニジャンクショントランジスタが形成される。
【００６０】
大電流形フェルミＦＥＴは、従来のＦＥＴの約４倍の駆動電流を提供する。ゲート容量は、従来のＦＥＴ装置の約半分である。ソース注入タブ領域３７のドーピング濃度は、チャネル領域３６の中に注入されるキャリアの深さを一般に約１０００オングストローム（１００ｎｍ）に制御する。ソース注入タブ領域３７のドーピング濃度は一般に２Ｅ１８（２×１０¹⁸）であり、注入された多数キャリアの望ましい最大幅と少なくとも同じ幅を有することが好ましい。別の方法では、後で説明するが、それはフェルミタブ領域２２と同じ深さまで延びて、しきい値以下の漏洩電流を最小にする。チャネル３６に注入されたキャリア濃度は、ドレインに面するソース注入領域３７ａのドーピング濃度を超えることはできないことが示されるであろう。ソース注入領域３７ａのドレインに面する部分の幅は、一般に、０．０５〜０．１５μmの範囲である。ソース及びドレイン領域２３及び２４のドーピング濃度は、それぞれ、一般に１Ｅ１９（１×１０¹⁹）以上である。フェルミタブ２２の深さＹ_T＝（Ｔ_f＋Ｙ₀）は、約２２００Åであり、ドーピング濃度は約１．８Ｅ１６（１．８×１０¹⁶）である。
【００６１】
図１に示すように、大電流形フェルミＦＥＴ２０は、基板表面２１ａ上に隣接するソース注入領域３７ａから隣接するポリシリコンのゲート電極２８まで延びるゲート側壁スペーサ４１も含む。このゲート側壁スペーサ４１は、好ましいことに、隣接するドレイン注入領域３８ａから隣接するポリシリコンのゲート電極２８にも延びる。特に、図１に示すように、ゲート側壁スペーサ４１は、ポリシリコンのゲート電極の側壁２８ａから延びて、それぞれソース及びドレインの注入領域３７ａ及び３８ａの上に重なる。ゲート側壁スペーサ４１が、ポリシリコンのゲート電極２８を取り巻くことが好ましい。また好ましくは、後で詳細に説明するように、ゲート絶縁層２６は、基板表面２１ａのソース注入領域３７ａ及びドレイン注入領域３８ａ上に延び、ゲート側壁スペーサ４１もソース注入領域３７及びドレイン注入領域３８上に延びる。
【００６２】
ゲート側壁スペーサ４１は、後で詳細に説明するような方法で、フェルミＦＥＴ２０のピンチオフ電圧を低下させ、その飽和電流を増加させる。ゲート側壁スペーサは、ゲート絶縁層２６の誘電率よりも大きい誘電率を有する絶縁体であることが好ましい。このため、例えば、ゲート絶縁層２６が二酸化ケイ素である場合は、ゲート側壁スペーサは窒化ケイ素であることが好ましい。ゲート側壁スペーサ２６が窒化ケイ素である場合は、ゲート側壁スペーサは誘電率が窒化ケイ素よりも大きい絶縁体であることが好ましい。
【００６３】
図１に示すように、ゲート側壁スペーサ４１はそれぞれソース及びドレインの領域２３及び２４の上にも延び、それぞれソース及びドレインの電極３１及び３２はゲート側壁スペーサ領域の延長部の中に形成される。従来のフィールド酸化膜又は他の絶縁体４２の領域は、ソース、ドレイン及び基板接点を分離する。当業者は、ゲート側壁スペーサ４１の外面４１ａが断面では曲線で図示されているが、三角形の断面を生じる直線の外面又は長方形の断面を生ずる直交する外面などの他の形状も使用できることも理解されよう。
【００６４】
［低漏洩電流形フェルミ電界効果トランジスタ］
ここで図２Ａ及び図２Ｂを参照する。米国特許第５，３７４，８３６号による短チャネルであるが漏洩電流が少ないフェルミＦＥＴをここで説明する。これらの装置を以後「低漏洩電流形フェルミＦＥＴ」と呼ぶ。図２Ａの低漏洩電流形フェルミＦＥＴ５０は、この図ではＰ型で基板２１に対して高い濃度でドープされた、第１の導電型の底部漏洩電流制御領域５１を含む。このため、それは図２ＡではＰ⁺と図示される。図２Ｂの低漏洩電流形フェルミＦＥＴ６０は、延びたソース及びドレインの注入領域３７ａ，３８ａを含む。これらの注入領域は、フェルミタブ２２の深さまで延びることが好ましい。
【００６５】
ここで図２Ａを参照すると、底部漏洩電流制御領域５１は、ソース及びドレイン領域２３及び２４の対面する端部の延長部の間から基板２１を横切って延び、またフェルミタブ２２の深さの上からフェルミタブの深さの下まで基板の中に延びる。それは、フェルミチャネル３６の下側でフェルミチャネル３６と整列して配置されることが好ましい。前に記載した式との一貫性を保つために、フェルミチャネル３６から底部漏洩電流制御領域５１の上部までの深さは、Ｙ₀と記されている。図２ＡのフェルミＦＥＴトランジスタの残りは、チャネルが短く示されていることを除いて、図１に記載したものと同じである。図２Ａの装置の大電流特性を有しない、漏洩電流が少なく容量が小さい短チャネル形フェルミＦＥＴを提供するには、注入領域３７ａ及び３８ａ及び／又は注入タブ３７及び３８並びにゲート側壁スペーサ領域４１を省略できることは、当業者は理解されよう。
【００６６】
底部漏洩電流制御領域５１は、拡散空乏容量を低く維持しながら、短チャネル形フェルミ電界効果トランジスタ、すなわちチャネル長が約０．５μm未満の電界効果トランジスタの中のドレイン誘導による注入を最小にする。例えば、５ボルトで、３Ｅ−１３Ａ（３×１０^-13Ａ）以下の漏洩電流が維持される。
【００６７】
底部漏洩電流制御領域は、式（２）及び式（３）を用いて設計される。ここで、Ｙ₀は、図２Ａ及び図２Ｂに示すように、チャネルから底部漏洩電流領域の上部までの深さである。係数αは、底部漏洩電流制御領域５１のＰ⁺ドーピングとフェルミタブ２２のＮドーピングとの間の比率である。底部漏洩制御領域の中、すなわちゲート２８の下側で、αを約０．１５に設定することが好ましい。ソース及びドレインの領域２３及び２４の下では、αは約１．０に設定されて、拡散空乏容量を最小にする。換言すると、基板２１及びフェルミタブ２２のドーピング濃度は、ソース及びドレインの下の領域にほぼ等しい。このため、前述した設計パラメータに対して、また０．５ミクロンのチャネル幅に対して、底部漏洩制御領域５１内のドーピング濃度は約５Ｅ１７（５×１０¹⁷）であり、ドレイン又はソースの拡散電位が５ボルトの場合、タブ接合領域における部分的な空乏に対応するように十分に深い。
【００６８】
ここで図２Ｂを参照する。底部漏洩制御に対する別の設計では、ソース注入領域３７ａ及びドレイン注入領域３８ａの深さが、好ましくはフェルミタブの深さ（Ｙ_f＋Ｙ₀）まで延びる。図２Ｂに示すように、ソース注入タブ３７及びドレイン注入タブ３８の全体の深さは、フェルミタブの深さまで延びることが好ましい。注入タブ３７及び３８の底部とフェルミタブ２２の底部との間の分離距離は、好ましくはチャネル長の半分未満、さらに好ましくはほぼゼロである。これらの状態のもとでは、注入タブ３７及び３８のドーピング濃度は、約１．５Ｅ１８／ｃｍ³（１．５×１０¹⁸／ｃｍ³）である。基板接点領域３３ｂの深さも、フェルミタブの深さに達するまで延長されることが好ましい。図２ＢのフェルミＦＥＴトランジスタ６０の残りは、チャネルが短く示されていることを除いて、図１に記載したものと同一である。
【００６９】
［形状付けられたタブ形フェルミしきい値電界効果トランジスタ］
ここで図３を参照すると、米国特許第５，５４３，６５４号によるＮチャネルの形状付けられたタブ形フェルミＦＥＴが図示されている。当業者は、Ｎ及びＰの領域の伝導性を逆にすることによって、ＰチャネルのフェルミＦＥＴを得ることができることは理解されよう。図３に示すように、形状付けられたタブ形フェルミＦＥＴ２０’は、タブ深さが均一な図１のタブ２２ではなく形状付けられたタブ２２’が存在することを除いて、図１の大電流形フェルミＦＥＴ２０と同様である。注入タブ及び注入領域は存在するが、図示されていない。
【００７０】
さらに図３を参照する。形状付けられたタブ２２’は、基板面２１ａからそれぞれ間隔を空けたソース及びドレインの領域２３，２４の少なくともいずれかの下までの第１の所定の深さＹ₁を有する。この形状付けられたタブ２２’は、基板面２１ａからチャネル領域３６の下までの第２の所定の深さＴ２を有する。本発明によれば、形状付けられたタブ２２’を作るように、Ｙ₂はＹ₁とは異なり、好ましくはＹ₁よりも小さい。別の方法で説明すると、タブ２２’と基板２１との間の接合部は、チャネルの下のタブＦＥＴ基準によって指示された位置に対応して、ソース及びドレインの領域２３及び２４から離れるように押し下げられて、ソースまたはドレインの拡散容量を減少させ、これにより、形状付けられたタブ形フェルミＦＥＴが低電圧で動作できるようにされる。タブ２２’はソース領域２３又はドレイン領域２４の下でのみ形状付けられて、非対称の装置を作ることは、当業者は理解されよう。しかしながら、タブがソース２３及びドレイン２４の下で形状付けられる対称的な装置も、好ましいことに形成される。
【００７１】
第２の所定の深さＹ₂は、米国特許第５，１９４，９２３号及び５，３６９，２９５号の低容量形フェルミＦＥＴ（タブＦＥＴ）の基準に基づいて選択される。深さＹ_f及びＹ₀を決定し共に第２の所定の深さＹ₂を形成するこれらの基準は、前に説明した。
【００７２】
第１の所定の深さ（Ｙ₁）は、第２の所定の深さＹ₂よりも大きくなるように選択される。第１の所定の深さは、ゼロの電圧がソース接点３１及びドレイン接点３２にそれぞれ印加される場合、第１の所定の深さＹ₁とソース領域及び／又はドレイン領域との間のタブ領域２２’を空乏化するように選択されることも好ましい。従って、Ｙ_nと記された領域全体が、好ましいことに、それぞれゼロのソースバイアス又はドレインバイアスのもとで全面的に空乏化される。この基準に基づいて、Ｙ₁は次の式によって決定される。
【数８】

ここで、Ｎ_subは基板２１のドーピング濃度であり、Ｎ_tubは形状付けられたタブ２２’のドーピング濃度である。
【００７３】
［短チャネル形フェルミＦＥＴ］
ここで図４を参照すると、米国特許第５，８１４，８６９号による短チャネルでＮチャネルのフェルミＦＥＴ２０”が示されている。当業者は、Ｎ及びＰの領域の伝導性を逆にすることによって、ＰチャネルのフェルミＦＥＴを得ることができることは理解されよう。図４に示すように、フェルミタブ２２”は、基板表面２１ａから第１の深さ（Ｙ_f＋Ｙ₀）に延びる。それぞれ間隔を空けたソース及びドレインの領域２３及び２４が、領域２３ａ及び２４ａで示すように、タブ領域の中に配置される。しかしながら、それぞれソースまたはドレインの領域２３及び２４は、さらに、基板表面２１ａからタブ深さを超えて延びる。ソースまたはドレインの領域２３及び２４は、基板表面２１ａに沿った方向にタブ領域を超えて横方向にも延びる。
【００７４】
チャネル深さＹ_f及びチャネルからのタブ深さＹ₀は、ゲート電極がしきい値電位のときに、基板表面から深さＹ_fへのチャネル３６内で基板表面に垂直な静電界を最小にするように選択される。すでに説明したように、これらの深さは、電界効果トランジスタに対して半導体基板２１のフェルミ電位の２倍のしきい値電圧を発生するように選択されることが好ましい。これらの深さは、電界効果トランジスタのしきい値電圧を超える電圧をゲート電極に印加すると、深さＹ_fから基板表面２１ａに向かって延びるチャネル領域内を第２の導電型のキャリアがソース領域からドレイン領域に流れることができるように選択される。キャリアはチャネル内に反転層を作ることなく、基板表面の下側をソース領域からドレイン領域のチャネル領域の中を流れる。従って、最適ではないが、図４の装置は、従来のＭＯＳＦＥＴトランジスタよりもはるかに大きい飽和電流を発生することができ、オフ状態のゲート容量を著しく減少させる。ドレイン容量は、標準的なＭＯＳＦＥＴ装置と同様になる。
【００７５】
図４では、ソースまたはドレイン領域が基板面２１ａに直交する深さ方向及び基板面２１ａに平行な横方向にタブ領域を超えて延びることは理解されよう。しかしながら、側壁の寄生容量を減少させるために、タブ２２”はソース及びドレイン領域を超えて横方向に延びて、ソース及びドレイン領域が深さ方向にタブを通って突き出るようにすることが好ましい。
【００７６】
ここで図５を参照すると、米国特許第５，８１４，８６９号による短チャネル形フェルミＦＥＴの第２の実施形態が示されている。トランジスタ２０”’は、ソース及びドレインの延長領域２３ｂ及び２４ｂがそれぞれ基板２１内の基板面２１ａにおいてそれぞれチャネル３６の中に延びるソース及びドレイン領域２３’及び２４’に隣接して設けられていることを除いて、図４のトランジスタ２０”と同様である。
【００７７】
図５に示すように、ソース及びドレインの延長領域２３ｂ及び２４ｂはそれぞれ、ソース及びドレイン領域２３’及び２４’とほぼ同じドーピング濃度に高度にドープ（Ｎ⁺⁺）される。延長部２３ｂ及び２４ｂが、従来のＭＯＳＦＥＴ装置の軽度にドープされたドレイン構造体のように軽度にドープされているのではないことは理解されよう。むしろ、それらをソース及びドレイン領域と同じドーピング濃度でドープし、漏洩を減少し飽和電流を増加するために、実用上できるだけ高度にドープすることが好ましい。
【００７８】
ソース及びドレインの延長領域２３ｂ及び２４ｂは、前述した電荷共有によりドレインの電圧感度を減少する。残念なことに、図５の装置は、通常、図１及び図２の完全に囲まれたソース及びドレイン領域のような低い容量を示さない。ソースまたはドレインの延長領域２３ｂ及び２４ｂの寸法を保つために、ソース及びドレイン自体に一般的に使用される軽く移動が早い素子ではなく、ヒ素又はインジウムのような重く移動が遅いドーパントをソース及びドレインの延長領域に用いることが好ましいことは、当業者は理解されよう。
【００７９】
［ドレインフィールドの終端を含む短チャネル形フェルミＦＥＴ］
本願ではバイナルＦＥＴとも呼ばれる、米国特許第５，６９８，８８４号による、ドレインフィールドの終端領域を含む短チャネルフェルミしきい値形電界効果トランジスタのアーキテクチャをここで説明する。Ｎ及びＰ領域の導電性を逆にすることによって、ＰチャネルのバイナルＦＥＴを得ることができることは、当業者は理解されよう。
【００８０】
図６及び図７は、それぞれバイナルＦＥＴの第１及び第２の実施形態を示す。図６に示すように、バイナルＦＥＴ６０は、この図ではＰ型の第１の導電型の半導体基板２１を含む。半導体基板２１はバルク半導体材料上に形成された１つ以上のエピタキシャル層をも含むため、基板表面２１ａは実際にバルク半導体材料の外面ではなくエピタキシャル層の外面であることは、当業者は理解されよう。
【００８１】
さらに図６を参照すると、第２の導電型（ここではＮ型）の第１のタブ領域６２が、基板２１上の表面２１ａに形成され、基板表面２１ａから第１の深さＹ₃に延びている。ここではＰ型の第１の導電型の第２のタブ領域６４が、第１のタブ領域６２の中に含まれる。この第２のタブ領域６４は、基板表面２１ａから第２の深さＹ₂まで基板の中に延びる。第２の深さＹ₂は、第１の深さＹ₃よりも浅い。第１のタブ領域６２の中の第２のタブ領域６４は、第１のタブ領域６２を超えて横方向にも延びる。第２のタブ領域６４は、後で説明するが、ドレインフィールド終端（ＤＦＴ）領域を形成する。ここではＮ型の第２の導電型の第３のタブ領域６６は、第２のタブ領域６４の中に含まれる。この第３のタブ６６は、基板表面から第３の深さＹ₁だけ基板２１の中に延びる。ここで、第３の深さＹ₁は第２の深さよりも浅い。第３のタブ６６は、後で説明するように、エピタキシャル層の中に形成されることが好ましい。
【００８２】
さらに図６を参照すると、第２の導電型（ここではＮ⁺）の、それぞれ間隔を空けたソース及びドレインの領域２３及び２４が、第１のタブ領域６２の中に形成され、基板表面２１ａから基板の中に第４の深さＹ₄まで延びている。図６に示すように、この第４の深さＹ₄は第３の深さＹ₁よりも深い。図６に示すように、第４の深さＹ₄は、第２の深さＹ₂よりも深いが、第１の深さよりも浅い。このため、それぞれソース及びドレインの拡散部２３及び２４は、それぞれ第３および第２のタブ６６及び６４を通り第１のタブ６２の中に延びる。図７に示すようなバイナルＦＥＴ６０’の第２の実施形態では、第４の深さＹ₄は第３の深さＹ₁よりも深いが第２の深さＹ₂よりも浅いため、ソース及びドレイン領域は第３のタブ６６を通って第２のタブ６４の中に延びるが、第１のタブ６２の中には入らない。
【００８３】
図６及び図７の、それぞれバイナルＦＥＴトランジスタ６０及び６０’は、ゲート絶縁層２６及びここではＰ型の第１の導電型の多結晶のシリコン層２８を含むゲート電極も含んでいる。ソース、ゲート及びドレインの接点３１，２９及び３２も、すでに説明したように含まれる。基板接点３４も含まれる。この基板接点は、表面２１ａの反対側に示されているが、前の実施形態のように、表面２１ａに隣接して設けることもできる。
【００８４】
図６及び図７のバイナルＦＥＴ６０及び６０’は、ソース領域２３とドレイン領域２４との間に延びる、基板２１内の層の観点から説明することもできる。この点で考察すると、第３のタブ６６は、基板の中の基板表面に、ソース領域２３からドレイン領域２４に延びると共に、基板表面から第１の深さＹ₁まで基板の中に延びる第２の導電型の第１の層６６ａを作る。第２のタブ６４は、ソース領域２３からドレイン領域２４に延び、また基板表面からの第１の深さＹ₁から第２の深さＹ₂まで基板の中に延びる第１の導電型の第２の層６４ａを基板内に作る。第２の層６４ａは、後で説明するように、ドレインフィールド終端手段として動作する。第１のタブ６２は、ソース領域からドレイン領域に延びまた基板表面からの第２の深さＹ₂から第３の深さＹ₃まで基板の中に延びる第２の導電型の第３の層６２ａを基板の中に作る。
【００８５】
このように観察すると、図６の実施形態では、第３の層６２ａは、領域６２ｂで示すように、ソース底部２３ａからドレイン底部２４ａまで延びる。図７の実施形態では、それぞれ第２及び第３の層６４ａ及び６２ａは、領域６４ｂ及び６２ｂで示すように、両方ともソース底部２３ａからドレイン底部２４ａまで延びる。
【００８６】
図６及び図７のバイナルＦＥＴは、もとのタブの中にコントラドープされ埋め込まれたタブ６４を含むタブＦＥＴとみなすこともできる。さらに別の方法では、バイナルＦＥＴは、チャネル領域６６ａの下側に第１の導電型の埋込層６４ａを含むタブＦＥＴとみなすことができる。後で詳細に説明するように、第２の層６４ａを含む第２のタブ６４はドレインフィールド終端（ＤＦＴ）手段として動作し、印加されたドレインバイアスがキャリアをソース領域からチャネル領域の中又はチャネル領域の下に注入されないようにすることによって、ソース領域をシールドする。従って、第２のタブ６４及び第２の層６４ａも、ドレインフィールド終端（ＤＦＴ）領域と呼ぶことができる。
【００８７】
図６及び図７のバイナルＦＥＴ６０及び６０’の動作は、米国特許第５，６９８，８８４号の中で詳細に説明されているため、本願では再度説明しない。
【００８８】
［金属ゲート形フェルミＦＥＴトランジスタ］
公開されたＰＣＴ出願第ＷＯ９９／１７３７１号によれば、フェルミＦＥＴにコントラドープされたポリゲート（contra-doped polygate）ではなく金属ゲートを用いることによって、過度に漏洩電流を増加させること及び／又は必要以上に飽和電流を減少させることなく、フェルミＦＥＴトランジスタのしきい値電圧を低下させることができる。
【００８９】
図８は、金属ゲート形フェルミＦＥＴの実施形態を示す。この実施形態は、本願の図４に示す米国特許第５，５４３，６５４号のＮチャネルの短チャネル形フェルミＦＥＴの後にパターン化される。しかしながら、金属ゲート形フェルミＦＥＴ技術はそのしきい値電圧を低下させるために全てのフェルミＦＥＴに適用することができることは、当業者は認識されよう。
【００９０】
図８に示すように、金属ゲート形フェルミＦＥＴ１１０は、図４のＰ型ポリシリコンのゲート２８及び金属ゲートの電極層２９ではなく金属ゲート２８’を含む。説明を容易にするために、トランジスタ１１０の他の全ての素子は図４から変更しない。従って、図１１に示すように、金属ゲート２８’はゲート絶縁層２６上に直接含まれる。別の言い方をすると、フェルミＦＥＴ１１０の金属ゲート２８’は、ゲート絶縁層上に直接配置されるドープされたポリシリコンを含まない。このため、接点電位は、ポリシリコンのフェルミ電位によって制御されない。金属ゲートは複数の層を含み、ゲート絶縁層上に直接配置された層はドープされたポリシリコンを含まないことは理解されよう。
【００９１】
具体的に言うと、仕事関数がシリコンのバンドギャップのほぼ中心にある金属、ケイ素化合物、又は他の金属合金は、有害な二次元効果を過度に増やすことなくフェルミＦＥＴのしきい値を著しく減らすことができる。
【００９２】
仕事関数が約４．８５Ｖの材料は、対称的なＮチャネル及びＰチャネルのドーピングを結果として生じることができるため、フェルミＦＥＴの構造体には特に好ましい。他の材料を使用して、希望する性能にもよるが、比較的低いしきい値をＮ又はＰチャネルの装置に与えることもできる。Ｐ型シリコンとｎ型シリコンとの間の仕事関数を有する金属又は金属合金を使用することが好ましい。
【００９３】
［トレンチゲート形フェルミＦＥＴトランジスタ］
ここで図９を参照すると、本発明の実施形態によるＮチャネルのトレンチゲート形フェルミＦＥＴ９０の断面図が示されている。当業者は、Ｎ及びＰの領域の伝導性を逆にすることによって、Ｐチャネルのトレンチゲート形フェルミＦＥＴを得ることができることは理解されよう。図９に示すように、これらの実施形態は、表面１２１ａを有する、ここではＰ型の第１の導電型の半導体基板１２１を含む。基板１２１は、実際は、ここではＮ型の第２の導電型の基板１３３の中の第１の導電型の井戸領域であることは理解されよう。特に、Ｎチャネルのトレンチゲート形フェルミＦＥＴは、一般に、Ｎ型基板１３３の中のＰ型井戸１２１の中に形成されるが、Ｐチャネルのトレンチゲート形フェルミＦＥＴは、井戸領域を必要とすることなく、Ｎ型基板の中に形成される。Ｎ型及びＰ型の両方のトレンチゲート形フェルミＦＥＴは、よくＣＭＯＳ基板と呼ばれる単一の半導体基板の中に集積することができることも理解されよう。最後に、基板１３３及び／又は井戸領域１２１は、バルクの半導体材料の上に形成された１つ以上のエピタキシャル層も含むため、基板表面１２１ａは実際にはバルクの半導体材料の外面ではなく、エピタキシャル層の外面であることは、当業者は理解されよう。
【００９４】
さらに図９を参照すると、フェルミタブとも呼ばれる、ここではＮ型の第２の導電型のタブ領域１２２が、半導体基板１２１の中の表面１２１ａに設けられて、表面１２１ａから第１の深さＸ_iまで半導体基板の中に延びている。ここではＮ型の第２の導電型の、それぞれ間隔を空けたソース及びドレインの領域１２３及び１２４も、タブ領域１２２の中の表面１２１に設けられる。図９に示すように、ソース及びドレインの領域１２３及び１２４は、タブ領域１２２と、ここではＮ型の第２の導電型の単一の導電接合すなわちユニジャンクションを形成する。これらの間隔を空けたソース及びドレイン領域は、Ｎ⁺⁺で示すように高度にドープされて、第１の深さＸ_iより浅い第２の深さＸ_jまでタブ領域１２２の中に延びる。
【００９５】
トレンチ１３４が間隔を空けたソース及びドレインの領域１２３と１２４との間のタブ領域１２２の中に設けられ、表面１２１ａからタブ領域１２２の中に第３の深さＸ₃まで延びている。この第３の深さＸ₃は第２の深さＸ_jよりも深いが、第１の深さＸ_iよりも浅い。トレンチ１３４は図９では断面が長方形で示されているが、Ｕ，Ｖ又は角が丸い長方形の断面など、他の多くの形状の断面も使用できる。ゲート電極１２８及びゲート絶縁層１２６から構成する絶縁されたゲート電極が、トレンチ１３４の中に設けられる。ゲート電極１２８は幅Ｌ_dを有し、ソースまたはドレイン領域１２３／１２４の下方に分量Ｘ_dまで延び、ソース及びドレイン領域の上方に分量Ｘ_oまで延びる。
【００９６】
ソース及びドレインの電極１３１及び１３２は、例えば、それぞれソース及びドレインの領域１２３及び１２４と電気的に接触する表面１２１ａ上に設けられる。絶縁領域１４２を設けて、ソース及びドレインの電極１３１及び１３２を分離する。基板接点も、表面１２１ａ上及び／又は基板の反対側の表面上に設ける。最後に、図９に示すように、基板（又は井戸）１２１がドーピング濃度Ｎ_aでドープされ、タブ１２２がドーピング濃度Ｎ_dでドープされる。
【００９７】
さらに図９を参照する。本発明の実施形態によれば、タブとトレンチの床面との間の距離Ｙ₀は、第１の深さＸ_iから第３の深さＸ₃を引いた値に等しく、次のように式（５）に基づいて設定される。
【数９】

ここで、Ｎ_dはタブ１２２のドーピング濃度であり、このドーピング濃度は変化するが、トレンチの床面と基板１２１との間のタブ１２２の平均のドーピング濃度であることが好ましい。Ｎ_aは基板すなわち井戸のドーピング濃度であり、Ｎ_aは変化するが、ゲート１２８の下側でタブ１２２に隣接する位置のドーピング濃度であることが好ましい。ｎ_iは温度Ｔケルビンにおける材料の固有のキャリア濃度である。ε_sは材料の誘電率（シリコンの場合、ｋは１．３８ｘ１０^-23ジュール／ケルビン）である。そして、ｑは１．６ｘ１０^-19クーロンである。
【００９８】
式（５）は、トレンチ１３４の下側のタブ１２２の中の空乏領域の長さを定義することができる。この空乏領域が、第３の深さＸ₃から第１の深さＸ_jまでのトレンチ１３４の下側のタブ領域１２２を完全に空乏化するように延びることが好ましい。
【００９９】
本発明の実施形態では、Ｙ₀が式（５）で定義された距離に完全に等しい場合、トレンチゲート形フェルミＦＥＴのしきい値電圧は、シリコン基板とゲート材料との間の仕事関数の差に等しくなる。言い方を変えると、トランジスタのしきい値は基板のフェルミ電位の２倍になる。これにより、装置のしきい値電圧ではゼロとなる、チャネル領域の中で可能な縦方向の電界が最も低くなる装置を結果として生ずる。このため、電界効果トランジスタのしきい値電圧を絶縁されたゲート電極に印加すると、第３の深さＸ₃において基板の表面に垂直なゼロの静電界が生じる。適当なゲート材料を正しく選択すると、「理想的な」トレンチゲート形フェルミＦＥＴトランジスタを作ることができる式（５）の基準をなお満足させながら、数ミリボルト以下から１ボルト以上のしきい値を結果として生ずることができる。
【０１００】
トランジスタのしきい値を「理想的な」値の上又は下のいずれかに調整することは、縦方向の電界を少し増やすだけで可能である。このため、縦方向の電界は、タブ領域１２２を含まない電界効果トランジスタが発生する電界の大きさよりも、少なくとも１桁小さく維持される。他の実施形態では、電界は、タブ領域１２２を含まない電界効果トランジスタが発生する電界の１／２未満である。さらに他の実施形態では、縦方向の電界は、タブ領域１２２を含まない電界効果トランジスタが発生する電界の１／５未満である。さらに別の実施形態では、静電界は７００Ｖ／ｃｍ未満であり、これは縦方向の電界が約１０，０００Ｖ／ｃｍと約１００，０００Ｖ／ｃｍとの間の従来の電界効果トランジスタと比較することができる。Ｙ₀の実際の値を式（５）の中で定義された値から変えることによって、縦方向の電界を増加させることができる。Ｙ₀を増加することにより、装置のしきい値をゼロに低下することができる。
【０１０１】
従来の表面チャネルトランジスタ及び従来の埋込みチャネル電界効果トランジスタは、一般に、ゲート絶縁体の厚さに対して強いしきい値感度を有する。極めて対照的なことに、フェルミＦＥＴトランジスタの実施形態では、ゲート絶縁体の厚さに対する感度がほとんど又は全くないため、しきい値電圧はトレンチ床面上の絶縁層１２６の厚さには無関係のままである。このことは、しきい値電圧においては、絶縁体の電界は、しきい値電圧の極めて近くでゼロを通り、負方向から正方向に切り替わるという事実による。
【０１０２】
図１０Ａ及び図１０Ｂは、それぞれトレンチゲート形フェルミＦＥＴトランジスタ及び従来の表面チャネルトランジスタに対して印加されたゲートバイアス対ゲート絶縁体（例えば、酸化物）の電界を図表で示す。図１０Ａ及び図１０Ｂでは、また後に続く全てのシミュレーション結果では、シミュレーションは次の特性を有するトランジスタに対して行われた。
ドレインのチャネル長、 Ｌ_d＝０．１８μm；
ゲート酸化物（絶縁体）の厚さ、 Ｔ_ox＝３５Å；
動作ドレイン電圧、 Ｖ_d＝２．５ボルト；
漏洩電流（１．８Ｖにおける）、 Ｉ_dss＝２０ｐＡ／μm
図１０Ａに示すように、ゲート絶縁体の厚さには無関係に、トレンチゲート形フェルミＦＥＴの電界は低く、しきい値は１つである。これとは対照的に、図１０Ｂに示すように、従来の表面チャネルトランジスタは電界が高く、しきい値はゲート酸化物の厚さに大きく依存する。
【０１０３】
さらに、例えば、Panousisへの米国特許第４，８３５，５８５号、Solomonへの米国特許第５，１０８，９３８号及びIwamatsuへの米国特許第５，１４２，６４０号の中で説明したような、従来のトレンチゲート形電界効果トランジスタは、ゲート絶縁体の厚さに対してしきい値電圧の強い依存性を示す。換言すると、フェルミＦＥＴでない装置では、トレンチの角又は頂点などの誘電体が厚い領域ではしきい値電圧が高くなるため、トレンチにおけるチャネルの形成は均一でなくなる。これとは極めて対照的に、本発明の実施形態によるトレンチゲート形フェルミＦＥＴは、頂点でのゲート絶縁体の厚さにかかわらず、装置全体にわたってしきい値を均一にすることができる。
【０１０４】
図１０Ａ及び図１０Ｂに示すように、本発明の実施形態によるトレンチゲート形フェルミＦＥＴは、ゲート誘電体の厚さに対するしきい値電圧の感度を極めて低くすることができる。これにより、チャネル全体を一体として動作させることができ、このことは高いＧ_m及び極めて急速な動作を提供することができる。全く対照的に、表面チャネル装置及び従来の埋込みチャネルトランジスタの酸化物の厚さに対するしきい値感度は著しく高い。トレンチの頂点に隣接した場所で生ずるより厚い誘電体は、トレンチが長方形、丸みが付いた長方形、Ｖ字形又はＵ字形の場合でも、トランジスタを薄い領域で最初に動作させ、次ぎに遅れて厚い領域で動作させるため、オン抵抗を増加させ、またしきい値以下でのスイング（subthreshold swing）及びＧ_mを減少させる。
【０１０５】
図１１Ａ及び図１１Ｂは、それぞれトレンチゲート形フェルミＦＥＴトランジスタ及び従来のトレンチゲート形ＭＯＳＦＥＴトランジスタの実施形態の断面図であり、その中のチャネルの形成を図示すると共に対照させている。図１１Ａ及び図１１Ｂでは、全てのソース、ドレイン及びゲート電極は０Ｖのため、装置はオフである。図１１Ａに示すように、タブ１２２と井戸（すなわち基板）１２１との間に形成されたＰ／Ｎ接合により、タブ１２２及び井戸１２１の両方の中に空乏層が発生する。このため、空乏領域１２２ｂ及び空乏でない領域１２２ａがタブ１２２内に作られ、また空乏領域１２１ｂ及び空乏でない領域１２１ａが基板すなわちタブ１２１の中に作られる。
【０１０６】
図１１Ａに示すように、タブ領域１２２は、トレンチの床面から空乏化された領域１２２ｂ及び１２１ｂの界面における、タブ１２２と井戸１２１との間のＰ／Ｎ接合部までのトレンチ１３４の下側が完全に空乏化される。これにより、トレンチ１３４の下側に制限され、トレンチの幅Ｌ_dにわたって延び、厚さがトレンチの下側及びトレンチの幅Ｌ_dにわたって均一なチャネル１４０が作られる。このため、第２の導電型のキャリアが、電界効果トランジスタのしきい値電圧がゲート電極１２８に印加されると、タブ領域１２２の中のトレンチ１３４の下側の第３の深さＸ₃を流れる。さらに、第２の導電型のキャリアが、電界効果トランジスタのしきい値電圧を超える電圧がゲート電極１２８に印加されると、トレンチ１３４の下側のタブ領域１２２の中を流れ、第３の深さＸ₃から第１の深さＸ_iに向かって延びる。また、チャネル１４０の長さはトレンチの幅Ｌ_dに比例し、第１の深さＸ_iと第２の深さＸ_jとの間の差には無関係である。
【０１０７】
極めて対照的に、図１１Ｂの従来のトレンチＭＯＳＦＥＴでは、チャネル長は、一般に、次の式：Ｌ_eff≒Ｗ＋２Ｄに基づく、トレンチの深さに強く影響される関数である。ここで、Ｌ_effは有効チャネル長、Ｗはトレンチの幅、そしてＤはトレンチがソース及びドレインの深さを超える深さである。このため、トレンチの深さの小さな変化は、従来のＭＯＳＦＥＴ内の有効チャネル長に対しては比較的大きな変化をもたらすが、トレンチゲート形フェルミＦＥＴのしきい値電圧にはわずかな変動しか与えない。このことは、従来のＭＯＳＦＥＴが得ることができるものよりも極めて大きな処理の安定性を提供することができる。
【０１０８】
前述したように、Ｎチャネル及びＰチャネルのトレンチゲート形フェルミＦＥＴは集積基板の中に集積化され、論理メモリ、マイクロプロセッサ及び／又は他の用途に対する高性能なＣＭＯＳの用途を提供することができる。その上、トレンチゲート形フェルミＦＥＴは、高周波数で高電力の動作に特に良く適合することができる電力増幅器を含むラテラル電力装置（lateral power device）にも良く適合する。これらのラテラルトランジスタでは、ドレイン領域１２４の下側のタブ１２２の空乏化されない部分１２２ａの幅及びドーピングレベルを、電流経路に沿って傾斜濃度を有する垂直ドリフト領域として機能するように「調整」することができる。このため、単一の導電率の階段接合を、ソース１２３とタブ１２２との間及びドレイン１２４とタブ１２２との間に設ける必要はない。フェルミＦＥＴのチャネルの大きな有効移動性と組み合わされたドレイン領域は、高いブレイクダウン電圧、低いオン抵抗及び通常ヒ化ガリウムのようなよりエキゾティック半導体（more exotic semiconductor）に関連した動作周波数を有するＲＦ電力増幅器を作るように組み合わせることができる。
【０１０９】
［トレンチゲート形フェルミＦＥＴの製造工程］
トレンチゲート形フェルミＦＥＴトランジスタを形成する製造工程をここで説明する。以下に示すように、トレンチゲート形フェルミＦＥＴを作る製造工程は、従来のＭＯＳＦＥＴ及び／又はフェルミＦＥＴを形成するために使用するものよりも著しく短く及び／又は簡単にすることができる。工程を短く及び／又は簡単にできる１つの理由は、ゲートの構造体を他のドーピングが行われた後に作ることができるためである。これにより、ゲート、ソース、ドレイン及びチャネルを自己整列させることができる。
【０１１０】
図１２Ａ〜図１２Ｆは、本発明の実施形態による中間の製造段階の間の、本発明の実施形態によるトレンチゲート形フェルミＦＥＴの断面図である。Ｎチャネルのトレンチゲート形フェルミＦＥＴの製造が図示される。しかしながら、導電型を逆にすることによって、Ｐチャネルのトレンチゲート形フェルミＦＥＴも形成することができる。
【０１１１】
ここで図１２Ａを参照すると、単結晶のシリコン基板又はシリコン・オン・インシュレータ基板などのＰ型基板１３３が設けられている。最初の酸化被膜２０２又は他の絶縁層を、従来の技術を用いて形成する。フォトレジスト層のようなマスク２０４をパターン化して、トランジスタの位置を規定する。従来のフィールド酸化物及び／又はトレンチ絶縁部も設ける。マスク２０４は、後で説明するように、各種のイオン２１０を注入する埋込みウィンドウを規定する。
【０１１２】
さらに図１２Ａを参照する。Ｐイオンを注入してＰ井戸１２１を形成する。Ｎイオンを注入してＮ^-タブ１２２’を形成し、Ｎ⁺イオンを注入してソースまたはドレイン領域１２５を形成する。領域１２１，１２２’及び１２５を形成する注入の順序は任意であるため、例えば、ソースまたはドレイン領域１２５をタブ領域１２２’の前に注入することができ、これらの領域のいずれか又は両方は井戸領域１２１を形成する前に注入することができることは理解されよう。Ｐ型の基板を使用してＮチャネルのトレンチゲート形フェルミＦＥＴを製造する場合は、井戸領域１２１を形成する必要がないことも理解されよう。注入技術は当業者には周知であるため、本願ではこれ以上説明する必要はない。また図１２Ａに示すように、ソースまたはドレイン領域１２５の注入は、後で詳細に説明するが、垂直面から傾斜角θで行われる。
【０１１３】
ここで図１２Ｂを参照する。マスク２０４を取り除き、任意の窒化ケイ素の層２０６を従来の技術を用いて形成する。次に、第２のフォトレジスト層のような第２のパターン化されたマスク２０８を形成して、トレンチを定義する。次に、図１２Ｃに示すように、マスク２０８を使用して窒化物の層２０６をエッチングする。次に、この窒化物の層２０６をマスクとして使用して、トレンチ１３４を形成する。このトレンチ１３４はソースまたはドレイン領域１２５を通ってエッチングされて、間隔を空けたソース及びドレインの領域１２３及び１２４を形成し、部分的にタブ領域１２２の中にエッチングされて、前述した深さＹ₀を形成する。
【０１１４】
このように、トレンチ及びゲートが、ソースまたはドレイン、タブ及び井戸に対する注入を行った後で形成される。従って、ゲート構造体を作る前に注入２１０を完了することができるため、高濃度のＮ⁺注入を行って、約１５°を超える大きな傾斜角θを用いて、ソースまたはドレイン領域１２５を形成することができる。このため、ゲート電極を製造し、次ぎにこのゲート電極を用いて自己整列したソース及びドレインの領域をその後で形成するような工程と比較すると、浅く急峻なソースまたはドレイン領域１２３及び１２４を形成することができる。従来の工程では、浅く急峻なソースまたはドレイン領域を設けるために望ましい大きな傾斜角θは、ソース及びドレインの領域とゲートとの間の位置合わせ不良をもたらすことがある。これとは極めて対照的に、トレンチ１３４及びゲートをソースまたはドレイン領域の形成に続いて形成するため、図１２Ａでは、垂直面から１５°以上の大きな傾斜角θを使用して、ソースまたはドレイン領域１２５を形成することができる。タブ領域１２２’及び／又は井戸１２１を形成するには、小さい傾斜角を用いる又は傾斜角を使用しないこともある。
【０１１５】
式（５）に基づいてフェルミＦＥＴの性能を最適にできるように、トレンチ深さＸ₃をソース１２３、ドレイン１２４及びタブ１２２の埋込みプロフィールに適合させる必要があることも理解されよう。実際の注入プロフィールを理論的に予測することは若干難しいため、埋込み物及び熱工程を含む試験ウエハを作り、次に周知の量だけウエハの表面の中をエッチングすることによって、トレンチの深さＸ₃を実際の埋込みプロフィールに適合させることができる。次に、これらのサンプルを、後で説明するように、容量−電圧（ＣＶ）技術を用いて測定し判断することができる。
【０１１６】
ここで図１２Ｄを参照すると、ゲートの絶縁層１２６が形成されている。このゲート絶縁層１２６は、従来の熱酸化技術及び／又は従来の化学気相蒸着技術を用いて形成され、二酸化ケイ素の層を形成する。多層の酸化物の材料も使用することができる。窒化ケイ素などの他のゲート絶縁層も使用することができる。さらに、高温のアニールは図１２Ａ〜図１２Ｃとの関連においてすでに行われたので、ＰＺＴのような強誘電体材料を含む誘電率が高い材料などのエキゾティック誘電体材料（exotic dielectric material）も使用できるが、これらの材料に限定されることはない。当業者は周知であるが、これらの材料の特性は、高温に極めて敏感である。高温のアニールはすでに行われているので、それらをトレンチゲート形フェルミＦＥＴトランジスタに使用することができる。
【０１１７】
ここで図１２Ｅを参照する。ゲート電極の材料１２８’をブランケット蒸着（blanket-deposite）し、次ぎにエッチバックするか又は平坦化して、図１２Ｆのゲート電極１２８を形成する。いくつかの実施形態では、タングステンをゲート電極に使用し、従来の蒸着技術を用いて蒸着し、次ぎに化学機械研磨法（ＣＭＰ）を用いて、例えば窒化物の層２０６をストップとして用いて平坦化する。
【０１１８】
図１２Ｆに示すように、ゲート電極１２８をオーバエッチング及び／又は分離エッチング工程を行って、ゲート電極１２８を基板１３３の表面１２１ａより凹ませる。後で説明するように、ゲート電極１２８を、電界効果トランジスタ内のドレイン電流を減少させずに、絶縁されたゲート電極と間隔を空けたソース及びドレインの領域１２３及び１２４との間の容量を最小にする深さだけ、表面より凹ませることが好ましい。最後に、窒化物の層及び／又は酸化物の層２０６及び２０２を取り除き、絶縁層１４２及びソース及びドレイン接点１３１及び１３２（図９）を従来の技術を用いて形成する。さらに、上側及び／又は下側の基板接点も、従来の技術を用いてこの工程の中に組み込む。装置の分離工程も、前述した処理の前又は後に組み込む。
【０１１９】
このように、図１２Ａの注入工程に続くアニール動作の後で、高温の工程を減らす、また好ましくは削除することができる。従って、従来のトランジスタでは容易に使用することができない多くの他のゲート誘電体材料を使用することができる。
【０１２０】
［電気的シミュレーション］
前述のプロセスシミュレーションからの構造ファイルを、Ｎチャネルトランジスタをシミュレートするために、Atlasシミュレーションプログラムの入力として使用した。このシミュレーションは、デフォルトの移動度パラメータを使用し、４．６３ｅＶの仕事関数値をゲート材料に割り当てる。この実施例では、タングステンを使用した。他の全ての電極をニュートラルとして定義した。
【０１２１】
図１３は、同じアーキテクチャを用いて作られ、全ての電極のバイアスをゼロに設定したトレンチゲート形フェルミＦＥＴ（左側）の実施形態及び従来のトレンチＭＯＳＦＥＴ（右側）の中に存在する自由キャリア濃度を示すシミュレーション結果を示す。２つの装置を比較することによって、チャネル長の相違が明らかに認識できる。電気的シミュレーションの比較では、従来のＭＯＳＦＥＴは、フェルミＦＥＴの中に含まれるドリフト領域を含まないことに理解されたい。しかしながら、このことは、ＭＯＳＦＥＴ側に明らかに駆動電流を増加するように働く。
【０１２２】
図１４Ａ及び図１４Ｂは、それぞれ対数形式及び線形形式の同一のモデルパラメータを使用する、シミュレートされたトレンチゲート形フェルミＦＥＴ対シミュレートされたＭＯＳＦＥＴのドレイン電流対ゲート電圧特性を図表で示す。図１４Ａ及び図１４Ｂは、トレンチゲート形フェルミＦＥＴのアーキテクチャを使用する電位上の利点を明らかに示している。フェルミＦＥＴの中にドリフト領域が存在するにもかかわらず、しきい値電圧が一致する場合、ＭＯＳＦＥＴの駆動電流は僅か約６５％であり、漏洩電流は約３０倍大きい。
【０１２３】
さらに、トレンチは、埋込みチャネル形の装置の中でよく見られる短チャネル効果を劇的に高めることができる。これにより、容量を著しく低下させると共に低いしきい値電圧を使用することができ、これにより例えば、高性能な無線周波数の装置を作ることができる。
【０１２４】
図１５Ａ及び図１５Ｂは、トレンチゲート形フェルミＦＥＴのシミュレートされた実施形態に対して、対数形式及び線形形式によるトランジスタの性能を示す。この場合、ドレイン電圧は０．１Ｖと２．５Ｖとの間を変化する。短チャネルの効果が相対的にないことが、はっきりと示されている。
【０１２５】
図１６Ａ及び図１６Ｂは、ゲート絶縁層の厚さの変化の関数として、トレンチゲート形フェルミＦＥＴトランジスタについてのシミュレーション結果を図表で示す。特に、図１５Ａ及び図１５Ｂは厚さが４．０ｎｍのゲート絶縁体の厚さを示し、一方、図１６Ａ及び図１６Ｂは５．０ｎｍのゲート絶縁体の厚さを示す。ゲート絶縁体の厚さに対してしきい値が無関係であることが、明確に示されている。ドーピングがないこと又は深さの変化が、図１５Ａ及び図１５Ｂ並びに図１６Ａ及び図１６Ｂの構造体の間に発生している。誘電体が厚いと、線幅又はドーピングを変化させる必要なしに、動作電圧をそれだけ高くすることができる。繰り返すと、短チャネルの効果がないことが理解できる。
【０１２６】
２．５Ｖ及び３．３Ｖの両方のトレンチゲート形フェルミＦＥＴは、トランジスタのアーキテクチャにより、極めて高いブレイクダウン電圧（ＢＶ_dss）を有することができる。適当なゲート誘電体を用いることにより、ＢＶ_dssをトランジスタのアーキテクチャではなくＰ／Ｎ接合の関数とすることができる。このため、Ｐ／Ｎ接合を適当に構成することにより、低いしきい値電圧を維持しながら、極めて高いブレイクダウン性能を可能にできる。このことは、トレンチゲート形フェルミＦＥＴを電力用途に対して望ましい技術にすることもできる。
【０１２７】
図１７Ａは、ドレインバイアスをブレイクダウン点に設定した場合の、短チャネルのトレンチゲート形フェルミＦＥＴトランジスタのシミュレーションを示す。輪郭は自由ホール及び自由電子を示し、また図１５Ａ及び図１５Ｂの２．５Ｖトランジスタに対するブレイクダウンが始まるときの自由キャリアの濃度（１０¹¹ｃｍ^-3以上）を示す。ドレインから基板へのブレイクダウン経路が明確に示される。ブレイクダウンは、図１７Ｂに示すように、７．９８Ｖのドレイン電極の電位で発生する。ブレイクダウン時の端子電流は、ドレインから井戸への動作のみを示すが、電界が最大になる領域は空乏化されない井戸の近くのため、ゲートトレンチの直ぐ下である。
【０１２８】
本発明の実施形態によるトレンチゲート形フェルミＦＥＴトランジスタのブレイクダウン電圧は、少なくとも２つの技術を用いて、高くする好ましくは最大にすることができる。第１は、低濃度のＮシリコンの領域がタブ１２２と井戸１２１との間の接合部の上に存在できるように、ソース及びドレインの領域１２３及び１２４（図９）を十分に浅くすることができることである。このことは、必要なら、ソースまたはドレイン領域１２５（図１２Ａ）に対して大きな傾斜角θで低エネルギーの拡散注入を行うことによって実現できる。ゲートの構造体が拡散の後で作られるために大きな傾斜角が可能であるため、シャドーイングを考慮する必要がない。
【０１２９】
ブレイクダウン電圧を増加させる第２の方法は、ゲートの誘電体を一層厚くすることである。一層厚い誘電体のフィルムは、ピークの電界をウェアアウトレベル（wear-out level）の下に維持することができる。しきい値が誘電体の厚さに比較的影響を受けないため、他の装置パラメータを変更する必要なしに、より厚い誘電体を使用することができる。
【０１３０】
［トレンチの深さ及びゲートの凹部についての実験的な最適化］
前述したシミュレーションを使用して、注入ドーズ及びエネルギー並びに第１から第３の深さを調整することによって、本発明の実施形態によるトレンチゲート形フェルミＦＥＴの性能を向上及び好ましくは最適化することができる。しかしながら、実際の装置を作る場合、実際の注入プロフィールは、シミュレーションの中で使用した実際のプロフィールに正確に一致しないため、この最適化を作ることは困難であることは理解されよう。このことは、２つの反対ドーピングの注入プロフィール間のバランスのために、性能を式（５）から逸脱させることになる。
【０１３１】
この潜在的な困難を考慮して、工程開発の努力における複雑さを減らすことができるように、注入パラメータと実際のシリコン内のトレンチ深さとをバランスさせる実験的な技術をここで説明する。実際に、注入及び深さの値は、前述したように、シミュレーションの中の値に達することができる。次に、ここで説明する技術を用いて、補正を実際のシリコンに対して行うことができる。
【０１３２】
特に、図１２Ａ〜図１２Ｆで説明した工程に基づいて、図１２Ｃのエッチング段階を行わずに、試験ウエハを製造することができる。次に、図１２Ｃのトレンチのエッチングをウエハ全体にわたって行い、ウエハ全体の各種の位置の様々な深さで停止する。この工程に続いて、ゲートの誘電体を成長又は蒸着させ、次にゲート電極を加えてパターン化し、これによりコンデンサのアレイを作る。パターンニングは従来の技術を用いて行われる。図１８Ａ〜図１８Ｅは、単一のウエハ及び／又は一連のウエハの中で行われるエッチングの各種の段階を示す。ウエハ表面のエッチングされる深さが増えるにつれて、図１１ＡのＰ／Ｎ接合の深さは浅くなり、ソースまたはドレインの層１２５のドーピングは高濃度の拡散部がエッチングで除去されるにつれて小さくなる。
【０１３３】
エッチング量の関数としての容量対電圧（ＣＶ）プロットの動作は、電極のエッジ対面積の比率に依存する。図１９Ａ及び図１９Ｂは、それぞれ、大きな面積のコンデンサ及び小さな面積のコンデンサのシミュレーションを示す。所望のエッチング量は、図１９Ａ及び図１９Ｂから求めることができる。
【０１３４】
特に、図１９Ａ及び図１９Ｂの曲線を考察すると、実際に使用される特定の注入及び熱サイクルの組に対するトレンチのエッチング深さが適当であると認めることができる。例えば、図１９Ａの大きな面積対周辺曲線を調べると、グラフの右側では、エッチング深さの増加に伴って容量の初期低下があることが分かる。しかしながら、グラフの左側（負電圧側）の容量は、Ｃ_oxで止まったままである。エッチング深さを増加すると、正電圧側の容量は最低になり、増加し始める。さらにエッチングしても正電圧側の容量は増加しないが、負電圧側の容量をＣ_oxより下に急速に低下させる。最適なトランジスタは、負側の容量が低下し始める直前でエッチングを停止することによって得ることができる。図１９Ａでは、最適化されたフェルミＦＥＴのトレンチ深さは１５０ｎｍであることが分かる。この装置のしきい値における酸化物の電界のシミュレーションは、７００Ｖ／ｃｍ未満の垂直な成分を示す。
【０１３５】
小さい面積対周辺コンデンサの分析（図１９Ｂ）は、動作がやや異なっていることを示す。しかしながら、トレンチ深さの最適化をさらに行うことはできる。図１９Ａのように、初期のエッチング効果は、グラフの右側の、エッチング深さが増加する場合の容量の低下である。さらにエッチングを続けると、右側で容量が最低になる。エッチングを続けると、この正側の容量は急速に最大に達し、そして一定になる。さらにエッチングしても正側の容量は増加しないが、負側では容量が急速にＣ_oxよりも低下する。最適なトランジスタは、正側の容量が最大に達すると同時に、負側の容量が下降し始める前にエッチングを停止することによって得ることができる。繰り返すが、最適なトレンチ深さは１５０ｎｍである。これは、最小反転容量曲線（minimum inversion capacitance curve）と一致する。
【０１３６】
要約すると、トレンチ深さは、実際のトランジスタに中で使用される同じ誘電体及びゲート電極の材料を有する試験コンデンサ上で測定された容量／電圧プロットの負側で、容量を最大にできる最大深さを求めることによって決定する。
【０１３７】
前述したように、ゲート電極１２８（図９）は、表面１２１ａより凹ませることが好ましい。ゲートは、電界効果トランジスタ内のドレイン電流を減少させずに、絶縁されたゲート電極と間隔を空けたソース及びドレインの領域との間の容量を最小にする深さまで、表面から凹ませることが好ましい。ゲート電極を凹ませるための潜在的に最適な量を求める方法を、ここで説明する。
【０１３８】
特に、高速動作に対しては、好ましいことは全ての容量を減少させることであり、さらに好ましくは、最小にすることである。拡散領域の容量は、接合部がＮ⁺：ＰではなくＮ：Ｐであるため、拡散領域を深さ方向に急峻に保つことによって最小にすることができる。このことは、ブレイクダウン電圧の最適化の一部として行われる。ゲート−井戸間の容量は、フェルミＦＥＴトランジスタが動作する電荷重心が深いために、すでに小さくなっている。このため、最適化する残りの項目は、ゲート電極１２８とソース及びドレインの領域１２３，１２４との間の重複した容量である。
【０１３９】
公称３．３Ｖバージョンの装置を用いて、平坦化の後の様々な量のゲートのエッチバック（gate etchback）を用いて一連のシミュレーションを実行した。ゲート凹部の深さは、図９でＸ_j−Ｘ₀として定義する。定性的に、凹部の深さは、ゲート材料を基板の上面と一致するように機械的に平坦化した後の、トレンチの上面から測定される。
【０１４０】
図２０Ａは、種々の深さのゲート凹部を用いた、シミュレートされたトランジスタのシミュレートされた容量対電圧のプロットである。これらのトランジスタのそれぞれのドレイン電流対ゲート電圧の性能を、図２０Ｂに示す。図２０Ａを参照すると、オン抵抗が増加するために図２０Ｂの駆動電流が低下し始める前に、最も深い凹部を有する装置を選択することによって、寄生容量を最適にすることができる。図２０Ａ及び図２０Ｂでは、これは６０ｎｍのエッチバックに相当する。エッチバックの前の電極全体の高さは１５０ｎｍであることに注意すること。最適な性能を提供できる小さなエッチバック量では、ゲートの接触高さと拡散領域との接触高さとの間の差は大抵の工程では重要ではないため、接触エッチングに対しては特別な設備を作る必要はない。
【０１４１】
図２１Ａ及び図２１Ｂは、それぞれ、上述した方法に基づいて最適化された装置の最終的な正味ドーピング及び実際のＰ型及びＮ型のドーピングプロフィールを示す。
【０１４２】
［結論］
本発明の実施形態によるトレンチゲート形フェルミＦＥＴは、例えば、１／１０ミクロン以下の線幅を用いる短チャネルのＣＭＯＳ装置に特に良く適合する。本発明の実施形態によるトレンチゲート形フェルミＦＥＴは、ＲＦ増幅器の中で使用されるような高電力及び／又は高速の線形用途にも特に良く適合する。
【０１４３】
本発明の実施形態によるトレンチゲート形フェルミＦＥＴは、極めて簡単にした工程を用いて製造することができる。ハロー、拡張及び広範なチャネル工学を使用する必要はない。短チャネルの影響を大いに減少させることができる。極めて浅いソース及びドレインのプロフィールは大きな傾斜角を用いて作ることができるが、それらを必要としない。ソース及びドレインの寄生容量を減らすと共に、高いブレイクダウン電圧を提供することができる。さらに、ブレイクダウンの経路はゲートの誘電体ではなくバルクシリコンの中に入るため、信頼性を高めることができる。
【０１４４】
図面及び明細書の中で、本発明の典型的な好ましい実施形態を開示してきた。特定の用語が使用されるが、それらの用語は一般的で説明のためのみで使用されたものであり、限定する目的で使用したのではない。本発明の範囲は、以下の特許請求の範囲において述べる。
【図面の簡単な説明】
【０１４５】
【図１】米国特許第５，３７４，８３６号によるＮチャネル大電流形フェルミＦＥＴの断面図である。
【図２Ａ】米国特許第５，３７４，８３６号による短チャネル低漏洩電流形フェルミＦＥＴの第１の実施形態の断面図である。
【図２Ｂ】米国特許第５，３７４，８３６号による短チャネル低漏洩電流形フェルミＦＥＴの第２の実施形態の断面図である。
【図３】米国特許第５，５４３，６５４号によるＮチャネルの形状付けられたタブ形フェルミＦＥＴの断面図である。
【図４】米国特許第５，５４３，６５４号によるＮチャネルの短チャネル形フェルミＦＥＴの断面図である。
【図５】米国特許第５，８１４，８６９号によるＮチャネルの短チャネル形フェルミＦＥＴの第２の実施形態の断面図である。
【図６】米国特許第５，６９８，８８４号によるバイナルＦＥＴの第１の実施形態の断面図である。
【図７】米国特許第５，６９８，８８４号によるバイナルＦＥＴの第２の実施形態の断面図である。
【図８】公開されたＰＣＴ出願第ＷＯ９９／１７３７１号による金属ゲート形フェルミＦＥＴの実施形態の断面図である。
【図９】本発明の実施形態によるトレンチゲート形フェルミＦＥＴの断面図である。
【図１０】図１０Ａ及び図１０Ｂは、それぞれ本発明の実施形態及び従来の表面チャネルトランジスタの実施形態によるトレンチゲート形フェルミＦＥＴに対する印加されたゲートバイアス対ゲート絶縁体の電界を図表で示す図である。
【図１１】図１１Ａ及び図１１Ｂは、それぞれ本発明の実施形態及び従来のＦＥＴの実施形態によるトレンチゲート形フェルミＦＥＴトランジスタの断面図であり、中のチャネル形成を図示及び対照する。
【図１２】図１２Ａ〜図１２Ｆは、本発明の実施形態による中間の製造ステップ間の、本発明の実施形態によるトレンチゲート形フェルミＦＥＴの断面図である。
【図１３】本発明の実施形態及び従来のＦＥＴによるトレンチゲート形フェルミＦＥＴの実施形態の中に存在する自由キャリア濃度のシミュレーション結果を示す図である。
【図１４】図１４Ａ及び図１４Ｂは、それぞれ、本発明の実施形態によるシミュレートされたトレンチゲート形フェルミＦＥＴ対シミュレートされた従来のＦＥＴの、対数形式及び線形形式によるドレイン電流対ゲート電圧特性を図表で示す図である。
【図１５】図１５Ａ〜図１５Ｂは、それぞれ、本発明の実施形態によるシミュレートされたトレンチゲート形フェルミＦＥＴについての、対数形式及び線形形式によるトランジスタの特性を示す図である。
【図１６】図１６Ａ〜図１６Ｂは、ゲート絶縁層の厚さの変化の関数として、本発明の実施形態によるトレンチゲート形フェルミＦＥＴトランジスタに対するシミュレーション結果を図表で示す図である。
【図１７】図１７Ａは、ドレインバイアスをブレイクダウン点に設定した場合の、本発明の実施形態による短チャネルのトレンチゲート形フェルミＦＥＴトランジスタのシミュレーションを示す図である。図１７Ｂは、図１７Ａのシミュレートされたトランジスタに対するドレイン漏洩電流対ドレインバイアス電圧特性を示す図である。
【図１８】図１８Ａ〜図１８Ｅは、本発明の実施形態に基づいて、トレンチ深さの値を実験的に決定するために、単一のウエハ及び／又は一連のウエハの中で発生するエッチングの各種の段階の断面図である。
【図１９】図１９Ａ及び図１９Ｂは、本発明の実施形態による、それぞれ、大きな面積のコンデンサ及び小さな面積のコンデンサに対する図１８Ａ〜図１８Ｅのエッチング量の関数として、容量対電圧プロットを図表で示す図である。
【図２０】図２０Ａは、ゲート凹みが異なる、本発明の実施形態によるトレンチゲート形フェルミＦＥＴのシミュレートされた容量対電圧プロットを示す図である。図２０Ｂは、図２０Ａでシミュレートされたトランジスタに対するシミュレートされたドレイン電流対ゲートバイアスのプロットを示す図である。
【図２１】図２１Ａは、本発明の実施形態によるトレンチゲート形フェルミＦＥＴの、それぞれ、最終的な正味ドーピング及び実際のＰ型及びＮ型のドーピングプロフィールを示す図である。図２１Ｂは、本発明の実施形態によるトレンチゲート形フェルミＦＥＴの、それぞれ、最終的な正味ドーピング及び実際のＰ型及びＮ型のドーピングプロフィールを示す図である。【Technical field】
[0001]
[Field of the Invention]
The present invention relates to a transistor device and a method for manufacturing the same, and more particularly, to a field-effect transistor and a method for manufacturing the same.
[Background Art]
[0002]
[Background of the Invention]
Because FETs in integrated circuits are inherently high-impedance, high-density, and low-power devices, field effect transistors (FETs) are used in logic devices, memory devices, and very large scale integrated circuits (VSLIs) such as microprocessors. It has become a dominant active device for very large scale integrated circuit (ULSI) applications. More research and development activities have been focused on improving the speed and integration density of FETs and reducing their power consumption. FETs are also widely used as power devices such as power amplifiers. More research and development work has been focused on improving the speed and efficiency of FETs used as power devices in wired and wireless applications, especially at high frequencies.
[0003]
High speed, high performance field effect transistors are both described in U.S. Patent Nos. 4,984,043 and 4,990,974 by Albert W. Vinal. Both of these patents are entitled "Fermi Threshold Field Effect Transistor" and are both assigned to the assignee of the present application. These patents describe metal oxide semiconductor field effect transistors (MOSFETs) that operate in enhancement mode without the need for inversion by setting the threshold voltage of the device to twice the Fermi level of the semiconductor material. ing. As is well known to those skilled in the art, the Fermi level is defined as the level of probability that half of the energy state of a semiconductor material is occupied by electrons. As described in the above-mentioned Vinal patent, when the threshold voltage is set to twice the Fermi level, the threshold voltage for oxide thickness, channel length, drain voltage and substrate doping amount Is almost eliminated. Furthermore, if the threshold voltage is set to twice the Fermi level, the vertical electric field at the substrate surface between the oxide and the channel is minimized and is virtually zero. This maximizes the carrier mobility in the channel, resulting in a high speed device with greatly reduced hot electron effects.
[0004]
Compared to known FET devices, there has been a need to reduce the capacitance of Fermi-FET devices, despite the fact that Fermi-threshold FETs have been greatly improved. For this reason, both US Pat. Nos. 5,194,923 and 5,369,295 entitled "Fermi Threshold Field Effect Transistor With Reduced Gate and Diffusion Capacitance", both by Albert W. Vinal, assist carrier conduction. A Fermi-FET device has been described that allows conduction carriers to flow into a channel of predetermined depth in a substrate beneath a gate without the need to create an inversion layer on the surface of the semiconductor to accomplish this. Therefore, the average depth of the channel charge needs to include the dielectric constant of the substrate as part of the gate capacitance. This significantly reduces the gate capacitance.
[0005]
As described in the above-mentioned U.S. Pat. Nos. 5,194,295 and 5,369,923, a low-capacitance Fermi-FET has a conductivity type opposite to a substrate at a predetermined depth, but is different from a drain and a source. Is preferably realized using the same Fermi-tub region. The Fermi-tub extends downward from the substrate surface to a predetermined depth, and the drain and source diffusions are formed within the tab boundaries of the Fermi-tub. The Fermi-tub forms a single-junction transistor, in which the source, drain, channel and Fermi-tub are all doped with the same conductivity type but different doping concentrations. Thus, a low capacitance Fermi FET is provided. The low-capacitance Fermi-FET including the Fermi-tub is referred to as a “low-capacitance Fermi-FET” or “tab FET” in the present application.
[0006]
When compared to known FET devices, there has been a continuing need to increase the current per unit channel width that Fermi-FETs make despite the fact that Fermi-FETs and low-capacitance Fermi-FETs have been greatly improved. . As is well known to those skilled in the art, higher current flowing Fermi-FET devices allow for higher integration densities and / or higher speeds for logic, memory, microprocessor and other integrated circuit devices. Therefore, U.S. Pat. No. 5,374,836 entitled "High Current Fermi-Threshold Field Effect Transistor" by Albert W. Vinal and Michael W. Dennen of the present inventor is identical to the Fermitab and source regions. A Fermi-FET is described that includes a conductivity type implanted region adjacent to the source region and facing the drain region. The implanted region is preferably doped to a doping level intermediate between the relatively low doping concentration of Fermitab and the relatively high doping concentration of the source. The injection region controls the depth of carriers injected into the channel at a predetermined depth below the gate, and increases the injection of carriers in the channel. The transistor according to U.S. Pat. No. 5,374,836 is referred to herein as a "large current Fermi FET".
[0007]
Preferably, the source implant region is a source implant tub region surrounding the source region. An implantation tab region for the drain is also provided. In order to reduce the pinch-off voltage of the Fermi-FET and increase the saturation current, a spacer on the gate side wall extending from the portion adjacent to the injection region of the source of the Fermi-FET to the portion adjacent to the gate electrode is also provided. A bottom leakage control region of the same conductivity type as the substrate is also provided.
[0008]
Compared to known FET devices, despite the fact that Fermi-FETs, low-capacitance Fermi-FETs and high-current Fermi-FETs have been greatly improved, there is a continuing need to improve the operation of Fermi-FETs at low voltages. Was. As is well known to those skilled in the art, there is now more emphasis on low-power portable and / or battery-powered devices that typically operate at supply voltages of 5 volts, 3 volts, 1 volt or less. I have.
[0009]
By lowering the operating voltage for a given channel length, the lateral electric field decreases linearly. At very low operating voltages, the transverse electric field is so low that carriers in the channel cannot reach saturation velocity. This results in a sharp drop in the available drain current. Due to the reduced drain current, the reduction in operating voltage is effectively limited in order to obtain an available current rate for a given channel length.
[0010]
To improve the operation of the tab FET at low voltages, US Pat. No. 5,543, entitled “Contoured-Tub Fermi-Threshold Field Effect Transistor and Method of Forming Same” by Michael W. Dennen, the inventor of the present application. , 654 describes a Fermi-FET comprising a contoured Fermi-tub region with non-uniform tub depth. In particular, the Fermitab is located deeper below the source and / or drain regions than below the channel region. For this reason, the junction of the tab substrate is located deeper below the source and / or drain regions than below the channel region. This reduces the diffusion capacitance when compared to a Fermi-tub with a uniform tab depth, so that a large saturation current is generated at a low voltage.
[0011]
In particular, a Fermi-threshold field effect transistor having a contoured-tub according to the '654 patent comprises a semiconductor substrate of a first conductivity type and a second conductivity type on a surface of the semiconductor substrate. Includes spaced source and drain regions. A channel region of the second conductivity type is also formed on the substrate surface between the spaced source and drain regions in the semiconductor substrate. The substrate surface in the semiconductor substrate also includes a tab region of the second conductivity type. The tab region extends to a first predetermined depth below at least one of the source and drain regions spaced from the substrate surface and to a second predetermined depth below the channel region from the substrate surface. Extend. The second predetermined depth is shallower than the first predetermined depth. Also included are the insulating layer of the gate and the source, drain and gate contacts. Substrate contacts are also included.
[0012]
The second predetermined depth, the depth of the shaped tub adjacent to the channel, is the depth of the Fermi-FET as defined in the aforementioned U.S. Pat. Nos. 5,194,923 and 5,369,295. It is preferable to select so as to satisfy the criteria. In particular, the second predetermined depth is selected such that the gate electrode produces a zero electrostatic field perpendicular to the substrate plane at the bottom of the ground potential channel. The second predetermined depth is further selected to generate a threshold voltage for the field effect transistor that is twice the Fermi potential of the semiconductor substrate. The first predetermined depth, i.e., the depth of the shaped tub region adjacent the source and / or drain, is such that when a zero bias is applied to the source and / or drain contacts, the source and / or drain region Preferably, the lower tab region is selected to be depleted.
[0013]
As the state of the microelectronics manufacturing technology has advanced, linewidth manufacturing has been reduced to nearly one micron or less. These linewidth reductions have led to "short channel" FETs with channel lengths of approximately 1 micron or less, and typically less than 1/2 micron with current processing technology.
[0014]
U.S. Pat. Nos. 5,194,923 and 5,369,295 Low Capacitance Fermi-FET, U.S. Pat. No. 5,374,836 High-Current Fermi-FET and U.S. Pat. No. 5,543,654. Provided is a short-channel FET that exhibits high-performance at a low voltage by using the tab-type Fermi FET provided. However, those of ordinary skill in the art will recognize that as line widths decrease, processing limitations may limit the dimensions and conductivity achievable in FET fabrication. For this reason, the processing conditions require re-optimization of the Fermi-FET transistors to accommodate these processing limitations on line width reduction.
[0015]
Reoptimization of Fermi-FET transistors to address processing limitations is described in the United States by Michael W. Dennen, inventor of the present application, entitled "Short Channel Fermi-Threshold Field Effect Transistors," assigned to the assignee of the present invention. It was provided in Patent No. 5,814,869. The disclosure of this patent is incorporated herein by reference. The short-channel Fermi-FET of U.S. Pat. No. 5,814,869 is referred to herein as a "short-channel Fermi-FET" and extends beyond the Fermi-tub in the depth direction and also in the lateral direction. And spaced apart source and drain regions. As the source and drain regions extend beyond the tub, a junction is formed with the substrate that can provide a charge sharing state. To compensate for this condition, the doping of the substrate is increased. Very small separation between the source and drain regions is desirable to reduce tub depth. This results in a change in the electrostatic field perpendicular to the substrate at the oxide: substrate interface when the gate electrode is at the threshold potential. In a typical long channel Fermi-FET transistor, this field is essentially zero. In short channel devices, the electric field is significantly lower than MOSFET transistors, but somewhat higher than long channel Fermi-FETs.
[0016]
In particular, a short channel Fermi-FET includes a semiconductor substrate of a first conductivity type and a tab region of a second conductivity type within the surface of the substrate and extending from the surface of the substrate to a first depth. The short channel Fermi-FET also includes spaced apart source and drain regions of the second conductivity type in the tub region. The spaced source and drain regions extend beyond the first depth from the surface of the substrate and extend laterally from themselves beyond the tub region.
[0017]
A second conductivity type channel region extends from the substrate surface to a second depth between the spaced source and drain regions such that the second depth is less than the first depth. Included in the tab area. At least one of the first and second depths is selected to minimize an electrostatic field perpendicular to the substrate surface from the substrate surface to the second depth when the gate electrode is at a threshold potential. You. For example, 10 in a conventional MOSFET ^Five When compared with an electrostatic field of V / cm or more, the short channel Fermi FET ^Four An electrostatic field of V / cm is generated. On the other hand, the tab FETs of U.S. Pat. Nos. 5,194,923 and 5,369,295 are nearly zero when compared to conventional MOSFETs. ^Three It produces an electrostatic field of less than V / cm (often much smaller). The first and second depths are selected to generate a threshold voltage for the field effect transistor that is twice the Fermi potential of the semiconductor substrate, and the carrier of the second conductivity type has a threshold voltage. When a voltage is applied to the gate electrode, a current can flow from the source region to the drain region at a second depth in the channel region. It is selected so that it can extend from the second depth toward the substrate surface without creating an inversion layer. The transistor further includes a gate insulating layer and source, drain and gate contacts. Substrate contacts are also included.
[0018]
With continuous improvements in the miniaturization of field effect transistors in integrated circuits, channel lengths have been reduced to well below one micron. The continued miniaturization of this transistor often requires extremely high doping levels in the substrate. The higher doping levels and lower operating voltages required to make the devices smaller increase the capacitance associated with the source and drain regions of both Fermi-FET and conventional MOSFET devices.
[0019]
In particular, when Fermi-FETs are scaled down to 1 micron or less, it is generally necessary to significantly reduce the tub depth due to the increased Drain Induced Barrier Lowering (DIBL) at the source. Unfortunately, despite the changes described above for short-channel Fermi-FETs, short-channel Fermi-FETs have desirable depths and doping levels to control drain-induced barrier lowering and transistor leakage. Dimensions can be reached that are difficult to manufacture. In addition, the high doping level in the channel reduces carrier mobility, thus reducing the high current advantage of Fermi-FET technology. The junction capacitance is increased due to the lower drain voltage and the higher doping level of the substrate.
[0020]
A short-channel Fermi-FET capable of overcoming these potential problems is called "Short Channel Fermi-Threshold Field Effect Transistors Including Drain Field Termination Region and Methods of Fabricating Same", which is assigned to the assignee of the present invention. No. 5,698,884, issued to the present inventor by Michael W. Dennen. The disclosure of this patent application is incorporated herein by reference. The Fermi-FET includes a drain field terminating means between the source and drain regions to reduce, and preferably prevent, injection of carriers from the source region into the channel as a result of the drain bias. . The short-channel Fermi-FET including the drain field terminating means is referred to as “Vinal-FET” in the memory of the inventor of the Fermi-FET, which is now reduced, and the vertical Fermi-FET in the channel like the Fermi-FET. Prevents excessive drain-induced barrier reduction while permitting lowering of the electric field. Further, this vinyl FET can make the mobility of carriers extremely high, and at the same time can greatly reduce the junction capacitance of the source and the drain.
[0021]
The drain field termination means may be embodied by a buried contra-doped layer extending between the source region and the drain region below the substrate surface from the source region to the drain region. preferable. In particular, the vinyl FET includes a semiconductor substrate of a first conductivity type and a tab region of a second conductivity type on a surface in the substrate. The spaced apart source and drain regions of the second conductivity type are included in tub regions on the substrate surface. A buried drain field termination region of the first conductivity type is also included in the tub region. The buried drain field termination region extends below the substrate surface from the source region to the drain region. Also included are a gate insulating layer and source, drain and gate electrodes. For this reason, a vinyl FET is considered a Fermi-FET with a contra-doped and buried drain field termination region that prevents carriers from being injected from the source region into the tub region due to drain bias.
[0022]
As the channel length and integration density of field effect transistors in integrated circuits increase continually, the operating voltage of the transistors also decreases. This voltage drop is further stimulated by the increased use of integrated circuits in portable electronic devices such as laptop computers, cell phones, personal digital assistants, and the like. It is generally desirable to lower the threshold voltage because the operating voltage of the field effect transistor will decrease.
[0023]
Therefore, in order to provide a short-channel Fermi-FET operating at a low voltage, it is desirable to lower the threshold voltage to, for example, about 1/2 volt or less. However, it is necessary that the lowering of the threshold voltage does not cause performance degradation in other regions of the Fermi-FET. For example, the leakage current of the Fermi-FET must not be excessively increased and the saturation current of the Fermi-FET must not be reduced more than necessary due to the decrease in the threshold voltage.
[0024]
Fermi-FETs capable of low voltage operation have been published by Dennen and William R. Richards of the present inventor, entitled `` Metal Gate Fermi-Threshold Field Effect Transistors, '' assigned to the assignee of the present invention. PCT Application No. WO 99/17371. The disclosure of this application is incorporated herein by reference. As described therein, the Fermi threshold field effect transistor includes a metal gate. Contra-doped polysilicon gates are not used directly for the gate insulating layer. A metal gate can lower the threshold voltage of a Fermi-FET without degrading other desirable properties of the Fermi-FET. The metal gate is preferably made of a metal having a work function between P-type polysilicon and N-type polysilicon. More preferably, the metal gate is comprised of a metal having a work function of about 4.85 volts, ie, an intermediate work function between that of P-type polysilicon and N-type polysilicon.
[0025]
Undesirable short channel effects continue to increase as the channel length of field effect transistors is continually reduced, for example to dimensions below 1 micron and below 1/10 micron. In an attempt to reduce short channel effects, it is desirable to create very shallow source and drain regions. However, as it becomes increasingly difficult to make shallow source / drain regions, short channel effects will play an increasing role in degrading the performance of Fermi-threshold field effect transistors.
DISCLOSURE OF THE INVENTION
[0026]
[Summary of the Invention]
Embodiments of the present invention include a Fermi threshold field effect transistor (Fermi FET) including a trench in the tub region and an insulated gate electrode in the trench. These transistors are referred to herein as trench gated Fermi-FETs and can reduce short channel effects without having to make the source and drain profiles very shallow. High breakdown voltages and / or low source and drain parasitic capacitances are also provided.
[0027]
A field effect transistor according to an embodiment of the present invention includes a first conductivity type semiconductor substrate having a surface. A tub region of the second conductivity type is at a surface within the semiconductor substrate and extends into the semiconductor substrate from the first surface to a first depth. Source and drain regions spaced apart of the second conductivity type are included on the surface of the tub region of the second conductivity type and a single conductivity type tab region with the tub region of the second conductivity type. Form a conductive junction. These spaced source and drain regions extend into the tub region to a second depth that is less than the first depth. The trench is included in the tub region between the spaced source and drain regions and extends from the surface into the tub region to a third depth greater than the second depth but less than the first depth. . An insulated gate electrode is included in the trench. Source and drain electrodes in electrical contact with the source and drain regions, respectively, are provided on the surface.
[0028]
In some embodiments, at least one of the first, second and third depths is selected such that at a third depth the electrostatic field perpendicular to the surface is zero. In another embodiment, at least one of the first, second and third depths is perpendicular to the surface at the third depth when the threshold voltage of the field effect transistor is applied to the insulated gate electrode. Is selected so that the appropriate electrostatic field is zero.
[0029]
In yet another embodiment, the first, second, and / or third depths are selected to produce an electrostatic field of less than 700 V per centimeter perpendicular to the surface at the third depth. . In other embodiments, the first, second, and / or third depths are greater than an electrostatic field generated by a field effect transistor that is perpendicular to the surface at the third depth and that does not include a tub region. Are selected to generate an electrostatic field at least one order of magnitude smaller. In yet another embodiment, at least one of the first, second and third depths is equal to one of the electrostatic fields generated by the field effect transistor without the tub region perpendicular to the surface at the third depth. / 2 is selected to generate an electrostatic field smaller than / 2. In yet another embodiment, at least one of the first, second and third depths is equal to one of the electrostatic fields generated by the field effect transistor without the tub region perpendicular to the surface at the third depth. It is selected to generate an electrostatic field smaller than / 5. In another embodiment, these electrostatic fields are generated perpendicular to the surface at a third depth when the threshold voltage of the field effect transistor is applied to the insulated gate electrode.
[0030]
In yet another embodiment, the first, second, and / or third depths are selected to generate a threshold voltage for the field effect transistor that is twice the Fermi potential of the semiconductor substrate. .
[0031]
In yet another embodiment, at least one of the first, second, and third depths is below the third depth of the trench when the threshold voltage of the field effect transistor is applied to the gate electrode. It is selected so that carriers of the second conductivity type can flow into a certain tub region. In yet another embodiment, at least one of the first, second, and third depths is below the trench when a voltage exceeding a threshold voltage of the field effect transistor is applied to the gate electrode, The carrier of the second conductivity type is selected to be able to flow into the tub region extending from the depth of 3 to the first depth.
[0032]
In yet another embodiment, the trench forms a trench width and the first, second, and / or third depths are such that the channel width is proportional to the trench width in the tub region under the trench. And to form a channel that is independent of the difference between the first and second depths. In yet another embodiment, at least one of the first, second, and third depths is below the trench to deplete the tub region from the third depth to the first depth. Is selected.
[0033]
In yet another embodiment, the trench includes a trench floor and the insulated gate has a gate electrode on an insulating layer having a thickness on the trench floor and an insulating layer opposite the trench floor. Including. The first, second, and / or third depths are selected to produce a threshold voltage for the field effect transistor that is independent of the thickness of the insulating layer on the trench floor. In yet another embodiment, the trench forms a trench width, and at least one of the first, second, and third depths is determined by applying a threshold voltage of the field effect transistor to the gate electrode. Selected to form a channel at In this case, the channel is confined to the underside of the trench, extends across the trench width, and has a uniform thickness over the trench width underneath the trench.
[0034]
In yet another embodiment, the third depth is less than the first depth by an amount equal to:
(Equation 4)

Where N _d Is the doping concentration of the tub region, N _a Is the doping concentration of the semiconductor substrate, N _i Is the intrinsic carrier concentration of the substrate at the temperature T Kelvin, ε _s Is the dielectric constant of the substrate, q is 1.6 × 10 ^-19 Coulomb and k are 1.83 × 10 ^{-twenty three} Jules / Kelvin.
[0035]
The semiconductor substrate in all of the above-described embodiments is substantially at the surface itself in the semiconductor substrate of the second conductivity type, and the tab region of the second conductivity type is provided at the surface thereof. The first conductivity type well region may be in the first conductivity type well region and extend into the well region from the surface to a first depth.
[0036]
Further, in all the semiconductor substrates described above, the insulated gate electrode can be recessed from the surface in the trench. In some embodiments, the insulated gate electrode minimizes the capacitance between the insulated gate electrode and the spaced source and drain regions without reducing the drain current in the field effect transistor The amount is recessed from the surface.
[0037]
In yet another embodiment, the semiconductor substrate is doped to a first conductivity type at a first doping concentration and the tub region is doped to a second conductivity type at a second doping concentration. At least one of the first, second, and third depths and the first and second doping concentrations are selected based on any of the previously described embodiments.
[0038]
The field effect transistor of the present invention is achieved by forming a second conductivity type tab region extending from the surface to a first depth in the semiconductor substrate at a certain surface in the first conductivity type semiconductor substrate. It is manufactured based on the embodiment. A source or drain region of the second conductivity type is formed on the surface of the tub region of the second conductivity type to form a single conductive junction of the second conductivity type with the tub region of the second conductivity type. . The source or drain region extends into the tub region to a second depth that is less than the first depth. A trench is formed in the source or drain region to form a source and drain region spaced therefrom. The trench extends from the surface into the tub region to a third depth that is greater than the second depth but less than the first depth. An insulated gate electrode is formed in the trench. Source and drain electrodes in electrical contact with the source and drain regions, respectively, are formed on the surface.
[0039]
In another embodiment, the source or drain region is formed before forming the tub region. In yet another embodiment, the trench is formed after forming the source or drain region and the tub region. In yet another embodiment, the insulated gate electrode is formed prior to forming the source and drain electrodes. In all the method embodiments described above, the first, second and third depths and / or the first and second doping concentrations have been described in any of the structural embodiments described above. To be selected. Further, as described above, the first conductivity type well region is formed in the second conductivity type semiconductor substrate, and the second conductivity type tab region is formed in the first conductivity type well region. It is formed. Finally, the insulated gate electrode is recessed from the surface, as described above.
[0040]
In these method embodiments, the source or drain region is formed by implanting ions of the second conductivity type at a large tilt angle into the semiconductor substrate. As a result, a shallow source or drain region can be formed. However, since the gate electrode is formed after forming the source or drain region, it does not cause a positioning error. Thus, the gate electrode does not act to block the source or drain implantation. Further, an insulated gate electrode is formed by covering the trench with an insulating layer and forming the gate electrode in the trench covered with the insulating layer. The gate electrode is formed by forming the gate electrode layer on the substrate and in the trench, planarizing the gate electrode layer, and removing the gate electrode layer from the surface. Following planarization, the gate electrode is recessed from the surface.
[0041]
The (third) depth of the trench is determined by forming a trench-gate Fermi-FET field effect transistor and measuring its parameters. Further, the depth of the trench can be determined by simulation. Using experimental methods to determine the depth of a trench according to embodiments of the invention, by determining a series of capacitance versus voltage measurements on a series of sites having a tub region and a source or drain region therein. You can also decide. In this case, different amounts of source or drain regions are etched at a series of sites. These sites can be on a single wafer or on multiple wafers. The depth of the trench can be determined by determining the maximum depth at which the maximum capacitance can be obtained at a negative voltage.
BEST MODE FOR CARRYING OUT THE INVENTION
[0042]
[Detailed description of preferred embodiments]
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Throughout, the same numbers refer to similar elements. When an element, such as a layer, region, or substrate, is said to be "on" another element, it is understood that the element is directly on top of another element, or that there may be intervening elements present. Let's do it. On the other hand, if one element is said to be "directly on" another element, then there are no intervening elements.
[0043]
Prior to describing the trench-gate Fermi-threshold field effect transistor of the present invention, the Fermi-threshold field with reduced gate and diffusion capacitances of U.S. Patent Nos. 5,194,923 and 5,369,295. The effect transistor (sometimes referred to as a "low capacitance Fermi FET" or "tab FET") is described as a high current Fermi threshold field effect transistor in U.S. Patent No. 5,374,836. A shaped tab Fermi-FET according to U.S. Patent No. 5,543,654 is also described. The short channel Fermi-FET of U.S. Pat. No. 5,814,869 is also described. The vinyl FET of U.S. Pat. No. 5,698,884 is also described. A metal gated Fermi-FET in published PCT application WO 99/17371 is also described. A more complete description can be found in these patents and patent applications. These disclosures are incorporated herein by reference. Next, a trench gate type Fermi FET according to an embodiment of the present invention will be described.
[0044]
[Fermi FET with reduced gate capacitance and diffusion capacitance]
The following summarizes a low-capacity Fermi-FET including a Fermi-tab. Further details can be found in U.S. Patent Nos. 5,194,923 and 5,369,295.
[0045]
Conventional MOSFET devices require that an inversion layer be created on the surface of the semiconductor to support carrier conduction. The inversion layer depth is generally less than 100 °. Under these circumstances, the gate capacitance is essentially the dielectric constant of the gate insulator layer divided by its thickness. In other words, the charge in the channel is very close to the surface, so the effect of the dielectric properties of the substrate is not important in determining the gate capacitance.
[0046]
If the conduction carriers are confined in the channel region below the gate, the gate capacitance can be reduced. In this case, the average depth of the channel charge needs to include the dielectric constant of the substrate in order to calculate the gate capacitance. Generally, the gate capacitance of a low-capacitance Fermi-FET is represented by the following equation.
(Equation 5)

Where Y _f Is the depth of the conduction channel, called the Fermi channel, ε _s Is the dielectric constant of the substrate, and β is a coefficient that determines the average depth of charge flowing in the Fermi channel below the substrate. β depends on a profile that depends on the depth of carriers injected from the source into the channel. For a low capacitance Fermi FET, β is approximately 2. T _ox Is the thickness of the oxide film of the gate, ε _i Is the dielectric constant.
[0047]
The low-capacitance Fermi-FET includes a Fermi-tub region having a predetermined depth and a conductivity type opposite to that of the substrate and the same as that of the drain and source regions. The Fermi-tub extends downward a predetermined depth from the substrate surface, and the drain and source diffusions are formed within Fermi-tub boundaries in the Fermi-tub region. The preferred Fermi-tab depth is the Fermi-channel depth Y _f And depletion depth Y ₀ Is the sum of Predetermined depth Y _f And a Fermi channel region of width Z extends between the source and drain diffusions. The conductivity of the Fermi channel is controlled by the voltage applied to the gate electrode.
[0048]
The gate capacitance is determined by the Fermi channel depth and the carrier distribution in the Fermi channel and is relatively independent of the gate oxide thickness. Conversely, the diffusion capacity is determined by the Fermi-tub depth and the depletion depth Y in the substrate. ₀ Total depth and diffusion part X _d Depends on the difference between the depth. The diffusion depth is the Fermitab depth Y _T It is preferable to be shallower than that. The dopant concentration for the Fermi-tub region is preferably selected so that the depth of the Fermi-channel can be greater than three times the depth of the inversion layer in the MOSFET.
[0049]
Therefore, the low-capacitance Fermi-FET has a semiconductor substrate of a first conductivity type having a first surface, a Fermi-tub region of a second conductivity type on a first surface in the substrate, and a first substrate in a Fermi-tub region of the second conductivity type. A second conductivity type spaced source and drain region on the surface of the substrate and a second conductivity type channel between the spaced source and drain regions in the Fermi-tub region. The channel has a first predetermined depth (Y _f ) And the tab extends from the channel to a second predetermined depth (Y ₀ ). A gate insulating layer is provided on the first surface between the spaced source and drain regions on the substrate. Source, drain and gate electrodes which are in electrical contact with the source region, the drain region and the gate insulating layer, respectively, are provided.
[0050]
At least the first and second predetermined depths are selected such that, when the threshold voltage of the field effect transistor is applied to the gate electrode, the electrostatic field perpendicular to the first surface at the first depth is zero. Is done. The first and second predetermined depths may also be such that, when a voltage exceeding a threshold voltage of the field effect transistor is applied to the gate electrode, carriers of the second conductivity type are shifted from the first predetermined depth to the first Is selected so that it can flow from the source to the drain in a channel extending toward the surface of the substrate. Carriers flow from the source region to the drain region below the first surface without forming an inversion layer in the Fermi-tub region. The first and second predetermined depths also provide a voltage equal in polarity but opposite to the sum of the voltages between the substrate contact and the substrate and between the polysilicon gate electrode and the gate insulating layer. Is selected to occur on the substrate surface adjacent to.
[0051]
Substrate has doping concentration N _s And a specific carrier concentration n at temperature T Kelvin _i Has a dielectric constant ε _s And a substrate contact for the field effect transistor to make electrical contact with the substrate, wherein the channel has a first predetermined depth Y from the surface of the substrate. _f Extending from the channel to a second predetermined depth Y ₀ And the Fermitab area is multiplied by a factor α _s And the gate electrode includes a layer of polysilicon of the first conductivity type and has a doping concentration of N. _p When doped with a first predetermined depth (Y _f ) Is represented by the following equation.
(Equation 6)

Here, q is 1.6 × 10 ^-19 Coulomb, K is 1.38 × 10 ^{-twenty three} Jules / Kelvin. The second predetermined depth is equal to:
(Equation 7)

Where φ _s Is 2φ _f + KT / qLn (α), and φ _f Is the Fermi potential of the semiconductor substrate.
[0052]
[Structure of large current type Fermi FET]
Referring now to FIG. 1, there is illustrated an N-channel, high-current Fermi-FET according to US Pat. No. 5,374,836. One skilled in the art will appreciate that a P-channel Fermi-FET can be obtained by reversing the conductivity of the N and P regions.
[0053]
As shown in FIG. 1, the large current type Fermi FET 20 is a P-type first conductivity type in this figure, and is manufactured in a semiconductor substrate 21 including a substrate surface 21a. In this figure, an N-type second conductivity type Fermi-tub region 22 is formed on a surface 21 a in a substrate 21. In this figure, N-type and second conductivity type source and drain regions 23 and 24, respectively, are formed on surface 21a in Fermi-tub region 22. Those skilled in the art will appreciate that the source and drain regions can also be formed in trenches in surface 21a.
[0054]
A gate insulating layer 26 is formed on the surface 21a of the substrate 21 between the spaced source and drain regions 23 and 24, respectively. As is well known to those skilled in the art, this gate insulating layer is typically silicon dioxide. However, silicon nitride and other insulators can also be used.
[0055]
A gate electrode is formed on the gate insulating layer 26 opposite the substrate 21. The gate electrode preferably includes a gate electrode layer 28 of polycrystalline silicon (polysilicon) of the first conductivity type of P type here. A conductive gate electrode layer, typically a metal gate electrode layer 29, is formed on the polysilicon gate electrode 28 opposite the gate insulating layer 26. Generally, a metal source electrode 31 and a drain electrode 32 are also formed on the source region 23 and the drain region 24, respectively.
[0056]
Here, the P-type first conductivity type substrate contact 33 is also formed in the substrate 21 either inside the Fermi-tub 22 or outside the tab 22 as shown. As shown, the substrate contact 33 includes a relatively highly doped region 33a and a relatively lightly doped region 33b that are doped to a first conductivity type, here P-type. The substrate electrode 34 establishes electrical contact with the substrate.
[0057]
The structure described so far with reference to FIG. 1 corresponds to the structure of the low capacitance Fermi-FET of US Pat. Nos. 5,194,923 and 5,369,295. As already described in these applications, a channel 36 is created between the source region 23 and the drain region 24. In FIG. 1, Y _f , The channel depth from the surface 21a, and in FIG. ₀ The depth from the bottom of the channel to the bottom of the Fermi-tub 22 and the doping levels of the substrate 21, the tub region 22, and the gate electrode 28 of polysilicon, which are expressed by the relations (1) and (2), Are selected to provide high performance, low capacitance field effect transistors.
[0058]
Still referring to FIG. 1, here, an N-type second conductivity type source implantation region 37 a is provided adjacent to the source region 23 toward the drain region. The source injection region provides a high current Fermi FET by controlling the depth at which carriers are injected into the channel 36. The source implantation region 37a extends only between the source region 23 and the drain region 24. The source implantation region preferably surrounds the source region 23 to form a source implantation tab region 37 as shown in FIG. The side and bottom surfaces of the source region 23 are completely surrounded by the source implantation tab region 37. Alternatively, the source region 23 is laterally surrounded by the source implanted tub region 37, but the bottom protrudes from the source implanted tub region 37. In yet another alternative, the source implant region 37a extends into the substrate 21 to the junction between the Fermi-tub 22 and the substrate 21. There is also provided a drain implant region 38a, preferably a drain implant tab region 38 surrounding the drain region 24.
[0059]
The source implantation region 37a and the drain implantation region 38a or the source implantation tub region 37 and the drain implantation tub region 38 have a doping level intermediate between the relatively low doping level of the Fermi-tub 22 and the relatively high doping level of the source 23 and the drain 24. Here, it is preferable to dope the N-type second conductivity type. For this reason, as shown in FIG. 1, the Fermi-tub 22 is indicated as N, and the source and drain implantation tab regions 37, 38 are N. ⁺ And the source and drain regions 23 and 24 are N ⁺⁺ Is shown. Thereby, a unijunction transistor is formed.
[0060]
High-current Fermi-FETs provide approximately four times the drive current of conventional FETs. Gate capacitance is about half that of a conventional FET device. The doping concentration of the source implant tub region 37 controls the depth of carriers injected into the channel region 36, typically to about 1000 Angstroms (100 nm). The doping concentration of the source implantation tub region 37 is generally 2E18 (2 × 10 ¹⁸ ) And preferably has a width at least as large as the desired maximum width of the injected majority carriers. Alternatively, as described below, it extends to the same depth as Fermi-tub region 22 to minimize sub-threshold leakage current. It will be shown that the carrier concentration injected into the channel 36 cannot exceed the doping concentration in the source injection region 37a facing the drain. The width of the part of the source implantation region 37a facing the drain is generally in the range of 0.05 to 0.15 μm. The doping concentration of the source and drain regions 23 and 24 is generally 1E19 (1 × 10 ¹⁹ ) That is all. Depth Y of Fermi-tab 22 _T = (T _f + Y ₀ ) Is about 2200 ° and the doping concentration is about 1.8E16 (1.8 × 10 ¹⁶ ).
[0061]
As shown in FIG. 1, the high-current Fermi-FET 20 also includes a gate sidewall spacer 41 extending from an adjacent source injection region 37a on the substrate surface 21a to an adjacent polysilicon gate electrode 28. The gate sidewall spacer 41 preferably also extends from the adjacent drain implant region 38a to the adjacent polysilicon gate electrode 28. In particular, as shown in FIG. 1, gate sidewall spacer 41 extends from sidewall 28a of the polysilicon gate electrode and overlies source and drain implant regions 37a and 38a, respectively. A gate sidewall spacer 41 preferably surrounds the polysilicon gate electrode 28. Preferably, as will be described later in detail, the gate insulating layer 26 extends over the source implantation region 37a and the drain implantation region 38a on the substrate surface 21a, and the gate sidewall spacer 41 also extends to the source implantation region 37 and the drain implantation region 38. Extend up.
[0062]
Gate sidewall spacer 41 reduces the pinch-off voltage of Fermi-FET 20 and increases its saturation current in a manner to be described in detail below. The gate side wall spacer is preferably an insulator having a dielectric constant higher than that of the gate insulating layer 26. Thus, for example, if the gate insulating layer 26 is silicon dioxide, the gate sidewall spacer is preferably silicon nitride. If the gate sidewall spacer 26 is silicon nitride, the gate sidewall spacer is preferably an insulator having a higher dielectric constant than silicon nitride.
[0063]
As shown in FIG. 1, gate sidewall spacers 41 also extend over source and drain regions 23 and 24, respectively, and source and drain electrodes 31 and 32, respectively, are formed within extensions of the gate sidewall spacer regions. . A conventional field oxide or other insulator 42 region separates the source, drain and substrate contacts. Those skilled in the art will also appreciate that although the outer surface 41a of the gate sidewall spacer 41 is shown as a curve in cross-section, other shapes may be used, such as a straight outer surface resulting in a triangular cross-section or an orthogonal outer surface resulting in a rectangular cross-section. Like.
[0064]
[Low leakage current type Fermi field effect transistor]
Reference is now made to FIGS. 2A and 2B. A short channel but low leakage current Fermi FET according to US Pat. No. 5,374,836 will now be described. These devices are hereinafter referred to as "low leakage current type Fermi-FET". The low leakage current Fermi-FET 50 of FIG. 2A includes a first conduction type bottom leakage current control region 51 that is P-type in this figure and heavily doped with respect to the substrate 21. For this reason, in FIG. ⁺ Is illustrated. The low leakage current Fermi-FET 60 of FIG. 2B includes extended source and drain injection regions 37a, 38a. These implanted regions preferably extend to the depth of Fermi-tub 22.
[0065]
Referring now to FIG. 2A, the bottom leakage current control region 51 extends across the substrate 21 from between the extensions of the facing ends of the source and drain regions 23 and 24 and extends above the depth of the Fermi-tub 22. Extending into the substrate from below the depth of the Fermi-tub. It is preferably located below and in alignment with the Fermi channel 36. To maintain consistency with the previously described equation, the depth from the Fermi channel 36 to the top of the bottom leakage current control region 51 is Y ₀ It is written. The remainder of the Fermi-FET transistor of FIG. 2A is the same as that described in FIG. 1, except that the channel is shown shorter. To provide a short channel Fermi-FET with low leakage current and low capacitance without the high current characteristics of the device of FIG. 2A, the implanted regions 37a and 38a and / or the implanted tabs 37 and 38 and the gate sidewall spacer region 41 are provided. Those skilled in the art will understand that they can be omitted.
[0066]
Bottom leakage current control region 51 minimizes drain induced injection in short channel Fermi field effect transistors, ie, field effect transistors having a channel length less than about 0.5 μm, while maintaining low diffusion depletion capacitance. For example, at 5 volts, 3E-13A (3 × 10 ^-13 A) The following leakage current is maintained.
[0067]
The bottom leakage current control region is designed using equations (2) and (3). Where Y ₀ Is the depth from the channel to the top of the bottom leakage current region, as shown in FIGS. 2A and 2B. The coefficient α is the value of P in the bottom leakage current control region 51. ⁺ It is the ratio between the doping and the N doping of Fermitab 22. Preferably, α is set to about 0.15 in the bottom leakage control region, ie, below the gate 28. Below the source and drain regions 23 and 24, α is set to about 1.0 to minimize diffusion depletion capacitance. In other words, the doping concentration of the substrate 21 and Fermi-tub 22 is approximately equal to the region under the source and drain. Thus, for the design parameters described above and for a channel width of 0.5 microns, the doping concentration in the bottom leakage control region 51 is about 5E17 (5 × 10 ¹⁷ ) Where the drain or source diffusion potential is 5 volts, deep enough to accommodate partial depletion in the tub junction region.
[0068]
Reference is now made to FIG. In another design for bottom leakage control, the depth of the source implant region 37a and the drain implant region 38a is preferably the Fermi-tub depth (Y _f + Y ₀ ). As shown in FIG. 2B, the total depth of the source implant tab 37 and the drain implant tab 38 preferably extends to the depth of the Fermi tub. The separation distance between the bottom of the injection tabs 37 and 38 and the bottom of the Fermi-tub 22 is preferably less than half of the channel length, more preferably about zero. Under these conditions, the doping concentration of implantation tabs 37 and 38 is about 1.5E18 / cm ^Three (1.5 × 10 ¹⁸ / Cm ^Three ). Preferably, the depth of the substrate contact region 33b is also extended until it reaches the depth of the Fermi-tub. The rest of the Fermi-FET transistor 60 of FIG. 2B is identical to that described in FIG. 1, except that the channel is shown shorter.
[0069]
[Shaped tab-shaped Fermi-threshold field-effect transistor]
Referring now to FIG. 3, an N-channel shaped tabbed Fermi-FET according to US Pat. No. 5,543,654 is illustrated. One skilled in the art will appreciate that a P-channel Fermi-FET can be obtained by reversing the conductivity of the N and P regions. As shown in FIG. 3, the shaped tab-shaped Fermi-FET 20 'is similar to that of FIG. 1 except that there is a shaped tab 22' instead of the tab 22 of FIG. This is the same as the current source Fermi-FET 20. The implantation tab and the implantation region are present but not shown.
[0070]
Still referring to FIG. The shaped tab 22 'has a first predetermined depth Y from the substrate surface 21a to at least one of the spaced source and drain regions 23, 24, respectively. ₁ Having. The shaped tab 22 'has a second predetermined depth T2 from the substrate surface 21a to below the channel region 36. According to the present invention, to create a shaped tab 22 ', Y _Two Is Y ₁ Unlike Y ₁ Less than. Stated another way, the junction between the tub 22 'and the substrate 21 is spaced apart from the source and drain regions 23 and 24, corresponding to the position indicated by the tub FET reference below the channel. Depressed to reduce the source or drain diffusion capacitance, thereby allowing the shaped tab Fermi-FET to operate at lower voltages. Those skilled in the art will appreciate that tab 22 'is shaped only under source region 23 or drain region 24, creating an asymmetric device. However, a symmetric device in which the tub is shaped below the source 23 and the drain 24 is also preferably formed.
[0071]
Second predetermined depth Y _Two Is selected based on the criteria for low capacitance Fermi-FETs (tab FETs) of US Pat. Nos. 5,194,923 and 5,369,295. Depth Y _f And Y ₀ And a second predetermined depth Y _Two These criteria for forming are described above.
[0072]
A first predetermined depth (Y ₁ ) Is the second predetermined depth Y _Two Is selected to be larger than The first predetermined depth is equal to the first predetermined depth Y when zero voltage is applied to the source contact 31 and the drain contact 32, respectively. ₁ It is also preferably selected to deplete the tub region 22 'between the gate region and the source and / or drain region. Therefore, Y _n Is preferably fully depleted under a source bias or drain bias, respectively, of zero. Based on this criterion, Y ₁ Is determined by the following equation:
(Equation 8)

Where N _sub Is the doping concentration of the substrate 21 and N _tub Is the doping concentration of the shaped tub 22 '.
[0073]
[Short channel Fermi FET]
Referring now to FIG. 4, there is shown a short channel, N-channel Fermi-FET 20 "according to U.S. Pat. No. 5,814,869. One skilled in the art will appreciate that the conductivity of the N and P regions can be reversed. It can be understood that a P-channel Fermi-FET can be obtained from the substrate surface 21a by a first depth (Y) as shown in FIG. _f + Y ₀ ). Source and drain regions 23 and 24, respectively spaced apart, are located in the tub region, as indicated by regions 23a and 24a. However, the source or drain regions 23 and 24, respectively, also extend beyond the tub depth from the substrate surface 21a. Source or drain regions 23 and 24 also extend laterally beyond the tub region in a direction along substrate surface 21a.
[0074]
Channel depth Y _f And the tab depth Y from the channel ₀ Is the depth Y from the substrate surface when the gate electrode is at the threshold potential. _f Is selected to minimize the electrostatic field perpendicular to the substrate surface in the channel 36 to the substrate. As already explained, these depths are preferably chosen so as to generate a threshold voltage of twice the Fermi potential of the semiconductor substrate 21 for the field effect transistor. When a voltage exceeding the threshold voltage of the field effect transistor is applied to the gate electrode, these depths become _f Is selected so that carriers of the second conductivity type can flow from the source region to the drain region in a channel region extending from the substrate region to the substrate surface 21a. The carriers flow from the source region to the drain region in the channel region below the substrate surface without forming an inversion layer in the channel. Thus, although not optimally, the device of FIG. 4 can generate much higher saturation current than conventional MOSFET transistors, significantly reducing the off-state gate capacitance. The drain capacitance will be similar to a standard MOSFET device.
[0075]
In FIG. 4, it will be understood that the source or drain region extends beyond the tub region in a depth direction perpendicular to the substrate surface 21a and in a lateral direction parallel to the substrate surface 21a. However, to reduce sidewall parasitic capacitance, the tabs 22 "preferably extend laterally beyond the source and drain regions so that the source and drain regions protrude through the tabs in the depth direction.
[0076]
Referring now to FIG. 5, there is shown a second embodiment of a short channel Fermi-FET according to US Pat. No. 5,814,869. Transistor 20 "'has source and drain extension regions 23b and 24b provided adjacent to source and drain regions 23' and 24 ', respectively, extending into channel 36 on substrate surface 21a in substrate 21. Except for this, it is the same as the transistor 20 ″ of FIG.
[0077]
As shown in FIG. 5, the source and drain extension regions 23b and 24b are each highly doped (N) to approximately the same doping concentration as the source and drain regions 23 'and 24', respectively. ⁺⁺ ) Is done. It will be appreciated that extensions 23b and 24b are not lightly doped as in the lightly doped drain structure of a conventional MOSFET device. Rather, it is preferable to dope them with the same doping concentration as the source and drain regions and to dope as high as practical in order to reduce leakage and increase saturation current.
[0078]
The source and drain extension regions 23b and 24b reduce the drain voltage sensitivity due to the charge sharing described above. Unfortunately, the device of FIG. 5 does not typically exhibit as low capacitance as the fully enclosed source and drain regions of FIGS. In order to maintain the dimensions of the source or drain extension regions 23b and 24b, a heavy and slowly moving dopant such as arsenic or indium should be used instead of the light and fast moving element commonly used for the source and drain itself. It will be understood by those skilled in the art that the use of the extension region is preferable.
[0079]
[Short channel type Fermi FET including drain field termination]
The architecture of a short channel Fermi-threshold field effect transistor including a drain field termination region according to U.S. Patent No. 5,698,884, also referred to herein as a vinyl FET, is described herein. Those skilled in the art will appreciate that by inverting the conductivity of the N and P regions, a P-channel vinyl FET can be obtained.
[0080]
FIGS. 6 and 7 show the first and second embodiments of the vinyl FET, respectively. As shown in FIG. 6, the vinyl FET 60 includes a P-type first conductivity type semiconductor substrate 21 in this figure. One skilled in the art will appreciate that since the semiconductor substrate 21 also includes one or more epitaxial layers formed on the bulk semiconductor material, the substrate surface 21a is in fact the outer surface of the epitaxial layer rather than the outer surface of the bulk semiconductor material. Like.
[0081]
Still referring to FIG. 6, a first tab region 62 of a second conductivity type (here, N-type) is formed on surface 21a on substrate 21 and has a first depth Y from substrate surface 21a. _Three Extends. Here, a second tub region 64 of a P-type first conductivity type is included in the first tub region 62. The second tab region 64 is formed at a second depth Y from the substrate surface 21a. _Two Extend into the substrate up to. Second depth Y _Two Is the first depth Y _Three Shallower than. The second tab area 64 in the first tab area 62 also extends laterally beyond the first tab area 62. The second tub region 64 forms a drain field termination (DFT) region, as described below. Here, the third tab region 66 of the N-type second conductivity type is included in the second tab region 64. The third tab 66 has a third depth Y from the substrate surface. ₁ Only extends into the substrate 21. Here, the third depth Y ₁ Is shallower than the second depth. The third tub 66 is preferably formed in the epitaxial layer, as described below.
[0082]
Still referring to FIG. 6, the second conductivity type (here, N ⁺ The source and drain regions 23 and 24, respectively, are formed in the first tub region 62 and have a fourth depth Y from the substrate surface 21a into the substrate. _Four Extending to As shown in FIG. 6, this fourth depth Y _Four Is the third depth Y ₁ Deeper than. As shown in FIG. 6, the fourth depth Y _Four Is the second depth Y _Two Deeper, but shallower than the first depth. Thus, the source and drain diffusions 23 and 24, respectively, extend through the third and second tabs 66 and 64 and into the first tab 62, respectively. In the second embodiment of the vinyl FET 60 'as shown in FIG. 7, the fourth depth Y _Four Is the third depth Y ₁ Deeper than the second depth Y _Two Because it is shallower, the source and drain regions extend through the third tub 66 and into the second tub 64, but do not enter the first tub 62.
[0083]
6 and 7 respectively also include a gate electrode including a gate insulating layer 26 and a polycrystalline silicon layer 28 of a first conductivity type, here P-type. Source, gate and drain contacts 31, 29 and 32 are also included as previously described. Substrate contacts 34 are also included. This substrate contact is shown on the opposite side of the surface 21a, but can also be provided adjacent to the surface 21a, as in the previous embodiment.
[0084]
6 and 7 can also be described in terms of layers in the substrate 21 that extend between the source region 23 and the drain region 24. Considered in this regard, the third tub 66 extends from the source region 23 to the drain region 24 on the substrate surface in the substrate and has a first depth Y from the substrate surface. ₁ A first layer 66a of the second conductivity type extending into the substrate up to is formed. The second tub 64 extends from the source region 23 to the drain region 24 and has a first depth Y from the substrate surface. ₁ From the second depth Y _Two A second layer 64a of a first conductivity type extending into the substrate up to the substrate is formed in the substrate. The second layer 64a operates as a drain field terminating means, as will be described later. The first tub 62 extends from the source region to the drain region and has a second depth Y from the substrate surface. _Two From the third depth Y _Three A third layer 62a of the second conductivity type extending into the substrate up to the substrate is formed in the substrate.
[0085]
Observed in this manner, in the embodiment of FIG. 6, the third layer 62a extends from the source bottom 23a to the drain bottom 24a, as indicated by region 62b. In the embodiment of FIG. 7, the second and third layers 64a and 62a, respectively, both extend from the source bottom 23a to the drain bottom 24a, as shown by regions 64b and 62b.
[0086]
6 and 7 can also be considered as a tab FET that includes a tub 64 that is contradoped and embedded in the original tub. In yet another alternative, the vinyl FET can be considered a tab FET that includes a buried layer 64a of the first conductivity type below the channel region 66a. As will be described in greater detail below, the second tub 64, including the second layer 64a, acts as a drain field termination (DFT) means so that the applied drain bias causes carriers to move from the source region into the channel region or into the channel region. The source region is shielded by preventing it from being implanted below the region. Therefore, the second tub 64 and the second layer 64a can also be referred to as a drain field termination (DFT) region.
[0087]
The operation of the vinyl FETs 60 and 60 'of FIGS. 6 and 7 has been described in detail in U.S. Pat. No. 5,698,884 and will not be described again here.
[0088]
[Metal gate type Fermi FET transistor]
According to published PCT application WO 99/17371, by using metal gates instead of contra-doped polygates for Fermi-FETs, excessively increasing leakage current and / or more than necessary The threshold voltage of the Fermi-FET transistor can be reduced without reducing the saturation current.
[0089]
FIG. 8 shows an embodiment of a metal gate Fermi-FET. This embodiment is patterned after the N-channel short-channel Fermi-FET of US Pat. No. 5,543,654 shown in FIG. 4 of the present application. However, those skilled in the art will recognize that metal gated Fermi-FET technology can be applied to all Fermi-FETs to lower its threshold voltage.
[0090]
As shown in FIG. 8, the metal gate Fermi-FET 110 includes a metal gate 28 'instead of the P-type polysilicon gate 28 and the metal gate electrode layer 29 of FIG. All other elements of transistor 110 are unchanged from FIG. 4 for ease of explanation. Thus, as shown in FIG. 11, the metal gate 28 ′ is included directly on the gate insulating layer 26. Stated another way, the metal gate 28 'of the Fermi-FET 110 does not include doped polysilicon disposed directly on the gate insulating layer. Therefore, the contact potential is not controlled by the Fermi potential of polysilicon. It will be appreciated that the metal gate includes a plurality of layers, and that the layer disposed directly on the gate insulating layer does not include doped polysilicon.
[0091]
Specifically, metals, silicides, or other metal alloys whose work functions are approximately in the center of the silicon bandgap significantly reduce the Fermi-FET threshold without excessively increasing deleterious two-dimensional effects. be able to.
[0092]
Materials with a work function of about 4.85 V are particularly preferred for Fermi-FET structures because they can result in symmetric N-channel and P-channel doping. Other materials may be used to provide relatively low thresholds for N or P channel devices, depending on the desired performance. It is preferable to use a metal or metal alloy having a work function between P-type silicon and n-type silicon.
[0093]
[Trench gate type Fermi FET transistor]
Referring now to FIG. 9, a cross-sectional view of an N-channel trench-gate Fermi-FET 90 according to an embodiment of the present invention is shown. Those skilled in the art will appreciate that by inverting the conductivity of the N and P regions, a P-channel trench gated Fermi-FET can be obtained. As shown in FIG. 9, these embodiments include a semiconductor substrate 121 of a first conductivity type, here P-type, having a surface 121a. It will be appreciated that the substrate 121 is actually a first conductivity type well region in the N-type second conductivity type substrate 133 here. In particular, an N-channel trench-gate Fermi-FET is generally formed in a P-type well 121 in an N-type substrate 133, whereas a P-channel trench-gate Fermi-FET requires a well region. Instead, it is formed in an N-type substrate. It will also be appreciated that both N-type and P-type trench gated Fermi-FETs can be integrated into a single semiconductor substrate, often referred to as a CMOS substrate. Finally, because substrate 133 and / or well region 121 also includes one or more epitaxial layers formed over the bulk semiconductor material, substrate surface 121a is not actually the outer surface of the bulk semiconductor material, but rather the epitaxial surface. Those skilled in the art will appreciate that it is the outer surface of the layer.
[0094]
9, a N-type second conductivity type tab region 122, also referred to as Fermi-tub, is provided on the surface 121a in the semiconductor substrate 121 and has a first depth X from the surface 121a. _i Extending into the semiconductor substrate. Here, N-type second conductivity-type source and drain regions 123 and 124 are also provided on the surface 121 in the tub region 122, respectively. As shown in FIG. 9, the source and drain regions 123 and 124 form a single conductive junction or unijunction of the second conductivity type, here N-type, with the tub region 122. These spaced source and drain regions are N ⁺⁺ Highly doped as shown by the first depth X _i Second shallower depth X _j Extends into the tab area 122 to
[0095]
A trench 134 is provided in the tub region 122 between the spaced source and drain regions 123 and 124 and a third depth X from the surface 121a into the tub region 122. _Three Extending to This third depth X _Three Is the second depth X _j Deeper than the first depth X _i Shallower than. Although trench 134 is shown in FIG. 9 with a rectangular cross section, many other shapes of cross section may be used, such as a U, V or rectangular cross section with rounded corners. An insulated gate electrode including a gate electrode 128 and a gate insulating layer 126 is provided in the trench 134. The gate electrode 128 has a width L _d And a quantity X below the source or drain region 123/124. _d Extending above the source and drain regions by a quantity X _o Extend to.
[0096]
The source and drain electrodes 131 and 132 are provided, for example, on a surface 121a that is in electrical contact with the source and drain regions 123 and 124, respectively. An insulating region 142 is provided to separate the source and drain electrodes 131 and 132. Substrate contacts are also provided on surface 121a and / or on the opposite surface of the substrate. Finally, as shown in FIG. 9, the substrate (or well) 121 has a doping concentration N _a And the tub 122 has a doping concentration of N _d Doped with
[0097]
Still referring to FIG. According to an embodiment of the present invention, the distance Y between the tub and the floor of the trench ₀ Is the first depth X _i From the third depth X _Three And is set based on equation (5) as follows:
(Equation 9)

Where N _d Is the doping concentration of the tub 122, which varies, but preferably is the average doping concentration of the tub 122 between the trench floor and the substrate 121. N _a Is the doping concentration of the substrate or well, N _a Varies, but is preferably the doping concentration at a position below the gate 128 and adjacent to the tub 122. n _i Is the intrinsic carrier concentration of the material at the temperature T Kelvin. ε _s Is the dielectric constant of the material (for silicon, k is 1.38 × 10 ^{-twenty three} Jules / Kelvin). And q is 1.6 × 10 ^-19 Coulomb.
[0098]
Equation (5) may define the length of the depletion region in the tub 122 below the trench 134. This depletion region has a third depth X _Three From the first depth X _j It is preferable to extend so as to completely deplete the tub region 122 under the trench 134.
[0099]
In an embodiment of the present invention, Y ₀ Is exactly equal to the distance defined in equation (5), the threshold voltage of the trench-gate Fermi-FET will be equal to the difference in work function between the silicon substrate and the gate material. In other words, the threshold value of the transistor is twice the Fermi potential of the substrate. This results in a device having the lowest possible vertical electric field in the channel region, which is zero at the threshold voltage of the device. Therefore, when the threshold voltage of the field effect transistor is applied to the insulated gate electrode, the third depth X _Three A zero static electric field perpendicular to the surface of the substrate occurs. Proper selection of the appropriate gate material results in thresholds of less than a few millivolts to more than 1 volt, while still satisfying the criteria of equation (5) that can make "ideal" trench gated Fermi-FET transistors. Can occur as
[0100]
Adjusting the transistor threshold to either above or below the "ideal" value is possible with only a small increase in the vertical electric field. Therefore, the vertical electric field is maintained at least one order of magnitude smaller than the magnitude of the electric field generated by the field effect transistor not including the tab region 122. In other embodiments, the electric field is less than half the electric field generated by a field effect transistor that does not include tab region 122. In yet another embodiment, the vertical electric field is less than 1/5 of the electric field generated by a field effect transistor that does not include tab region 122. In yet another embodiment, the electrostatic field is less than 700 V / cm, which is comparable to a conventional field effect transistor with a longitudinal electric field between about 10,000 V / cm and about 100,000 V / cm. Can be. Y ₀ Can be increased from the value defined in equation (5) to increase the vertical electric field. Y ₀ By increasing the threshold value of the device can be reduced to zero.
[0101]
Conventional surface channel transistors and conventional buried channel field effect transistors generally have strong threshold sensitivity to gate insulator thickness. In sharp contrast, in the Fermi-FET transistor embodiment, the threshold voltage is independent of the thickness of the insulating layer 126 on the trench floor because there is little or no sensitivity to gate insulator thickness. Remains. This is due to the fact that at threshold voltage the electric field of the insulator passes through zero very close to the threshold voltage and switches from negative to positive.
[0102]
10A and 10B graphically illustrate gate bias versus gate insulator (eg, oxide) electric field applied to a trench gated Fermi FET transistor and a conventional surface channel transistor, respectively. 10A and 10B, and in all subsequent simulation results, the simulation was performed on a transistor having the following characteristics.
Drain channel length, L _d = 0.18 μm;
Gate oxide (insulator) thickness, T _ox = 35 °;
Operating drain voltage, V _d = 2.5 volts;
Leakage current (at 1.8V), I _dss = 20 pA / μm
As shown in FIG. 10A, regardless of the thickness of the gate insulator, the electric field of the trench-gate Fermi-FET is low and the threshold value is one. In contrast, as shown in FIG. 10B, the conventional surface channel transistor has a high electric field and the threshold value is highly dependent on the gate oxide thickness.
[0103]
Further, for example, as described in US Pat. No. 4,835,585 to Panousis, US Pat. No. 5,108,938 to Solomon and US Pat. No. 5,142,640 to Iwamatsu, Conventional trench gate type field effect transistors show a strong dependence of the threshold voltage on the thickness of the gate insulator. In other words, in a device other than a Fermi-FET, the threshold voltage is high in a region where the dielectric is thick, such as a corner or a vertex of the trench, so that the channel is not formed uniformly in the trench. In sharp contrast, trench-gate Fermi-FETs according to embodiments of the present invention can have a uniform threshold across the device, regardless of the gate insulator thickness at the apex.
[0104]
As shown in FIGS. 10A and 10B, the sensitivity of the threshold voltage to the thickness of the gate dielectric can be extremely low in the trench gate type Fermi FET according to the embodiment of the present invention. This allows the entire channel to operate as one, which translates into high G _m And very rapid operation can be provided. In sharp contrast, the threshold sensitivity to oxide thickness of surface channel devices and conventional buried channel transistors is significantly higher. The thicker dielectric that occurs near the top of the trench will cause the transistor to operate first in a thinner area, even if the trench is rectangular, rounded rectangular, V-shaped or U-shaped, and then later in a thicker area. , The on-resistance is increased, and the swing below the threshold (subthreshold swing) and G _m Decrease.
[0105]
11A and 11B are cross-sectional views of embodiments of a trench-gate Fermi-FET transistor and a conventional trench-gate MOSFET transistor, respectively, illustrating and contrasting the formation of a channel therein. In FIGS. 11A and 11B, all the source, drain and gate electrodes are at 0 V, so the device is off. As shown in FIG. 11A, a depletion layer is generated in both the tab 122 and the well 121 due to the P / N junction formed between the tab 122 and the well (that is, the substrate) 121. Thus, depletion region 122b and non-depletion region 122a are created in tub 122, and depletion region 121b and non-depletion region 121a are created in the substrate or tub 121.
[0106]
As shown in FIG. 11A, the tub region 122 extends from the floor of the trench to the P / N junction between the tub 122 and the well 121 at the interface between the depleted regions 122b and 121b. Completely depleted. Accordingly, the width is limited to the lower side of the trench 134 and the width L of the trench is set. _d And the thickness is below the trench and the width of the trench L _d A uniform channel 140 is created. For this reason, when the threshold voltage of the field effect transistor is applied to the gate electrode 128, the carrier of the second conductivity type becomes the third depth X under the trench 134 in the tub region 122. _Three Flows through. Further, when the second conductivity type carrier is applied to the gate electrode 128 with a voltage exceeding the threshold voltage of the field effect transistor, the carrier flows through the tub region 122 below the trench 134 and the third depth. Sa X _Three From the first depth X _i Extending towards. The length of the channel 140 is the width L of the trench. _d And the first depth X _i And the second depth X _j Is irrelevant to the difference between
[0107]
In sharp contrast, for the conventional trench MOSFET of FIG. 11B, the channel length is generally: _eff It is a function based on ≒ W + 2D, which is strongly influenced by the depth of the trench. Where L _eff Is the effective channel length, W is the width of the trench, and D is the depth of the trench beyond the source and drain depths. Thus, a small change in trench depth results in a relatively large change in the effective channel length in a conventional MOSFET, but only a small change in the threshold voltage of a trench-gate Fermi-FET. . This can provide significantly greater processing stability than can be obtained with conventional MOSFETs.
[0108]
As described above, N-channel and P-channel trench gated Fermi-FETs can be integrated into an integrated substrate to provide high performance CMOS applications for logic memories, microprocessors and / or other applications. . Moreover, trench gated Fermi-FETs are well suited for lateral power devices, including power amplifiers, which can be particularly well adapted for high frequency, high power operation. In these lateral transistors, the width and doping level of the undepleted portion 122a of the tub 122 under the drain region 124 are "tuned" to function as a vertical drift region having a graded concentration along the current path. Can be. Therefore, it is not necessary to provide a single conductivity step junction between the source 123 and the tub 122 and between the drain 124 and the tub 122. The drain region, combined with the large effective mobility of the channel of the Fermi-FET, provides a high breakdown voltage, low on-resistance and an RF having an operating frequency typically associated with more exotic semiconductors such as gallium arsenide. They can be combined to make a power amplifier.
[0109]
[Manufacturing process of trench gate type Fermi FET]
The manufacturing process for forming a trench gate Fermi-FET transistor will now be described. As shown below, the manufacturing process for making a trench gated Fermi-FET can be significantly shorter and / or simpler than that used to form a conventional MOSFET and / or Fermi-FET. One reason the process can be shortened and / or simplified is that the structure of the gate can be made after other doping has taken place. This allows the gate, source, drain and channel to be self-aligned.
[0110]
12A to 12F are cross-sectional views of a trench-gate Fermi-FET according to an embodiment of the present invention during an intermediate manufacturing stage according to the embodiment of the present invention. The fabrication of an N-channel trench gated Fermi-FET is illustrated. However, by inverting the conductivity type, a P-channel trench gate Fermi-FET can also be formed.
[0111]
Referring now to FIG. 12A, a P-type substrate 133 such as a single crystal silicon substrate or a silicon-on-insulator substrate is provided. An initial oxide layer 202 or other insulating layer is formed using conventional techniques. A mask 204, such as a photoresist layer, is patterned to define the location of the transistor. Conventional field oxide and / or trench insulation is also provided. The mask 204 defines a buried window into which the various ions 210 are implanted, as described below.
[0112]
Referring still to FIG. P wells 121 are formed by implanting P ions. N ions are implanted and N ^- Forming tabs 122 ', N ⁺ The source or drain region 125 is formed by implanting ions. Since the order of implantation to form regions 121, 122 'and 125 is arbitrary, for example, source or drain region 125 may be implanted before tub region 122', and either or both of these regions may be wells It will be appreciated that the implant can be performed before forming the region 121. It will also be understood that the well region 121 need not be formed when manufacturing an N-channel trench gate Fermi-FET using a P-type substrate. Injection techniques are well known to those skilled in the art and need not be described further herein. As shown in FIG. 12A, implantation of the source or drain region 125 is performed at an inclination angle θ from a vertical plane, which will be described later in detail.
[0113]
Reference is now made to FIG. The mask 204 is removed and an optional silicon nitride layer 206 is formed using conventional techniques. Next, a second patterned mask 208, such as a second photoresist layer, is formed to define a trench. Next, as shown in FIG. 12C, the nitride layer 206 is etched using the mask 208. Next, trench 134 is formed using nitride layer 206 as a mask. The trench 134 is etched through the source or drain region 125 to form spaced source and drain regions 123 and 124 and partially etched into the tub region 122 to a depth Y ₀ To form
[0114]
Thus, trenches and gates are formed after implanting the source or drain, tub, and well. Therefore, the implantation 210 can be completed before the gate structure is created, so that a high concentration of N ⁺ Implantation can be performed to form source or drain regions 125 using large tilt angles θ of greater than about 15 °. For this reason, compared to a process in which a gate electrode is manufactured and then self-aligned source and drain regions are formed using the gate electrode, shallow and steep source or drain regions 123 and 124 are formed. be able to. In conventional processes, a large tilt angle θ desired to provide shallow and steep source or drain regions can result in misalignment between the source and drain regions and the gate. In sharp contrast, in order to form trenches 134 and gates following the formation of the source or drain regions, FIG. 125 can be formed. The tab regions 122 ′ and / or the wells 121 may be formed using a small tilt angle or no tilt angle.
[0115]
To optimize the Fermi-FET performance based on equation (5), the trench depth X _Three Need to be adapted to the buried profile of the source 123, drain 124 and tub 122. Since it is somewhat difficult to predict the actual implantation profile theoretically, a test wafer containing an implant and a thermal step is made and then etched into the surface of the wafer by a known amount to obtain a trench depth X _Three Can be adapted to the actual embedding profile. These samples can then be measured and determined using capacitance-voltage (CV) techniques, as described below.
[0116]
Referring now to FIG. 12D, a gate insulating layer 126 is formed. This gate insulating layer 126 is formed using conventional thermal oxidation techniques and / or conventional chemical vapor deposition techniques to form a layer of silicon dioxide. Multi-layer oxide materials can also be used. Other gate insulating layers such as silicon nitride can also be used. In addition, an exotic dielectric material, such as a high dielectric constant material including a ferroelectric material such as PZT, is also used since the high temperature anneal was already performed in connection with FIGS. 12A-12C. It is possible, but not limited to these materials. As those skilled in the art are well aware, the properties of these materials are very sensitive to high temperatures. Since high temperature anneals have already been performed, they can be used for trench gated Fermi-FET transistors.
[0117]
Reference is now made to FIG. The gate electrode material 128 'is blanket-deposited and then etched back or planarized to form the gate electrode 128 of FIG. 12F. In some embodiments, tungsten is used for the gate electrode, deposited using conventional deposition techniques, and then planarized using chemical mechanical polishing (CMP), for example, using nitride layer 206 as a stop. Become
[0118]
As shown in FIG. 12F, the gate electrode 128 is recessed from the surface 121a of the substrate 133 by performing an over-etching and / or a separation etching process. As will be explained later, the gate electrode 128 minimizes the capacitance between the insulated gate electrode and the spaced source and drain regions 123 and 124 without reducing the drain current in the field effect transistor. It is preferable that the surface is depressed from the surface by the depth to be formed. Finally, the nitride and / or oxide layers 206 and 202 are removed and the insulating layer 142 and source and drain contacts 131 and 132 (FIG. 9) are formed using conventional techniques. In addition, upper and / or lower substrate contacts are also incorporated into this process using conventional techniques. The separation step of the device is also incorporated before or after the above-mentioned processing.
[0119]
Thus, after the anneal operation following the implant step of FIG. 12A, the high temperature steps can be reduced or preferably eliminated. Thus, many other gate dielectric materials can be used that cannot be easily used in conventional transistors.
[0120]
[Electrical simulation]
The structure file from the process simulation described above was used as input to an Atlas simulation program to simulate N-channel transistors. This simulation uses default mobility parameters and assigns a work function value of 4.63 eV to the gate material. In this example, tungsten was used. All other electrodes were defined as neutral.
[0121]
FIG. 13 shows the free carrier concentration present in a trench-gate Fermi-FET (left) embodiment and a conventional trench MOSFET (right) made using the same architecture with all electrode biases set to zero. The simulation result shown is shown. By comparing the two devices, the difference in channel length can clearly be recognized. In comparison of the electrical simulations, it should be understood that the conventional MOSFET does not include the drift region included in the Fermi-FET. However, this obviously serves to increase the drive current on the MOSFET side.
[0122]
14A and 14B graphically illustrate the drain current versus gate voltage characteristics of a simulated trench-gate Fermi-FET versus a simulated MOSFET using the same model parameters in log and linear form, respectively. 14A and 14B clearly illustrate the potential advantage of using a trench gated Fermi-FET architecture. If the threshold voltages match, despite the presence of a drift region in the Fermi-FET, the drive current of the MOSFET is only about 65% and the leakage current is about 30 times greater.
[0123]
In addition, trenches can dramatically enhance short channel effects commonly found in buried channel devices. This allows a significant reduction in capacity and the use of low threshold voltages, which makes it possible, for example, to produce high-performance radio-frequency devices.
[0124]
FIGS. 15A and 15B show the performance of the transistor in logarithmic and linear form for a simulated embodiment of a trench gated Fermi-FET. In this case, the drain voltage changes between 0.1V and 2.5V. The relative absence of short channel effects is clearly shown.
[0125]
16A and 16B graphically illustrate simulation results for a trench-gate Fermi-FET transistor as a function of gate insulation layer thickness change. In particular, FIGS. 15A and 15B show a gate insulator thickness of 4.0 nm, while FIGS. 16A and 16B show a gate insulator thickness of 5.0 nm. It is clearly shown that the threshold is independent of gate insulator thickness. No doping or a change in depth has occurred between the structures of FIGS. 15A and 15B and FIGS. 16A and 16B. Thicker dielectrics allow for higher operating voltages without having to change line width or doping. Again, it can be seen that there is no short channel effect.
[0126]
Both 2.5V and 3.3V trench gated Fermi FETs have extremely high breakdown voltages (BV) due to the transistor architecture. _dss ). By using a suitable gate dielectric, the BV _dss Can be a function of the P / N junction instead of the transistor architecture. Therefore, by appropriately configuring the P / N junction, extremely high breakdown performance can be achieved while maintaining a low threshold voltage. This can also make trench gated Fermi-FETs a desirable technology for power applications.
[0127]
FIG. 17A shows a simulation of a short channel trench-gate Fermi-FET transistor when the drain bias is set at the breakdown point. The outline shows free holes and free electrons, and the concentration of free carriers (10%) when breakdown begins for the 2.5V transistors of FIGS. 15A and 15B. ¹¹ cm ^-3 Above). The breakdown path from the drain to the substrate is clearly shown. The breakdown occurs at a drain electrode potential of 7.98 V, as shown in FIG. 17B. The terminal current at the time of breakdown indicates only the operation from the drain to the well, but the region where the electric field is maximum is immediately below the gate trench because the region where the electric field is maximized is near the well that is not depleted.
[0128]
The breakdown voltage of a trench-gate Fermi-FET transistor according to embodiments of the present invention can be increased, preferably maximized, using at least two techniques. First, the source and drain regions 123 and 124 (FIG. 9) should be sufficiently shallow so that a region of lightly doped N silicon can be present above the junction between tub 122 and well 121. What you can do. This can be achieved, if necessary, by performing low energy diffusion implantation at a large tilt angle θ with respect to the source or drain region 125 (FIG. 12A). Because the gate structure is made after diffusion, large tilt angles are possible, so that shadowing need not be considered.
[0129]
A second way to increase the breakdown voltage is to make the gate dielectric thicker. Thicker dielectric films can maintain the peak electric field below the wear-out level. Thicker dielectrics can be used without having to change other device parameters since the threshold is relatively independent of dielectric thickness.
[0130]
[Experimental optimization of trench depth and gate recess]
Using the simulations described above, it is possible to improve and preferably optimize the performance of a trench gated Fermi-FET according to embodiments of the present invention by adjusting the implant dose and energy and the first through third depths. it can. However, it will be appreciated that in making a real device, it is difficult to make this optimization because the real injection profile does not exactly match the real profile used in the simulation. This will cause performance to deviate from equation (5) due to the balance between the two oppositely doped implantation profiles.
[0131]
In view of this potential difficulty, an experimental technique is described herein that balances implant parameters with actual trench depth in silicon so that complexity in process development efforts can be reduced. In fact, the implantation and depth values can reach the values in the simulation, as described above. The correction can then be performed on the actual silicon using the techniques described herein.
[0132]
In particular, a test wafer can be manufactured based on the processes described with reference to FIGS. 12A to 12F without performing the etching step of FIG. 12C. Next, the etching of the trench of FIG. 12C is performed over the entire wafer, and stops at various positions at various positions on the entire wafer. Subsequent to this step, the gate dielectric is grown or deposited, and then gate electrodes are added and patterned, thereby creating an array of capacitors. Patterning is performed using conventional techniques. 18A-18E illustrate various stages of etching performed in a single wafer and / or a series of wafers. As the etched depth of the wafer surface increases, the depth of the P / N junction of FIG. 11A decreases and the doping of the source or drain layer 125 decreases as the heavily diffused portions are etched away.
[0133]
The operation of the capacitance versus voltage (CV) plot as a function of the amount of etching depends on the electrode edge to area ratio. 19A and 19B show simulations of a large area capacitor and a small area capacitor, respectively. The desired etching amount can be obtained from FIGS. 19A and 19B.
[0134]
In particular, considering the curves in FIGS. 19A and 19B, it can be seen that the trench etch depth is appropriate for the particular implant and thermal cycle set actually used. For example, examining the large area vs. perimeter curve of FIG. 19A, it can be seen on the right side of the graph that there is an initial decrease in capacitance with increasing etch depth. However, the capacitance on the left side (negative voltage side) of the graph is C _ox It has stopped at. As the etching depth is increased, the capacitance on the positive voltage side becomes minimum and starts increasing. Further etching does not increase the capacity on the positive voltage side, but the capacity on the negative voltage side is C _ox Drop rapidly below. An optimal transistor can be obtained by stopping the etching just before the negative capacitance starts to decrease. In FIG. 19A, it can be seen that the trench depth of the optimized Fermi-FET is 150 nm. Simulation of the electric field of the oxide at the threshold of this device shows a vertical component of less than 700 V / cm.
[0135]
Analysis of small area versus peripheral capacitors (FIG. 19B) shows that the operation is slightly different. However, further optimization of the trench depth can be performed. As shown in FIG. 19A, the initial etching effect is a decrease in capacity as the etching depth increases, on the right side of the graph. If the etching is further continued, the capacity becomes the lowest on the right side. As the etch continues, this positive volume quickly reaches a maximum and becomes constant. Further etching does not increase the positive side capacitance, but the negative side rapidly increases the capacitance. _ox Lower than. An optimal transistor can be obtained by stopping the etch as soon as the positive capacitance reaches a maximum and the negative capacitance begins to fall. Again, the optimal trench depth is 150 nm. This is consistent with the minimum inversion capacitance curve.
[0136]
In summary, the trench depth is the maximum depth at which capacitance can be maximized on the negative side of the capacitance / voltage plot measured on a test capacitor having the same dielectric and gate electrode materials used in the actual transistor. Determined by seeking
[0137]
As described above, the gate electrode 128 (FIG. 9) is preferably recessed from the surface 121a. The gate is preferably recessed from the surface to a depth that minimizes the capacitance between the insulated gate electrode and the spaced source and drain regions without reducing the drain current in the field effect transistor. . A method for determining a potentially optimal amount for recessing a gate electrode will now be described.
[0138]
In particular, for high speed operation, the preference is to reduce all capacitance, and more preferably to minimize it. The capacitance of the diffusion region is N ⁺ : P instead of N: P, the diffusion region can be minimized by keeping it steep in the depth direction. This is done as part of the breakdown voltage optimization. The gate-to-well capacitance has already been reduced due to the deep charge center of gravity at which the Fermi-FET transistor operates. Thus, the remaining item to be optimized is the overlapping capacitance between the gate electrode 128 and the source and drain regions 123,124.
[0139]
A series of simulations were performed using various amounts of gate etchback after planarization using a nominal 3.3V version of the device. The depth of the gate recess is X in FIG. _j -X ₀ Is defined as Qualitatively, the depth of the recess is measured from the top surface of the trench after mechanically planarizing the gate material to match the top surface of the substrate.
[0140]
FIG. 20A is a simulated capacitance vs. voltage plot of a simulated transistor using gate recesses of various depths. The drain current versus gate voltage performance of each of these transistors is shown in FIG. 20B. Referring to FIG. 20A, the parasitic capacitance can be optimized by selecting the device with the deepest recess before the drive current of FIG. 20B begins to drop due to the increased on-resistance. In FIGS. 20A and 20B, this corresponds to a 60 nm etchback. Note that the overall height of the electrode before etchback is 150 nm. For small etch-back quantities that can provide optimal performance, the difference between the gate contact height and the contact height with the diffusion region is not important in most processes, so special equipment must be built for contact etching There is no.
[0141]
FIGS. 21A and 21B show the final net doping and actual P-type and N-type doping profiles of a device optimized according to the method described above, respectively.
[0142]
[Conclusion]
Trench-gate Fermi-FETs according to embodiments of the present invention are particularly well-suited for short-channel CMOS devices using, for example, line widths of 1/10 micron or less. Trench-gate Fermi-FETs according to embodiments of the present invention are also particularly well suited for high power and / or high speed linear applications such as those used in RF amplifiers.
[0143]
The trench gate Fermi-FET according to the embodiment of the present invention can be manufactured using a very simplified process. There is no need to use halos, extensions and extensive channel engineering. The effects of short channels can be greatly reduced. Extremely shallow source and drain profiles can be made with large tilt angles, but they are not required. The source and drain parasitic capacitance can be reduced, and a high breakdown voltage can be provided. Further, the reliability of the breakdown path can be increased because the breakdown path enters the bulk silicon instead of the gate dielectric.
[0144]
In the drawings and specification, there have been disclosed exemplary preferred embodiments of the present invention. Certain terms are used, but those terms are general and used only for description, and not for purposes of limitation. The scope of the invention is set forth in the following claims.
[Brief description of the drawings]
[0145]
FIG. 1 is a cross-sectional view of an N-channel large-current Fermi-FET according to US Pat. No. 5,374,836.
FIG. 2A is a cross-sectional view of a first embodiment of a short-channel, low-leakage-current Fermi-FET according to US Pat. No. 5,374,836.
FIG. 2B is a cross-sectional view of a second embodiment of a short channel, low leakage current Fermi-FET according to US Pat. No. 5,374,836.
FIG. 3 is a cross-sectional view of an N-channel shaped tabbed Fermi-FET according to US Pat. No. 5,543,654.
FIG. 4 is a cross-sectional view of an N-channel short-channel Fermi-FET according to US Pat. No. 5,543,654.
FIG. 5 is a cross-sectional view of a second embodiment of an N-channel short channel Fermi-FET according to US Pat. No. 5,814,869.
FIG. 6 is a cross-sectional view of a first embodiment of a vinyl FET according to US Pat. No. 5,698,884.
FIG. 7 is a cross-sectional view of a second embodiment of a vinyl FET according to US Pat. No. 5,698,884.
FIG. 8 is a cross-sectional view of an embodiment of a metal gated Fermi-FET according to published PCT application WO 99/17371.
FIG. 9 is a sectional view of a trench gate type Fermi-FET according to an embodiment of the present invention.
10A and 10B graphically illustrate the applied gate bias vs. the field of the gate insulator for a trench-gate Fermi-FET according to an embodiment of the present invention and a conventional surface channel transistor embodiment, respectively. is there.
11A and 11B are cross-sectional views of trench-gate Fermi-FET transistors according to embodiments of the present invention and a conventional FET embodiment, respectively, illustrating and contrasting channel formation therein.
12A to 12F are cross-sectional views of a trench gated Fermi-FET according to an embodiment of the present invention during intermediate manufacturing steps according to an embodiment of the present invention.
FIG. 13 is a diagram showing a simulation result of a free carrier concentration existing in the embodiment of the present invention and the embodiment of the trench gate type Fermi-FET using the conventional FET.
FIGS. 14A and 14B are drain current versus gate voltage characteristics of a simulated trench gate Fermi FET versus a simulated conventional FET, respectively, in logarithmic and linear forms according to an embodiment of the present invention. FIG.
15A and 15B are diagrams illustrating the characteristics of a transistor in a logarithmic form and a linear form, respectively, for a simulated trench-gate Fermi-FET according to an embodiment of the present invention.
FIGS. 16A-16B graphically illustrate simulation results for a trench-gate Fermi-FET transistor according to an embodiment of the present invention as a function of a change in gate insulating layer thickness.
FIG. 17A is a diagram showing a simulation of a short-channel trench-gate Fermi-FET transistor according to an embodiment of the present invention when a drain bias is set to a breakdown point. FIG. 17B is a diagram illustrating drain leakage current versus drain bias voltage characteristics for the simulated transistor of FIG. 17A.
FIGS. 18A-18E illustrate etching occurring in a single wafer and / or a series of wafers to experimentally determine trench depth values, in accordance with an embodiment of the present invention. FIGS. 3 is a sectional view of various stages of FIG.
FIGS. 19A and 19B graphically illustrate capacitance vs. voltage plots as a function of the etch depth of FIGS. 18A-18E for large area capacitors and small area capacitors, respectively, according to embodiments of the present invention. FIG.
FIG. 20A shows a simulated capacitance versus voltage plot of a trench gated Fermi-FET according to an embodiment of the present invention with different gate depressions. FIG. 20B shows a plot of simulated drain current versus gate bias for the transistor simulated in FIG. 20A.
FIG. 21A shows the final net doping and actual P-type and N-type doping profiles of a trench-gate Fermi-FET, respectively, according to embodiments of the present invention. FIG. 21B illustrates the final net doping and actual P-type and N-type doping profiles of a trench gated Fermi-FET according to an embodiment of the present invention, respectively.

Claims (91)

A semiconductor substrate of a first conductivity type having a surface;
A second conductivity type tab region extending into the semiconductor substrate from the surface to a first depth and at the surface in the semiconductor substrate;
A source and drain region at the surface in the tub region of the second conductivity type and spaced apart from the tub region of the second conductivity type by a second conductivity type with the tub region of the second conductivity type; Source and drain regions, which form a single conductive junction of and extend into the tub region to a second depth less than the first depth;
A third depth deeper than the second depth but less than the first depth in the tub region from the surface into the tub region between the spaced source and drain regions; A trench extending to
An insulated gate electrode in the trench;
A field effect transistor comprising source and drain electrodes in electrical contact with the source and drain regions, respectively. 2. The method of claim 1, wherein at least one of the first, second, and third depths is selected such that an electrostatic field perpendicular to the surface at the third depth is zero. Field effect transistor. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to be zero. At least one of the first, second and third depths is selected so as to generate a threshold voltage of twice the Fermi potential of the semiconductor substrate for the field effect transistor. The field-effect transistor according to claim 1. When the threshold voltage of the field effect transistor is applied to the gate electrode at least one of the first, second and third depths, the trench having the third depth is formed in the tub region. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to allow carriers of a second conductivity type to flow underneath. When a voltage exceeding a threshold voltage of the field effect transistor is applied to the gate electrode, at least one of the first, second, and third depths is below the trench, and the third The field effect of claim 1, wherein the field effect is selected to allow the carrier of the second conductivity type to flow into the tub region extending from a depth to the first depth. Transistor. At least one of the first, second and third depths is selected to form a channel in the tub region at the third depth below the trench. The field-effect transistor according to claim 1. The trench forms a trench width, wherein at least one of the first, second and third depths is within the tub region and below the trench, wherein a channel width is proportional to the trench width; The field effect transistor of claim 1, wherein the field effect transistor is selected to form a channel that is independent of a difference between the first depth and the second depth. At least one of the first, second, and third depths is selected to deplete the tub region under the trench from the third depth to the first depth. The field-effect transistor according to claim 1, wherein: Wherein the trench includes a trench floor surface, the insulated gate includes an insulating layer having a thickness on the trench floor surface, and a gate electrode on the insulating layer opposite the trench floor surface; At least one of the second and third depths is selected to produce a threshold voltage for the field effect transistor that is independent of the thickness of the insulating layer on the trench floor. The field-effect transistor according to claim 1. The trench forms a trench width, and at least one of the first, second, and third depths is below the trench when a threshold voltage of the field effect transistor is applied to the gate electrode. The tub region of claim 1, wherein the channel is limited and is selected to form a channel in the tub region that extends over the trench width and has a uniform thickness over the trench width below the trench. Field effect transistor. The third depth is given by the following equation:

Shallower than said first depth by an amount equal to
Here, N _d is the doping concentration of the tub region, N _a is the doping concentration of the semiconductor substrate, N _i-specific carrier concentration of the substrate at temperature T degrees Kelvin, epsilon _s is the dielectric constant of the substrate, q is 1 2. The field effect transistor of claim 1, wherein 0.6 x ^10-19 coulombs and k is 1.83 x ^10-23 Joules / Kelvin. The semiconductor substrate of the first conductivity type is a well region of the first conductivity type in the substrate of the second conductivity type on the surface, and the tab region of the second conductivity type is provided on the surface of the substrate. 3. The field effect transistor of claim 1 wherein said transistor is in said well region and extends from said surface to said first depth in said well region. The field effect transistor according to claim 1, wherein the insulated gate electrode is in the trench and recessed from the surface. The insulated gate electrode is within the trench and provides a capacitance between the insulated gate electrode and the spaced source and drain regions without reducing drain current in the field effect transistor. 15. The field effect transistor of claim 14, wherein said transistor is recessed from said surface by an amount that minimizes The first, second, and / or third depths are selected to produce an electrostatic field of less than 700 volts per centimeter perpendicular to the surface at the third depth. The field-effect transistor according to claim 1. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field of less than 700 volts per centimeter. At least one of the first, second, and third depths is at least one order of magnitude greater than an electrostatic field generated by a field effect transistor that does not include the tub region and is perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate a small electrostatic field. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field at least one order of magnitude smaller than that generated by the field effect transistor not including the tub region. At least one of the first, second, and third depths is less than half the electrostatic field generated by a field effect transistor perpendicular to the surface at the third depth and not including the tub region. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate a static electric field. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field that is less than half the electrostatic field generated by the field effect transistor that does not include the tub region. At least one of the first, second and third depths is less than 1/5 of an electrostatic field generated by a field effect transistor perpendicular to the surface at the third depth and not including the tub region. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate a static electric field. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field less than one-fifth of an electrostatic field generated by the field effect transistor not including the tub region. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And the at least one of the first and second doping concentrations is selected to produce a zero electrostatic field perpendicular to the surface at the third depth. Field effect transistor. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And wherein at least one of the first and second doping concentrations is such that, when a threshold voltage of the field effect transistor is applied to the insulated gate electrode, a zero perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And at least one of said first and second doping concentrations is selected to generate a threshold voltage for said field effect transistor that is twice the Fermi potential of said semiconductor substrate. Item 2. The field effect transistor according to Item 1. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And when at least one of the first and second doping concentrations applies a threshold voltage of the field effect transistor to the gate electrode, the buried region is located below the trench having the third depth in the tub region. The field effect transistor according to claim 1, wherein the field effect transistor is selected such that carriers of the second conductivity type can flow to the side. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And wherein the first and / or second doping concentrations are selected to produce an electrostatic field of less than 700 volts per centimeter perpendicular to the surface at the third depth. Item 2. The field effect transistor according to Item 1. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And when at least one of the first and second doping concentrations applies a threshold voltage of the field effect transistor to the insulated gate electrode, a centimeter perpendicular to the surface at the third depth. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate less than 700 volts per electrostatic field. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And at least one of the first and second doping concentrations is at least an order of magnitude smaller than an electrostatic field generated by a field effect transistor perpendicular to the surface at the third depth and not including the tub region. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electric field. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And when at least one of the first and second doping concentrations applies a threshold voltage of the field effect transistor to the insulated gate electrode, the third depth is perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field at least one order of magnitude smaller than that generated by a field effect transistor that does not include a tab region. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And when a voltage exceeding at least one of the first and second doping concentrations exceeds a threshold voltage of the field effect transistor to the gate electrode, the third depth is below the trench. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to allow carriers of a second conductivity type to flow into the tub region extending from the first depth to the first depth. The semiconductor substrate is doped with a first doping concentration of a first conductivity type, the tub region is doped with a second doping concentration of a second conductivity type, and the first, second, and third depths are different. And wherein the first and / or second doping concentrations are selected to form a channel in the third depth tub region below the trench. 2. The field-effect transistor according to 1. The trench defining a trench width, the semiconductor substrate doped with a first doping concentration of a first conductivity type, the tub region doped with a second doping concentration of a second conductivity type, At least one of the second and third depths and the first and second doping concentrations have a channel width in the tub region below the trench that is proportional to the trench width; 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to form a channel that is independent of a difference between the first depth and the second depth. The semiconductor substrate is doped to a first conductivity type with a first doping concentration, the tub region is doped to a second conductivity type with a second doping concentration, and the first, second and third depths are doped. And wherein at least one of the first and second doping concentrations is selected to deplete the tub region from the third depth to the first depth below the trench. The field effect transistor according to claim 1, wherein The trench includes a trench floor, the insulated gate includes an insulating layer having a thickness on the trench floor, and a gate electrode on the insulating layer opposite to the trench floor, wherein the semiconductor substrate is The tub region is doped to a first conductivity type with a first doping concentration, the tub region is doped to a second conductivity type with a second doping concentration, and the first, second and third depths and the first And / or at least one of the second doping concentrations is selected to produce a threshold voltage for the field effect transistor that is independent of the thickness of the insulating layer on the trench floor. The field effect transistor according to claim 1. The trench defining a trench width, the semiconductor substrate doped with a first doping concentration of a first conductivity type, the tub region doped with a second doping concentration of a second conductivity type, At least one of the second and third depths and the first and second doping concentrations are limited to a lower side of the trench when a threshold voltage of the field effect transistor is applied to the gate electrode. 2. The field effect of claim 1, wherein the field effect is selected to form a channel in the tub region extending across the trench width and having a uniform thickness over the trench width below the trench. Transistor. The semiconductor substrate is doped to a first conductivity type with a first doping concentration, the tub region is doped to a second conductivity type with a second doping concentration, and the first, second and third depths are doped. And wherein at least one of the first and second doping concentrations is less than half the electrostatic field generated by the field effect transistor perpendicular to the surface at the third depth and not including the tub region. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electric field. The semiconductor substrate is doped to a first conductivity type with a first doping concentration, the tub region is doped to a second conductivity type with a second doping concentration, and the first, second and third depths are doped. And when at least one of the first and second doping concentrations applies a threshold voltage of the field effect transistor to the insulated gate electrode, the third depth is perpendicular to the surface at the third depth. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field that is less than half the electrostatic field generated by a field effect transistor that does not include a tab region. The semiconductor substrate is doped to a first conductivity type with a first doping concentration, the tub region is doped to a second conductivity type with a second doping concentration, and the first, second and third depths are doped. And wherein at least one of the first and second doping concentrations is less than 1/5 of an electrostatic field generated by a field effect transistor perpendicular to the surface at the third depth and not including the tub region. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electric field. The semiconductor substrate is doped to a first conductivity type with a first doping concentration, the tub region is doped to a second conductivity type with a second doping concentration, and the first, second and third depths are doped. And when at least one of the first and second doping concentrations applies a threshold voltage of the field effect transistor to the insulated gate electrode, the third depth is perpendicular to the surface at the third depth. 2. The field effect transistor of claim 1, wherein the field effect transistor is selected to generate an electrostatic field that is less than one-fifth of an electrostatic field generated by a field effect transistor that does not include a tab region. Forming, on a surface, a second conductivity type tab region in the first conductivity type semiconductor substrate, the second conductivity type tab region extending from the surface to a first depth in the semiconductor substrate;
Forming a second conductive type single conductive junction with the second conductive type tab region and extending into the tub region to a second depth less than the first depth; Forming a source or drain region of a conductivity type at the surface in the tub region of the second conductivity type;
Deeper than the second depth but less than the first depth from the surface into the tub region in the source or drain region to form spaced source and drain regions; Forming a trench extending to a third depth;
Forming an insulated gate electrode in the trench;
Forming source and drain electrodes in electrical contact with the source and drain regions, respectively. 43. The method of claim 42, wherein forming the source or drain region precedes forming the tub region. 43. The method of claim 42, wherein forming the trench is followed by forming the source or drain region and forming the tub region. 43. The method of claim 42, wherein forming the insulated gate electrode precedes forming the source or drain region. 43. The method of claim 42, wherein forming the source or drain region comprises implanting ions of a second conductivity type into the semiconductor substrate at a large tilt angle. Forming the insulated gate electrode,
Covering the trench with an insulating layer;
Forming a gate electrode in said trench covered with said insulating layer. The method of forming the gate electrode,
Forming a gate electrode layer in the trench on the first surface;
Flattening said gate electrode layer to remove said gate electrode layer from said first surface. 49. The method of claim 48, wherein the step of planarizing is followed by a step of recessing the gate electrode from the surface. 50. The method of claim 47, wherein forming the gate electrode comprises forming a gate electrode in the trench covered with the insulating layer and recessed from the surface. Forming the trench by performing a series of capacitance versus voltage measurements on the series of sites having a tub region and a source or drain region etched into the series of sites by varying amounts; 43. The method of claim 42, wherein the method is performed after the step of experimentally determining a third depth. 43. The method of claim 42, wherein at least one of the first, second, and third depths is selected such that an electrostatic field perpendicular to the surface at the third depth is zero. the method of. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 43. The method of claim 42, wherein the electrostatic field has been selected to be zero. At least one of the first, second and third depths is selected so as to generate a threshold voltage of twice the Fermi potential of the semiconductor substrate for the field effect transistor. 43. The method according to claim 42. When a threshold voltage of the field effect transistor is applied to the gate electrode, at least one of the first, second, and third depths is below the trench at the third depth. 43. The method of claim 42, wherein a carrier of the second conductivity type has been selected to flow within the tub region. When a voltage exceeding a threshold voltage of the field effect transistor is applied to the gate electrode, at least one of the first, second, and third depths is below the trench, and the third 43. The method of claim 42, wherein said method is selected to allow said second conductivity type carrier to flow into said tub region extending from a depth to said first depth. At least one of the first, second and third depths is selected to form a channel in the tub region at the third depth below the trench. 43. The method of claim 42. The trench forms a trench width, and at least one of the first, second, and third depths is such that a channel width is proportional to the trench width in the tub region below the trench. 43. The method of claim 42, wherein said channel is selected to form a channel that is independent of a difference between said first depth and said second depth. At least one of the first, second, and third depths is selected to deplete the tub region under the trench from the third depth to the first depth. 43. The method of claim 42, wherein Wherein the trench includes a trench floor surface, the insulated gate includes an insulating layer having a thickness on the trench floor surface, and a gate electrode on the insulating layer opposite the trench floor surface; At least one of the second and third depths is selected to produce a threshold voltage for the field effect transistor that is independent of the thickness of the insulating layer on the trench floor. 43. The method according to claim 42. The trench forms a trench width, and at least one of the first, second, and third depths is below the trench when a threshold voltage of the field effect transistor is applied to the gate electrode. 43. The method of claim 42, wherein the channel is limited and is selected to form a channel in the tub region that extends over the trench width and has a uniform thickness over the trench width below the trench. Method. The third depth is given by the following equation:

Shallower than said first depth by an amount equal to
Here, N _d is the doping concentration of the tub region, N _a is the doping concentration of the semiconductor substrate, N _i-specific carrier concentration of the substrate at temperature T degrees Kelvin, epsilon _s is the dielectric constant of the substrate, q is 1 43. The method of claim 42, wherein 0.6 x ^10-19 coulombs and k is 1.83 x ^10-23 Joules / Kelvin. The semiconductor substrate of the first conductivity type is a well region of the first conductivity type in the surface of the substrate of the second conductivity type, and the tab region of the second conductivity type is provided on the surface of the substrate. 43. The method of claim 42, wherein the method is in the well region and extends into the well region from the surface to the first depth. A method of forming the gate electrode recessed from the surface, wherein the capacitance between the insulated gate electrode and the spaced source and drain regions is reduced without reducing drain current in the field effect transistor. 51. The method of claim 50, comprising forming a gate electrode recessed from the surface by an amount that minimizes. The first, second, and / or third depths are selected to produce an electrostatic field of less than 700 volts per centimeter perpendicular to the surface at the third depth. 43. The method of claim 42. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 43. The method of claim 42, wherein the method is selected to produce an electrostatic field of less than 700 volts per centimeter. At least one of the first, second, and third depths is at least one order of magnitude greater than an electrostatic field generated by a field effect transistor that does not include the tub region and is perpendicular to the surface at the third depth. 43. The method of claim 42, wherein the method is selected to generate a small electrostatic field. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 43. The method of claim 42, wherein the method is selected to produce an electrostatic field at least an order of magnitude less than that produced by the field effect transistor without the tab region. At least one of the first, second, and third depths is less than half the electrostatic field generated by a field effect transistor perpendicular to the surface at the third depth and not including the tub region. 43. The method of claim 42, wherein the method is selected to generate a static electric field of: When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 43. The method of claim 42, wherein said method is selected to produce an electrostatic field of less than one-half the electrostatic field produced by said field effect transistor without said tab region. At least one of the first, second and third depths is less than 1/5 of an electrostatic field generated by a field effect transistor perpendicular to the surface at the third depth and not including the tub region. 43. The method of claim 42, wherein the method is selected to generate a static electric field of: When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 43. The method of claim 42, wherein the method is selected to produce an electrostatic field that is less than 1/5 of the electrostatic field produced by the field effect transistor that does not include the tub region. A first conductivity type semiconductor substrate having a surface;
A second conductivity type tab region in the semiconductor substrate, wherein the second conductivity type tab region extends in the semiconductor substrate from the surface to a first depth;
Forming a single conductive junction of the second conductivity type with the tab region of the second conductivity type on the surface and in the tab region of the second conductivity type; A second conductivity type spaced source and drain region extending into the tub region to a shallow second depth;
A third depth greater than the second depth but less than the first depth from the surface into the tub region in the tub region between the spaced source and drain regions; A trench extending to
An insulated gate electrode in the trench;
A method of determining a third depth for a trench of a field effect transistor including source and drain electrodes in electrical contact with the source and drain regions, respectively, wherein the method comprises:
Forming a second conductivity type tab region in the first conductivity type semiconductor substrate on the surface, the second conductivity type tab region extending from the surface to the first depth in the semiconductor substrate;
A second conductive type forming a single conductive junction of a second conductivity type with the second conductive type tab region and extending into the tub region to a second depth less than the first depth; Forming a source or drain region of a mold at the surface in the tub region of the second conductivity type;
Etching a plurality of spaced apart portions of the source or drain region by a corresponding plurality of different amounts;
Forming an insulated gate electrode on the plurality of spaced portions by the corresponding plurality of different amounts to form a plurality of capacitors;
Obtaining a capacitance-voltage measurement for the plurality of capacitors;
Determining said third depth from said plurality of capacitance-voltage measurements. 74. The method of claim 73, wherein forming the source or drain region precedes forming the tub region. 74. The method of claim 73, wherein the plurality of spaced portions are a plurality of spaced portions on a single semiconductor substrate. 74. The method of claim 73, wherein said determining comprises determining a maximum thickness at which a maximum capacitance can be obtained at a negative voltage. Forming, on a surface, a second conductivity type tab region in the first conductivity type semiconductor substrate, which extends into the semiconductor substrate from the surface to the first depth;
Forming a second conductive type single conductive junction with the second conductive type tab region and extending into the tub region to a second depth less than the first depth; A mold extends between the spaced source and drain regions and the spaced source and drain regions and is deeper than the second depth but less than the first depth from the surface into the tub region. Forming a trench extending to a third depth in the surface of the second conductivity type tub region;
Forming an insulated gate electrode in the trench;
Forming source and drain electrodes on said surface in electrical contact with said source or drain regions, respectively. Forming the insulated gate electrode,
Covering the trench with an insulating layer;
Forming a gate electrode in said trench covered with said insulating layer. The method of forming the gate electrode,
Forming a gate electrode layer in the trench on the first surface;
Planarizing said gate electrode layer to remove said gate electrode layer from said first surface. 80. The method of claim 79, wherein the step of planarizing is followed by a step of recessing the gate electrode from the surface. 79. The method of claim 78, wherein forming the gate electrode comprises forming a gate electrode in the trench covered with the insulating layer and recessed from the surface. The step of forming the spaced source and drain regions and trenches includes forming a series of capacitor pairs on the series of sites having a tub region and source or drain regions etched into the series of sites by varying amounts. 78. The method of claim 77, wherein the method is performed after the step of experimentally determining the third depth by performing a voltage measurement. 78. The method of claim 77, wherein at least one of the first, second, and third depths is selected such that an electrostatic field perpendicular to the surface at the third depth is zero. the method of. When a threshold voltage of the field effect transistor is applied to the insulated gate electrode, at least one of the first, second, and third depths is perpendicular to the surface at the third depth. 78. The method of claim 77, wherein the electrostatic field has been selected to be zero. At least one of the first, second and third depths is selected so as to generate a threshold voltage of twice the Fermi potential of the semiconductor substrate for the field effect transistor. 78. The method of claim 77, wherein there is. When a threshold voltage of the field effect transistor is applied to the gate electrode, at least one of the first, second, and third depths is below the trench at the third depth. 78. The method of claim 77, wherein the method is selected to allow carriers of the second conductivity type to flow within the tub region. When a voltage exceeding a threshold voltage of the field effect transistor is applied to the gate electrode, at least one of the first, second, and third depths is below the trench, and 78. The method of claim 77, wherein said method is selected to allow said second conductivity type carrier to flow into said tub region extending from a depth to said first depth. At least one of the first, second and third depths is selected to form a channel in the tub region at the third depth below the trench. 78. The method of claim 77. The third depth is given by the following equation:

Shallower than said first depth by an amount equal to
Here, N _d is the doping concentration of the tub region, N _a is the doping concentration of the semiconductor substrate, N _i-specific carrier concentration of the substrate at temperature T degrees Kelvin, epsilon _s is the dielectric constant of the substrate, q is 1 78. The method of claim 77, wherein 0.6 x ^10-19 coulomb, and k is 1.83 x ^10-23 Joules / Kelvin. The semiconductor substrate of the first conductivity type is a well region of the first conductivity type in the substrate of the second conductivity type on the surface, and the tab region of the second conductivity type is 81. The method of claim 77, wherein at a surface, the well is in the well region and extends into the well region from the surface to the first depth. A method of forming the gate electrode recessed from the surface, wherein the capacitance between the insulated gate electrode and the spaced source and drain regions is reduced without reducing drain current in the field effect transistor. 82. The method of claim 81, comprising forming a gate electrode recessed from the surface by an amount that minimizes.

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