JP2004514960A5 - - Google Patents

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Publication number
JP2004514960A5
JP2004514960A5 JP2001585024A JP2001585024A JP2004514960A5 JP 2004514960 A5 JP2004514960 A5 JP 2004514960A5 JP 2001585024 A JP2001585024 A JP 2001585024A JP 2001585024 A JP2001585024 A JP 2001585024A JP 2004514960 A5 JP2004514960 A5 JP 2004514960A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2001585024A
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JP2004514960A (ja
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Priority claimed from US09/569,944 external-priority patent/US7523151B1/en
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Publication of JP2004514960A publication Critical patent/JP2004514960A/ja
Publication of JP2004514960A5 publication Critical patent/JP2004514960A5/ja
Pending legal-status Critical Current

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JP2001585024A 2000-05-12 2000-10-03 剰余演算を用いて計算を行う方法および装置 Pending JP2004514960A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/569,944 US7523151B1 (en) 2000-05-12 2000-05-12 Method and apparatus for performing computations using residue arithmetic
PCT/US2000/027221 WO2001088694A1 (en) 2000-05-12 2000-10-03 Method and apparatus for performing computations using residue arithmetic

Publications (2)

Publication Number Publication Date
JP2004514960A JP2004514960A (ja) 2004-05-20
JP2004514960A5 true JP2004514960A5 (ja) 2007-11-22

Family

ID=24277555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001585024A Pending JP2004514960A (ja) 2000-05-12 2000-10-03 剰余演算を用いて計算を行う方法および装置

Country Status (7)

Country Link
US (3) US7523151B1 (ja)
EP (1) EP1281118B1 (ja)
JP (1) JP2004514960A (ja)
AT (1) ATE347133T1 (ja)
AU (1) AU2000276258A1 (ja)
DE (1) DE60032181T2 (ja)
WO (1) WO2001088694A1 (ja)

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US8428103B2 (en) 2009-06-10 2013-04-23 Harris Corporation Discrete time chaos dithering
US8340295B2 (en) * 2009-07-01 2012-12-25 Harris Corporation High-speed cryptographic system using chaotic sequences
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US8379689B2 (en) * 2009-07-01 2013-02-19 Harris Corporation Anti-jam communications having selectively variable peak-to-average power ratio including a chaotic constant amplitude zero autocorrelation waveform
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US9712185B2 (en) * 2012-05-19 2017-07-18 Olsen Ip Reserve, Llc System and method for improved fractional binary to fractional residue converter and multipler
US9179406B2 (en) * 2012-10-17 2015-11-03 Qualcomm Incorporated Method and apparatus for enhanced sleep mode tiering to optimize standby time and test yield
RU2557444C1 (ru) * 2014-07-16 2015-07-20 Федеральное государственное бюджетное образовательное учреждение высшего образования "Вятский государственный университет" Устройство для сравнения чисел в системе остаточных классов на основе интервально-позиционных характеристик
US20170236855A1 (en) * 2014-08-05 2017-08-17 Sharp Kabushiki Kaisha Method of producing imaging panel, imaging panel, and x-ray imaging device
US10901836B2 (en) * 2016-09-16 2021-01-26 University Of Southern California Systems and methods for mitigating faults in combinatory logic
US10387122B1 (en) 2018-05-04 2019-08-20 Olsen Ip Reserve, Llc Residue number matrix multiplier
US10992314B2 (en) * 2019-01-21 2021-04-27 Olsen Ip Reserve, Llc Residue number systems and methods for arithmetic error detection and correction
US11029920B1 (en) 2020-10-21 2021-06-08 Chariot Technologies Lab, Inc. Execution of a conditional statement by an arithmetic and/or bitwise unit
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