ATE347133T1 - Verfahren und anordnung zur ausführung von berechnungen mit residuenarithmetik - Google Patents

Verfahren und anordnung zur ausführung von berechnungen mit residuenarithmetik

Info

Publication number
ATE347133T1
ATE347133T1 AT00965559T AT00965559T ATE347133T1 AT E347133 T1 ATE347133 T1 AT E347133T1 AT 00965559 T AT00965559 T AT 00965559T AT 00965559 T AT00965559 T AT 00965559T AT E347133 T1 ATE347133 T1 AT E347133T1
Authority
AT
Austria
Prior art keywords
residue
arthmetic
arrangement
computing
logic gates
Prior art date
Application number
AT00965559T
Other languages
English (en)
Inventor
Jonathon D Mellott
Original Assignee
Athena Group Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Athena Group Inc filed Critical Athena Group Inc
Application granted granted Critical
Publication of ATE347133T1 publication Critical patent/ATE347133T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/18—Conversion to or from residue codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Error Detection And Correction (AREA)
AT00965559T 2000-05-12 2000-10-03 Verfahren und anordnung zur ausführung von berechnungen mit residuenarithmetik ATE347133T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/569,944 US7523151B1 (en) 2000-05-12 2000-05-12 Method and apparatus for performing computations using residue arithmetic

Publications (1)

Publication Number Publication Date
ATE347133T1 true ATE347133T1 (de) 2006-12-15

Family

ID=24277555

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00965559T ATE347133T1 (de) 2000-05-12 2000-10-03 Verfahren und anordnung zur ausführung von berechnungen mit residuenarithmetik

Country Status (7)

Country Link
US (3) US7523151B1 (de)
EP (1) EP1281118B1 (de)
JP (1) JP2004514960A (de)
AT (1) ATE347133T1 (de)
AU (1) AU2000276258A1 (de)
DE (1) DE60032181T2 (de)
WO (1) WO2001088694A1 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006195563A (ja) * 2005-01-11 2006-07-27 Renesas Technology Corp 演算処理装置
FR2895605A1 (fr) * 2005-12-22 2007-06-29 Thomson Licensing Sas Procede de reception d'un signal a porteuses multiples, procede d'emission, recepteur et emetteur correspondants
US8312551B2 (en) 2007-02-15 2012-11-13 Harris Corporation Low level sequence as an anti-tamper Mechanism
US8611530B2 (en) 2007-05-22 2013-12-17 Harris Corporation Encryption via induced unweighted errors
US20090104357A1 (en) * 2007-10-17 2009-04-23 Dattilo Vincent P Mutli-layer composite coloring coating process
US8363830B2 (en) 2008-02-07 2013-01-29 Harris Corporation Cryptographic system configured to perform a mixed radix conversion with a priori defined statistical artifacts
US8320557B2 (en) 2008-05-08 2012-11-27 Harris Corporation Cryptographic system including a mixed radix number generator with chosen statistical artifacts
US8325702B2 (en) 2008-08-29 2012-12-04 Harris Corporation Multi-tier ad-hoc network in which at least two types of non-interfering waveforms are communicated during a timeslot
US8351484B2 (en) 2008-12-29 2013-01-08 Harris Corporation Communications system employing chaotic spreading codes with static offsets
US8406276B2 (en) 2008-12-29 2013-03-26 Harris Corporation Communications system employing orthogonal chaotic spreading codes
US8457077B2 (en) 2009-03-03 2013-06-04 Harris Corporation Communications system employing orthogonal chaotic spreading codes
US8428102B2 (en) * 2009-06-08 2013-04-23 Harris Corporation Continuous time chaos dithering
US8509284B2 (en) * 2009-06-08 2013-08-13 Harris Corporation Symbol duration dithering for secured chaotic communications
US8428103B2 (en) 2009-06-10 2013-04-23 Harris Corporation Discrete time chaos dithering
US8406352B2 (en) 2009-07-01 2013-03-26 Harris Corporation Symbol estimation for chaotic spread spectrum signal
US8385385B2 (en) 2009-07-01 2013-02-26 Harris Corporation Permission-based secure multiple access communication systems
US8369376B2 (en) 2009-07-01 2013-02-05 Harris Corporation Bit error rate reduction in chaotic communications
US8379689B2 (en) * 2009-07-01 2013-02-19 Harris Corporation Anti-jam communications having selectively variable peak-to-average power ratio including a chaotic constant amplitude zero autocorrelation waveform
US8363700B2 (en) * 2009-07-01 2013-01-29 Harris Corporation Rake receiver for spread spectrum chaotic communications systems
US8340295B2 (en) * 2009-07-01 2012-12-25 Harris Corporation High-speed cryptographic system using chaotic sequences
US8428104B2 (en) 2009-07-01 2013-04-23 Harris Corporation Permission-based multiple access communications systems
US8369377B2 (en) 2009-07-22 2013-02-05 Harris Corporation Adaptive link communications using adaptive chaotic spread waveform
US8848909B2 (en) 2009-07-22 2014-09-30 Harris Corporation Permission-based TDMA chaotic communication systems
US20110137969A1 (en) * 2009-12-09 2011-06-09 Mangesh Sadafale Apparatus and circuits for shared flow graph based discrete cosine transform
US8345725B2 (en) * 2010-03-11 2013-01-01 Harris Corporation Hidden Markov Model detection for spread spectrum waveforms
KR101171199B1 (ko) 2011-03-29 2012-08-06 경남대학교 산학협력단 Ｃｒｔ를 이용한 고속 승산 장치 및 방법
RU2503992C2 (ru) * 2011-09-27 2014-01-10 Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Северо-Кавказский федеральный университет" Устройство для сравнения чисел, представленных в системе остаточных классов
US9712185B2 (en) * 2012-05-19 2017-07-18 Olsen Ip Reserve, Llc System and method for improved fractional binary to fractional residue converter and multipler
US9179406B2 (en) * 2012-10-17 2015-11-03 Qualcomm Incorporated Method and apparatus for enhanced sleep mode tiering to optimize standby time and test yield
RU2557444C1 (ru) * 2014-07-16 2015-07-20 Федеральное государственное бюджетное образовательное учреждение высшего образования "Вятский государственный университет" Устройство для сравнения чисел в системе остаточных классов на основе интервально-позиционных характеристик
WO2016021472A1 (ja) * 2014-08-05 2016-02-11 シャープ株式会社 撮像パネルの製造方法、撮像パネル、及びｘ線撮像装置
EP3513293A4 (de) * 2016-09-16 2020-05-20 University Of Southern California Systeme und verfahren zur abschwächung von fehlern in kombinatorischer logik
US10387122B1 (en) 2018-05-04 2019-08-20 Olsen Ip Reserve, Llc Residue number matrix multiplier
US10992314B2 (en) * 2019-01-21 2021-04-27 Olsen Ip Reserve, Llc Residue number systems and methods for arithmetic error detection and correction
US11029920B1 (en) 2020-10-21 2021-06-08 Chariot Technologies Lab, Inc. Execution of a conditional statement by an arithmetic and/or bitwise unit
RU2747371C1 (ru) * 2020-10-22 2021-05-04 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Устройство определения знака числа, представленного в системе остаточных классов
US11669665B1 (en) * 2020-11-16 2023-06-06 Synopsys, Inc. Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization
RU2767450C1 (ru) * 2021-04-01 2022-03-17 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Способ определения знака числа в системе остаточных классов

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609328A (en) * 1968-12-19 1971-09-28 Bell Telephone Labor Inc Multiaperture ferrite residue arithmetic unit
US4107783A (en) * 1977-02-02 1978-08-15 The Board Of Trustees Of The Leland Stanford Junior University System for processing arithmetic information using residue arithmetic
US4281391A (en) 1979-01-15 1981-07-28 Leland Stanford Junior University Number theoretic processor
US4363106A (en) 1980-08-13 1982-12-07 Environmental Research Institute Of Michigan Computation module for addition and multiplication in residue arithmetic
US4506340A (en) 1983-04-04 1985-03-19 Honeywell Information Systems Inc. Method and apparatus for producing the residue of the product of two residues
US4709345A (en) 1985-04-04 1987-11-24 Harris Corporation Apparatus for executing Chinese remainder theorem for residue decoding through quotient-remainder conversion
JPS61271536A (ja) * 1985-05-27 1986-12-01 Matsushita Electric Ind Co Ltd 論理演算装置
GB8703136D0 (en) 1987-02-11 1987-03-18 Univ Cardiff Filtering electrical signals
AU2366588A (en) 1987-10-12 1989-04-13 Sony Corporation Method and apparatus for encoding and decoding data in residue number system
FR2622713A1 (fr) 1987-10-30 1989-05-05 Thomson Csf Circuit de calcul utilisant une arithmetique residuelle
US4948959A (en) * 1988-07-15 1990-08-14 The Boeing Company Optical computer including pipelined conversion of numbers to residue representation
JP2930325B2 (ja) 1989-07-29 1999-08-03 ソニー株式会社 ディジタル信号処理回路
US5077793A (en) * 1989-09-29 1991-12-31 The Boeing Company Residue number encryption and decryption system
US5107451A (en) 1990-01-30 1992-04-21 The Boeing Company Method and apparatus for pipelined detection of overflow in residue arithmetic multiplication
JPH05252045A (ja) 1992-03-04 1993-09-28 Sony Corp 剰余演算処理回路
US5424971A (en) 1992-11-12 1995-06-13 Vlsi Technology, Inc. Unsigned constant multiplier compiler
US5619535A (en) * 1994-07-27 1997-04-08 Alvarez, Jr.; Cesar E. Digital frequency synthesizer
US6195386B1 (en) * 1994-09-26 2001-02-27 Texas Instruments Incorporated Parallel decision feedback equalizer
US5987487A (en) * 1996-03-11 1999-11-16 Cirrus Logic, Inc. Methods and apparatus for the processing of digital signals
JP3615622B2 (ja) * 1996-06-28 2005-02-02 株式会社ルネサステクノロジ マイクロコンピュータ

Also Published As

Publication number Publication date
DE60032181D1 (de) 2007-01-11
US20100030832A1 (en) 2010-02-04
US8180821B2 (en) 2012-05-15
AU2000276258A1 (en) 2001-11-26
US20120284319A1 (en) 2012-11-08
EP1281118B1 (de) 2006-11-29
US8965943B2 (en) 2015-02-24
EP1281118A1 (de) 2003-02-05
DE60032181T2 (de) 2007-03-29
JP2004514960A (ja) 2004-05-20
US7523151B1 (en) 2009-04-21
WO2001088694A1 (en) 2001-11-22

Similar Documents

Publication Publication Date Title
ATE347133T1 (de) Verfahren und anordnung zur ausführung von berechnungen mit residuenarithmetik
NL1025106A1 (nl) Simd geheel getal vermenigvuldiging van de meest significante deel met afronden en schuiven.
WO2017192243A3 (en) Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
TW200703037A (en) Cryptographically secure modular polynomial reduction method and computational hardware for executing the same
DE60234187D1 (de) Vorrichtung und verfahren für die stereoskopische bildverarbeitung
ATE484790T1 (de) Verfahren und vorrichtung zum erzeugen von zufallsdaten
DE50114509D1 (de) Vorrichtung zur bestimmung des endes der verarbeitungszeit von härtbaren dentalmassen
KR980004018A (ko) 데이타 처리장치 및 마이크로컴퓨터
ATE346334T1 (de) Peripheriegerät für ein datenverarbeitungssystem
TW200520498A (en) Randomized modular reduction method and hardware therefor
ATE422278T1 (de) Verfahren und vorrichtung zum ermitteln eines schlüsselpaars und zum erzeugen von rsa-sclüsseln
WO2007020564A3 (en) Circuit arrangement and method for rsa key generation
ATE347268T1 (de) Fleischverarbeitungsmaschine mit fettanalysevorrichtung
DE69426801D1 (de) Multiplizierer zur Berechnung von einfacher Genauigkeit, doppelter Genauigkeit, innerem Produkt und zur Multiplikation von komplexen Zahlen in den Betriebsarten
BR0209779A (pt) Processo
ATE472769T1 (de) Verbesserte natürliche montgomery- exponentenmaskierung
DE602008002994D1 (de) Verfahren und Vorrichtung zur Aktivierung und Deaktivierung eines Sperrmodus auf einem tragbaren elektronischen Gerät
ATE419577T1 (de) Verfahren und einrichtung zur durchführung einer kryptographischen operation
AU2003250361A8 (en) Processor for performing arithmetic operations in composite operands
TW200506634A (en) Physical presence determination in a trusted platform
EP1818810A3 (de) Schaltkreis und Verfahren zur Vervielfältigung langer ganzzahliger Werte
TW200612329A (en) Galois field multiplier and multiplication method thereof
HUP0303485A2 (hu) PMI-szirupfázisok és alkalmazásuk oldhatatlan adalékok stabilizálására
FR2847056A1 (fr) Procede et systeme de traitement de donnees d'evaluation
Younes Residue number system based building blocks for applications in digital signal processing

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties